JP2005190289A - Memory controller, flash memory system therewith, and method for controlling flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory system that increases an allowable number for defective blocks to occur as a whole by lending a block that belongs to a certain zone to any zone where the number of defective blocks that have occurred has exceeded the allowable number. <P>SOLUTION: The memory controller includes: an allocation management function for managing the correspondence between a zone composed of a plurality of blocks within a flash memory and a logical block address space of a host system allocated to the zone; an access control function for controlling access to the zone; a borrower/lender management function for managing the correspondence between a lender's zone and a borrower's zone when the blocks are lent and borrowed between the zones; and an information setting function for setting, in the redundant area of the block lent, information showing that the blocks are being lent when data about the logical block address allocated to the borrower's zone are written. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called block erase.

  Therefore, when data is rewritten in the NAND flash memory, new data (data after rewriting) is written to the erased block which has been erased, and old data (data before rewriting) is written. A process of erasing the written block is generally performed. When data is rewritten in this way, the data after rewriting is written in a different block from before rewriting, so the correspondence between the logical block address given by the host system and the physical block address in the flash memory Changes dynamically every time data is rewritten. Therefore, in order to manage this correspondence, an address conversion table showing the correspondence between the logical block address and the physical block address is required.

  If this address translation table is created for all blocks in the flash memory, the size of the address translation table increases as the flash memory capacity increases. Or, the time burden increases. In order to solve this problem, in Patent Document 1 (Japanese Patent Laid-Open No. 2000-284996), the flash memory is divided into a plurality of zones, and an address conversion table is created for the blocks allocated to each zone.

In addition, in the flash memory system adopting the above zone, in consideration of the occurrence of a defective block, an extra block constituting the zone is added to the host system side address space (address space corresponding to a specific range of logical block addresses). Assigned.
JP 2000-284996 A

When a zone is configured with a plurality of blocks in the flash memory as described above, if the number of spare blocks (an extra allocated block in consideration of the occurrence of a bad block) allocated to each zone is increased, The ratio of spare blocks increases and the address space on the host system side that can be covered by the flash memory of the same capacity becomes narrower (hereinafter, the width of the address space on the host system side that can be covered by the flash memory of the same capacity is called usage efficiency). ). On the other hand, if the number of spare blocks allocated to each zone is reduced, the use efficiency of the flash memory is improved, but the allowable amount for the generation of defective blocks (the allowable number of defective blocks generated) decreases. Considering this, the number of preliminary blocks in each zone is determined. However, the number of defective blocks may exceed the allowable amount due to initial failure or defective block formation due to long-term use.

  Accordingly, the present invention provides a memory controller that improves the overall tolerance for the occurrence of defective blocks by lending blocks belonging to other zones to the zone where the number of occurrences of the defective blocks exceeds the tolerance. And a flash memory system including the memory controller, and a flash memory control method.

An object of the present invention is to provide an allocation management function for managing the correspondence between a zone composed of a plurality of blocks in a flash memory and a logical block address space on the host system side allocated to the zone,
An access control function for controlling access to the zone;
A loan management function for managing the correspondence between the zone on the lending side and the zone on the borrowing side when lending blocks between the zones; and
When the data of the logical block address assigned to the borrowing zone is written in the block lent out from the lent zone, the block is lent out in the redundant area of the lent block. This is achieved by a memory controller having an information setting function for setting information to be shown. The object of the present invention is also achieved by a flash memory system comprising the memory controller and a flash memory.

  Here, “lending / leaving a block between zones” means writing data of a logical block address assigned to one zone to a block in the other zone.

  Further, according to the present invention, it is preferable that information relating to the correspondence relationship between the lending side zone and the borrowing side zone is stored in a specific block in the flash memory by the lending management function.

  Here, the “information regarding the correspondence between the lending side zone and the borrowing side zone” includes a lending management table showing the correspondence between the lending side zone and the borrowing side zone.

  According to the present invention, it is preferable that a logical value set in a specific bit of the redundant area corresponds to the information indicating that the lending is performed.

  In other words, the data written to the block in the lending side zone is the data of the logical block address assigned to the borrowing side zone, or the logical block address assigned to the lending side zone. It is preferable that whether it is data can be determined by a logical value set in a specific bit.

  Further, according to the present invention, it is preferable that the lending management function determines a correspondence relationship between the lending side zone and the borrowing side zone based on information relating to the number of defective blocks for each zone.

  By doing so, it is possible to smoothly assign the lending-side zone with a small number of defective blocks to the borrowing-side zone with a large number of defective blocks.

  Further, according to the present invention, it is preferable that the information regarding the defective block in the rush memory is stored in a specific block in the flash memory by the loan management function.

  Here, the information regarding the bad block includes information indicated by the physical block address of the bad block.

  Further, according to the present invention, it is preferable that the information relating to the number of defective blocks for each zone is stored in a specific block in the flash memory by the loan management function.

An object of the present invention is to provide a flash memory that controls access from the host system side to the flash memory in accordance with a correspondence relationship between a logical block address space on the host system side and a zone composed of a plurality of blocks in the flash memory. Control method,
A process of writing data of a logical block address corresponding to the first zone to a block in the second zone assigned to the first zone in which a block to be written to cannot be secured; and in the second zone In the writing process to the block, data of the logical block address corresponding to the first zone is written in the redundant area of the block in which the data of the logical block address corresponding to the first zone is written. This is achieved by a flash memory control method including a process for setting information indicating the above.

  According to the present invention, since a block belonging to another zone is lent out to a zone in which the number of occurrences of defective blocks exceeds the allowable amount, the overall allowable amount for the generation of defective blocks can be improved. Can do. Also, since the above-mentioned workaround is prepared for the zone where the number of defective blocks exceeds the allowable amount, the ratio of spare blocks should be lowered to improve the usage efficiency of the flash memory. You can also.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data or the like is taken into the controller 3 using the host interface block 7 as an entrance, and the data or the like supplied from the flash memory system 1 to the host system 4 is sent to the host system 4 using the host interface block 7 as an exit. To be supplied.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14.

The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

  The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Connection state.

Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a user area 25 of 512 bytes and a redundant area 26 of 16 bytes. The user area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error collection code, a corresponding logical block address and a block status. It is an area.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set. [Description of logical block address and physical block address]
Since data cannot be overwritten in the flash memory, when rewriting data, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting). The process of erasing the block in which "." Has been written must be performed. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.
[Description of zone configuration]
The flash memory system according to the present invention employs a method of dividing an area in the flash memory into a plurality of zones, and each zone is composed of a plurality of blocks in the flash memory. FIG. 5 shows an example in which a zone is composed of 1024 blocks. In this example, the zone is composed of 1024 blocks B0000 to B1023, and each block is composed of 32 pages P00 to P31. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing. Note that the storage capacity of each block and the number of pages of each block differ depending on the specifications of the flash memory.

  This zone is assigned to a certain range of logical block address space. For example, in the example shown in FIG. 6, a zone composed of 1024 blocks is allocated to a space of 1000 blocks of logical block addresses. Here, the reason why the blocks constituting the zone are allocated to the extra 24 blocks is because of the occurrence of defective blocks. However, when data is rewritten and new data is once written to another block, and then the block where the old data has been written is erased, a spare block for writing the new data is necessary. In effect, an extra 23 blocks are allocated. The number of blocks constituting the zone is appropriately set according to the use of the flash memory system and the specification of the flash memory.

Also, when writing the corresponding logical block address to the redundant area of each block, the logical block address given from the host system side is written as it is, or the serial number in each logical block address space assigned to each zone (each If a zone is assigned to a logical block address space for 1000 blocks, a serial number from 0 to 999 may be written (hereinafter, a serial number in the logical block address space assigned to each zone is called a logical serial number. .) Here, the logical sequence number can be converted into an actual logical block address by adding an offset corresponding to each zone. For example, when the top address of the logical block address space assigned to zone 0 in FIG. 6 is ADD0, the following offset is assigned to each zone.
Zone 0: ADD0
Zone 1: ADD0 + 1000x1
Zone 2: ADD0 + 1000x2
・
・
・
Zone N: ADD0 + 1000 × N
Since the flash memory system according to the present invention lends blocks between zones as will be described later, a logical block assigned to a lending side zone is included in a redundant area of a block belonging to the lending side zone. The address and the logical block address assigned to the borrower's zone will be described. At this time, if only the logical sequence number assigned to each zone is described in the redundant area of the block belonging to the lending-side zone, the logical sequence number is the lending-side logical sequence number or borrowing only with that logical sequence number. It is not possible to determine whether it is a logical sequence number on the side. Therefore, when the logical serial number assigned to each zone is described in the redundant area of the block, it is necessary to set information indicating whether or not the block is lent out. When this information is set, for example, a specific bit in the redundant area may be assigned to the lending flag, and the logical value of the bit may indicate whether or not the block is lent.
[Explanation of block lending between zones]
In the flash memory system according to the present invention, when data in a logical block address space allocated to a zone is written, if a block to be written to cannot be secured in the zone, the block is borrowed from another zone. By doing so, the missing blocks are replenished. The combination of the loan-side zone and the borrowing-side zone when lending the block is preferably set as appropriate in consideration of the number of defective blocks generated.

  It should be noted that the combination of the lending-side zone and the borrowing-side zone is preferably set sequentially when a zone in which a writing destination block cannot be secured occurs. For example, when a zone in which a write destination block cannot be secured occurs, a zone having a small number of defective blocks may be sequentially assigned to the zone. However, in the vicinity of congenital defective blocks (defective blocks from the time of shipment), it is considered that there is a high probability of acquiring acquired defective blocks (defective blocks that occurred during use). A combination that matches the assigned zone and the zone assigned to the area with few congenital bad blocks is set in advance. May be performed.

  The correspondence between the lending-side zone and the borrowing-side zone is a table showing the correspondence (hereinafter, the table showing the correspondence between the lending-side zone and the borrowing-side zone is called a lending management table). .) Is preferably created and stored in a specific block in the flash memory. For example, in the loan management table shown in FIG. 7, the correspondence relationship is indicated by writing the zone number on the borrowing side and the zone number on the lending side together. When borrowing a block based on this table, for example, zone 0 borrows a block from zone 1, and zone 5 borrows a block from zone 4.

  In addition, when a zone in which a block to be written to cannot be secured occurs, and when a zone with a small number of bad blocks is assigned to the zone, the number of bad blocks in each zone or a bad It is preferable to store the physical block address of the block in a specific block in the flash memory. In this way, since the number of defective blocks in each zone can be easily grasped, the lending-side zone can be assigned smoothly.

  Next, an address conversion table used when accessing the flash memory will be described with reference to the drawings. FIG. 8 shows an example of an address conversion table on the borrowing side, and shows an address conversion table when a zone is composed of 1024 blocks and the zone is allocated to a logical block address space for 1000 blocks. ing. In this address conversion table, physical block addresses of blocks storing data corresponding to each logical block address are described in the order of logical block addresses.

  Here, when the physical block address is described, the actual address in the flash memory may be described. However, in order to reduce the area on the SRAM for creating the address conversion table, the physical block address is assigned in the order. In many cases, serial numbers (0 to 1023) in each zone are described (hereinafter, serial numbers assigned in the order of physical block addresses are referred to as physical serial numbers). In this case, since it is not possible to determine whether the block is borrowed only by the physical serial number on the address conversion table, a borrowing flag is provided in the address conversion table and the block is borrowed by this borrowing flag. It is preferable to indicate whether or not. For example, a bit indicating whether or not the block is borrowed may be provided, and a logical value (“0” or “1”) of this bit may indicate whether or not the block is borrowed. . In the borrower's address conversion table shown in FIG. 8, the borrowing flag is set to “0” when the block is not borrowed, and the borrowing flag is set to “1” when the block is borrowed.

The physical serial number (0 to 1023) can be converted into an actual address in the flash memory by adding an offset corresponding to each zone. For example, when blocks in the flash memory are assigned to zones 0 to N in the order of addresses, the following offsets are assigned to each zone.
Zone 0: 0
Zone 1: 1024x1
Zone 2: 1024x2
・
・
・
Zone N: 1024 x N
For a logical block address in which the corresponding data is not stored, data indicating that the corresponding data is not stored in the portion corresponding to the logical block address in the address conversion table, not the physical block address, for example, “111 1111 1111b (binary number)” is set.

  When creating the borrower's address conversion table shown in FIG. 8, for example, an area that can describe the borrowing flag and physical serial number (physical block address) for 1000 blocks is secured on the SRAM and borrowed as an initial setting. “0” (a flag indicating that the block is not borrowed) is set in the portion describing the flag, and “111 1111 1111b (binary number)” (indicating that no data is stored in the area describing the physical block address) Set the data shown). After that, the redundant area of the block assigned to the zone for creating the address conversion table (the borrower's zone) is read sequentially, and the logical sequence number indicating the logical block address is written in the portion describing the corresponding logical block address of the redundant area. If it is described, the physical serial number of the block in which the logical serial number is described is described in the part corresponding to the logical serial number (the part corresponding to the logical block address) of the address conversion table. By sequentially performing this process for the 1024 blocks constituting the zone, an address conversion table corresponding to the data stored in the borrower's zone is created.

  In the above process, the conversion table corresponding to the data stored in the block borrowed from the lending side zone is not created, so the following additional process is required. In this additional processing, a block (redundant area) of the lending side zone corresponding to the borrowing side zone is read, and a flag indicating that the lending is set is set in the bit assigned to the lending flag of the redundant area. (For example, if the logical value “0” is set when not rented, and if the logical value “1” is set when lent), then “1” is set).

  This additional processing will be described with reference to FIG. 9 showing the redundant area of the block on the lending side and the address conversion table on the borrowing side. In the redundant area of the block on the lending side, in the redundant area of the block with the physical sequence number 6, the flag “1” indicating that it is lent is set, and in the portion describing the corresponding logical block address, the logical sequence number 3 Is described. In other words, the block of the physical serial number 6 on the lending side stores the data of the logical block address space allocated to the zone on the borrowing side, and the logical serial number in the logical block address space is 3 (000 0000 0011b (binary number)). In the process of adding information on the borrowed block to the borrower's address translation table, the borrow flag corresponding to the logical serial number 3 of the borrower's address translation table is set to “1” and the physical block address is described Describes the physical serial number 6 (000 0000 0110b (binary number)). If the above-described additional processing is performed for all blocks in which the flag “1” indicating that lending is performed in the lending-side redundant area, the borrowing-side address conversion table is completed. If there is no block borrowed from the zone on the lending side, there is no need to perform the additional processing.

  When creating the address conversion table on the lending side, for example, an area where the physical block addresses for 1000 blocks can be described is secured on the SRAM, and “111 1111 1111b ( Binary)) ”(data indicating that no data is stored). After that, the redundant area of the block assigned to the zone for creating the address conversion table (lending side zone) is read sequentially, and the logical sequence number indicating the logical block address is written in the portion describing the corresponding logical block address of the redundant area. If it is described, the physical serial number of the block in which the logical serial number is described is described in the part corresponding to the logical serial number (the part corresponding to the logical block address) of the address conversion table. This processing is sequentially performed for blocks that are not lent in the zone (blocks that are set with a flag “0” indicating that they are not lent), thereby completing the address conversion table on the rent side.

  Next, processing for writing data in the logical block address space allocated to the borrowing zone to the block borrowed from the lending zone will be described. This write process is usually performed when a block (erased block or block in which valid data is not written) that is a data write destination cannot be secured in the borrowing zone. In addition, when a lending side zone is not set in a zone in which a writing destination block cannot be secured, the lending side zone is allocated with reference to the number of defective blocks in each zone.

  In this process, first, an erased block is searched for the lending side zone. In this search, for example, an erased block search table as shown in FIG. 10A is used. In this erased block search table, each block constituting the zone is associated with each bit on the SRAM, and data is written according to the logical value (“0” or “1”) of each bit. Or a state in which no data is written. Here, the bits on the erased block search table correspond to 1024 blocks (physical serial numbers 0 to 1023) constituting the zone. With respect to this correspondence, the bits on the erased block search table are associated with each other in the order of physical block addresses from the upper row to the lower row, and from the left to the right in the order of the physical block addresses. .) Therefore, the upper left bit of the erased block search table corresponds to the block having the physical sequence number 0, and the lower right bit corresponds to the block having the physical sequence number 1023.

  Further, the erased block search table shown in FIG. 10A indicates that data is written in a block corresponding to each bit on the erased block search table or that it is a defective block. When the block status is described, “0” is set to the bit, and when the data is not written (in the case of the erased block), “1” is set to the bit. The erased block search table can be created together with the address conversion table. For example, “0” is set in the SRAM area for creating the erased block search table, and the corresponding logical block address is not described in the redundant area of each block and the block status indicating that it is a bad block is not described. Sometimes, if the bit corresponding to the block is set to “1”, the address conversion table can be created together. In other words, if this process is performed when the data described in the redundant area of the blocks constituting the zone is read out, only “1” is set to the bit corresponding to the erased block, and this corresponds to the block that is not the erased block. The bit to be maintained remains “0” set in advance. After creation, when data is written to an erased block, the bit corresponding to that block is changed from “1” to “0”, and the block in which data is written is erased. Therefore, it is necessary to sequentially perform update processing for changing the bit corresponding to the block from “0” to “1”.

Next, retrieval of erased blocks using the erased block search table will be described with reference to FIG. In this erased block search, the bit corresponding to the block with the physical sequence number 1023 (from the leftmost bit in the top row) to the bit corresponding to the block with the physical sequence number 1023 (in the bottom row, (The rightmost bit) is scanned, and a bit of “1” corresponding to the erased block is searched. Here, the scanning is performed from the upper row to the lower row and from the left to the right in each row.

  In the erased block search table shown in FIG. 10B, when scanning is started from the leftmost bit in the top row, the fifth bit from the left in the fourth row from the top is Since it is “1”, the search is terminated here, and the data of the logical block address space allocated to the borrower's zone is written in the block of the physical serial number 28 corresponding to this bit.

  This erased block search table is used in the same way when searching for an erased block into which data in the logical block address space allocated to the renting zone is written. Scanning starts from the sixth bit from the left in the th row. Further, such a search is continued, and when scanning proceeds to the rightmost bit in the bottom row, scanning returns to the leftmost bit in the top row and scanning is continued.

Next, a process for writing the data of the logical block address space allocated to the borrower side zone into the erased block retrieved using the erased block search table on the lending side will be described. In this write process, after the write data is taken into the buffer 9 shown in FIG. 1, the following write process is set in the register of the flash memory sequencer block 12.
1) An internal write command is set in a predetermined register in the flash memory sequencer block 12 as an internal command.
2) An offset corresponding to the zone on the lending side is added to the physical serial number of the erased block retrieved using the erased block search table on the lending side, and the physical block address generated by adding this offset is added. The address of the page to which 5 bits (bits for identifying 32 pages) corresponding to the page number are added is set in a predetermined register in the flash memory sequencer block 12.

  Thereafter, the flash memory sequencer block 12 executes processing based on the setting of the write processing. When this processing is executed, command information and address information for executing an internal write command are supplied from the flash memory interface block 10 to the flash memory 2 via the internal bus 14. The write data held in the buffer 9 is also supplied to the flash memory 2 via the internal bus 14, and the data is written to a page set in a predetermined register in the flash memory sequencer block 12.

  In addition, after completion of the writing process, a flag indicating that the data is lent out is set in the redundant area of the block in which the data has been written, and the data written in the block is described in the portion describing the corresponding logical block address. A logical serial number (a logical serial number in the logical block address space allocated to the borrower's zone) is written. In the writing process to the redundant area, after setting data such as the flag and the logical serial number in a buffer for setting data to be written to the redundant area, a command and an address are assigned to a predetermined register in the flash memory sequencer block 12. By setting, it can be executed in the same manner as the above-described writing process.

Next, processing for reading data written in the borrowed block will be described. When reading data written in a borrowed block, the data is read from the block in the lending side, not the block in the borrowing zone assigned to the logical block address of the data to be read. Therefore, the logical block address of the data to be read is converted into a physical block address in the rent side zone. In other words, in the process of reading the data written in the borrowed block, the lending-side offset is added to the physical sequence number given by the borrowing-side address conversion table shown in FIG. The physical serial number is converted into a physical block address corresponding to a block in the lending side zone. The offset on the lending side is added only to the physical serial number where “1” is set in the borrowing flag in the address conversion table on the borrowing side shown in FIG. 8, and “0” is set in the borrowing flag. The borrower's offset is added to the set physical serial number.

When the read process is performed based on the physical block address obtained as described above, the following read process is set in the register of the flash memory sequencer block 12 shown in FIG.
1) An internal read command is set in a predetermined register in the flash memory sequencer block 12 as an internal command.
2) An offset corresponding to the lending side zone is added to the physical sequence number given by the address conversion table, and 5 bits (32 pages corresponding to the page number) are identified in the physical block address generated by adding this offset. The address of the page to which the bit is added is set in a predetermined register in the flash memory sequencer block.

  Thereafter, the flash memory sequencer block 12 executes the process based on the setting of the read process. When this processing is executed, command information and address information for executing an internal write command to the flash memory 2 are supplied from the flash memory interface block 10 to the flash memory via the internal bus 14. Thereafter, the data output from the page of the address set in the predetermined register in the flash memory sequencer block 12 from the flash memory 2 is fetched into the buffer 9 and further transferred to the host system 4 side.

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell constituting the flash memory. FIG. 3 is a cross-sectional view schematically showing a memory cell in a written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory. FIG. 5 is a diagram showing an example in which a zone is composed of 1024 blocks. FIG. 6 is a diagram showing the correspondence between each zone and the logical block address space. FIG. 7 is a diagram illustrating an example of a loan management table. FIG. 8 is a diagram showing an example of the address conversion table on the borrower side. FIG. 9 is a diagram showing the correspondence between the address conversion table on the borrowing side and the block on the lending side. FIG. 10 is a conceptual diagram illustrating an example of an erased block search table.

Explanation of symbols

1 Flash memory system 2, 35, 36 Flash memory 3 Controller 4 Host computer 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region

Claims (8)

An allocation management function for managing the correspondence between a zone composed of a plurality of blocks in the flash memory and a logical block address space on the host system side allocated to the zone;
An access control function for controlling access to the zone;
A loan management function for managing the correspondence between the zone on the lending side and the zone on the borrowing side when lending blocks between the zones; and
When the data of the logical block address assigned to the borrowing zone is written in the block lent out from the lent zone, the block is lent out in the redundant area of the lent block. A memory controller comprising an information setting function for setting information to be indicated. The memory controller according to claim 1, wherein the loan management function stores information on a correspondence relationship between the lending side zone and the borrowing side zone in a specific block in the flash memory. 3. The memory controller according to claim 1, wherein a logical value set in a specific bit of the redundant area corresponds to information indicating that the lending is performed. 4. The memory controller according to claim 1, wherein the lending management function determines a correspondence relationship between the lending side zone and the borrowing side zone based on information on the number of defective blocks for each zone. 5. The memory controller according to claim 1, wherein information relating to a defective block in the flash memory is stored in a specific block in the flash memory by the loan management function. 6. The memory controller according to claim 1, wherein information relating to the number of defective blocks for each zone is stored in a specific block in a flash memory by the loan management function. A flash memory system comprising the memory controller according to any one of claims 1 to 6 and a flash memory. A flash memory control method for controlling access from the host system side to the flash memory according to a correspondence relationship between a logical block address space on the host system side and a zone configured by a plurality of blocks in the flash memory,
A process of writing data of a logical block address corresponding to the first zone to a block in the second zone assigned to the first zone in which a block to be written to cannot be secured; and in the second zone In the writing process to the block, data of the logical block address corresponding to the first zone is written in the redundant area of the block in which the data of the logical block address corresponding to the first zone is written. And a method for controlling the flash memory.