JP2008226188A - Memory controller, flash memory system with memory controller, and method for controlling flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of a failure when the number of acquired defective blocks increases in a flash memory. <P>SOLUTION: A physical address space of the flash memory is divided into a plurality of unit physical areas (physical zone or a plurality of physical segments). Each unit physical area is an aggregate of a plurality of physical blocks. A correspondence relation between a logical block and a physical block is controlled as in the preparation of an address conversion table in each unit physical area. When the number of defective blocks increases in any unit physical area to make it difficult to secure erased blocks necessary for data rewriting in the unit physical area, the unit physical area is connected to another unit physical area to be expanded to a larger unit physical area so that erased blocks can be secured. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to flash memory control, and more particularly to memory control that takes into account the occurrence of acquired bad blocks in flash memory.

  In a flash memory, in particular, a NAND flash memory, data erasure can be performed in units of physical blocks that are sets of a plurality of physical pages. Therefore, when the host system requests to write new data to a certain logical address (that is, to rewrite the old data at the logical address to new data), the new data is written to the physical block storing the old data. It cannot be overwritten. In this case, the process of erasing the old block data from the physical block storing the old data after writing the new block data including the new data to another erased physical block (that is, a free block) is performed. Is called. As described above, when data is rewritten, the new data is moved to a physical block different from the old data.

  Therefore, the correspondence between the logical block specified by the logical address code provided from the host system and the physical block in the flash memory changes every time data is rewritten. A memory controller interposed between the host system and the flash memory controls and manages this correspondence. That is, each physical block has a redundant area mainly used for control purposes in addition to an area for storing user data. The memory controller records information for specifying the logical block corresponding to the physical block in the redundant area of each physical block. The memory controller then reads the above information from the redundant areas of a large number of physical blocks in the memory at each point in time, and creates an address conversion table describing the correspondence between the logical blocks and the physical blocks based on the information. To do.

  The total number of physical blocks in flash memory is very large. As the capacity of the flash memory increases, the number of physical blocks also increases. If the memory controller tries to create an address translation table that describes the above correspondence relationship for all physical blocks in the flash memory, it takes time to create the address translation table, which impedes access speed. Let's go. In order to solve this problem, the physical address space of the flash memory is divided into a plurality of physical zones, each of which is a set of an appropriate number of physical blocks, and a logic such as the creation of the address conversion table described above is created for each physical zone. A technique is known that reduces the processing load of control by controlling the correspondence between blocks and physical blocks.

  According to this zoning technique, a logical address space in which logical addresses are defined is also divided into a plurality of logical zones, each of which is a set of an appropriate number of logical blocks. A plurality of logical zones and a plurality of physical zones are basically associated in a one-to-one relationship. The number of physical blocks included in one physical zone is slightly larger than the number of logical blocks included in one corresponding logical zone. One of the reasons is that, as described above, in order to rewrite data of one logical block, an empty physical block for writing new data is used in addition to a physical block storing old data. This is because a larger number of physical blocks is required than the number of logical blocks. Another reason is that all physical blocks include some bad blocks, so each physical zone must have enough physical blocks to allow a certain number of bad blocks. That's why.

  However, when many defective blocks (physical blocks that cannot be written or erased normally) are concentrated at a specific location in the memory cell array of the flash memory, the defective blocks are concentrated in a specific physical zone to which the specific location is assigned. There is a possibility that a defect (typically, an empty block cannot be secured) may occur in the zone. In order to solve this problem, during the initial setting, a plurality of physical blocks included in one physical zone are physically distributed in the flash memory, and the number of congenital bad blocks included in the physical zone is equalized. A technique for achieving this has been proposed (for example, Patent Document 1). In addition, a technique for detecting the position of a defective block and adjusting the boundary of the physical zone so that good physical blocks are evenly distributed in a plurality of physical zones has been proposed (for example, Patent Document 2).

JP 2005-209140 A JP 2006-509304 A

  According to the block distribution technique described in Patent Document 1 and the zone boundary technique described in Patent Document 2, the concentration of defective blocks in a specific physical zone can be reduced. However, in the flash memory, the number of acquired defective blocks gradually increases due to an increase in the number of accesses and deterioration over time. Therefore, after the start of the use of the flash memory, there is always a time when the number of defective blocks reaches an allowable limit and a free block cannot be secured in any physical zone.

  Accordingly, an object of the present invention is to prevent the occurrence of problems when the number of acquired defective blocks increases in a flash memory.

According to a first aspect of the present invention, there is provided a memory controller that controls access to a flash memory that is erased in physical block units based on logical addresses in logical sector units given from a host system,
Unit area management means for managing the correspondence between a plurality of unit logical areas, each of which is a set of a plurality of logical sectors, and a plurality of unit physical areas, each of which is a set of a plurality of physical blocks;
Address management means for managing the correspondence between the logical address included in each unit logical area and the physical address included in each unit physical area corresponding to each unit logical area;
A physical region combining means that combines two or more unit physical regions into an expanded unit physical region;
The unit area management means includes two or more unit logical areas corresponding to the two or more unit physical areas before combining, with respect to all the expanded unit physical areas after combining. To correspond,
A memory controller is provided.

  In a preferred embodiment, at least one of the two or more unit physical areas coupled by the physical area coupling unit includes a predetermined number or more of defective blocks. The memory controller is configured as described above.

  In a preferred embodiment, the number of the plurality of unit physical areas and the number of the two or more unit physical areas combined by the physical area combining unit are both given as a power of two. The memory controller is configured.

  In a preferred embodiment, a logical block area distribution unit is further provided which includes a plurality of logical block areas continuous in a logical address space in a distributed manner with respect to the plurality of unit logical areas. Each logical block area includes a plurality of the logical sectors in which the logical addresses are continuous. The number of the logical sectors belonging to the logical block area and the number of the plurality of unit logical areas are both given by a power of two.

In a preferred embodiment, when the number of the logical sectors belonging to the logical block area is 2 ⁱ and the number of the plurality of unit logical areas is 2 ^j , the logical sector of the logical sector is The unit logical area including the logical block area to which the logical sector belongs, and the unit corresponding to the unit logical area, based on the bit values from the (i + 1) th bit to the (i + j) th bit counted from the lower side of the address The memory controller is configured to identify the physical area.

  According to another aspect of the present invention, a flash memory system including the memory controller and the flash memory is provided.

According to still another aspect of the present invention, there is provided a method for controlling access to a flash memory that is erased in units of physical blocks, based on logical addresses in units of logical sectors given from a host system.
Managing a correspondence relationship between a plurality of unit logical areas, each of which is a set of a plurality of logical sectors, and a plurality of unit physical areas, each of which is a set of a plurality of physical blocks;
Managing the correspondence between the logical address included in each unit logical area and the physical address included in each unit physical area corresponding to each unit logical area;
Combining two or more unit physical areas into an expanded unit physical area;
A step of associating the expanded unit physical area after the combination with two or more unit logical areas corresponding to the two or more unit physical areas before the combination. A method is provided.

  In a preferred embodiment, the control method further includes a step of determining whether there is a free block in each unit physical area, and when it is determined that there is no free block in each unit physical area, Two or more unit physical areas are combined.

  According to the present invention, it is possible to prevent the occurrence of problems when the number of acquired defective blocks increases in the flash memory.

  Several preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an overall configuration of a flash memory system 1 according to an embodiment of the present invention.

  As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3. The memory controller 3 is connected to the flash memory 2 via the internal bus 14 and is connected to the host system 4 via the external bus 13. The host system 4 can be various devices that request access to the flash memory 2, such as personal computers, digital still cameras, and other information processing devices. The memory controller 3 controls access to the flash memory 2 in response to access (that is, write and read) requests from the host system 4. The flash memory 2 includes a large-capacity nonvolatile memory cell array for storing data, and a small-capacity register (e.g., equivalent to one physical page) for mediating data transfer between the memory cell array and the internal bus 14 And have.

  The memory controller 3 gives an internal command, a physical address, data, and the like to the flash memory 2 based on an external command, a logical address, and the like given from the host system 4. The flash memory 2 executes processes such as a read process, a write process, and an erase process based on an internal command and a physical address given from the memory controller 3. Here, a command that the host system 4 gives to the flash memory system 1 is called an external command, and a command that the memory controller 3 gives to the flash memory 2 is called an internal command.

  FIG. 2 shows the configuration of the physical address space of the memory cell array of the flash memory 2.

  As shown in FIG. 2, the physical address space of the flash memory 2 is divided into a large number of physical blocks. Each physical block is a set of a predetermined plurality of physical pages. In the present embodiment, the total number of physical blocks is, for example, 8192, and one physical block is, for example, a set of 64 physical pages. Here, the physical page is a unit of a memory area that is a target of data reading and writing in the flash memory 2 (a memory group selected at one time during data reading and writing). A physical block is a unit of a memory area (a group of memory cells from which data is erased at once) that is a target of data erasure in the flash memory 2.

  Each physical page has a user area 25 and a redundant area 26. The user area 25 is a storage area for storing user data given from the host system 4. The redundant area 26 is a storage area for storing additional data for control purposes mainly used by the memory controller 3. In this embodiment, the user area 25 of each physical page has a capacity corresponding to, for example, 4 sectors, that is, a capacity of 2048 bytes, and the redundant area 26 has a capacity of 64 bytes.

  Further, in the present embodiment, the physical address space of the flash memory 2 is divided into a predetermined plurality of physical zones, and the physical zone is composed of a predetermined plurality of physical blocks. In the present embodiment, the total number of physical zones is, for example, 8, and each physical zone is a set of, for example, 1024 physical blocks.

  Furthermore, each physical zone is divided into a predetermined plurality of physical segments by the memory controller 3, and each physical segment is composed of a predetermined plurality of physical blocks. Note that the memory controller 3 performs management processing of physical zones and physical segments and control processing of the correspondence relationship between logical blocks and physical blocks (for example, creation of an address conversion table). In the present embodiment, the control processing of the correspondence relationship between the logical block and the physical block (such as creation of an address translation table) is performed in units of physical segments (that is, an address translation table is created for each physical segment).

  The memory controller 3 divides one physical zone into a predetermined maximum number of physical segments (that is, minimizes the number of physical blocks included in the physical segment) when the use of the flash memory 2 is started (initial stage). However, as the number of acquired bad blocks in the physical zone increases, in accordance with the principles of the present invention, the number of physical segments in the physical zone is reduced and the size of each physical segment is increased (i.e. , Increase the number of physical blocks in the physical segment). That is, the memory controller 3 continuously monitors the number of defective blocks (congenital defective blocks and acquired defective blocks) included in each physical segment from the initial stage, and determines the number of defective blocks included in a specific physical segment. When the number increases to a certain level, the physical segment is combined with other physical segments to increase the size of the physical segment. After that, when the number of bad blocks included in the physical segment whose size has been increased to a certain level, the physical segment whose size has been increased is combined with other physical segments to further increase the size of the physical segment. To do. Here, the level (number of defective blocks) when the physical segments are combined can be appropriately set according to the number (total number) of physical blocks included in the physical segment.

  Instead of combining multiple physical segments based on the number of bad blocks included in a physical segment, when it becomes impossible to secure an empty block in a specific physical segment, the physical segment is transferred to another physical segment. The size of the physical segment may be increased by combining with the segment. Also in this case, when it becomes impossible to secure an empty block in the physical segment whose size has been increased, the physical segments are combined to further increase the size of the physical segment.

  In the present embodiment, in the initial stage, the number of physical segments in one physical zone is, for example, eight, and one physical segment is a set of, for example, 128 physical blocks. As the number of bad blocks increases, the number of physical segments in one physical zone decreases gradually, and at the same time, the size of one physical segment (expanded physical segment) increases gradually. To go.

  Here, the size of the physical segment is increased only for a physical segment that has reached the combined level (a physical segment in which the number of bad blocks has reached a certain level or a physical segment for which a free block cannot be secured). However, it is preferably performed for the entire physical zone including the physical segment that has reached the coupling level. That is, when there are 8 physical segments in one physical zone and at least one of the physical segments has reached the coupling level (when the number of bad blocks reaches a certain level or When it becomes impossible to secure a free block), the physical segment that has not reached the combined level is also increased in size, and the number of physical segments existing in the physical zone is reduced from eight to four, for example. . After this, when at least one physical segment in the physical segment whose size has been expanded (four physical segments) reaches the coupling level, the number of physical segments existing in the physical zone is further increased to four. For example, the number is reduced to two.

  When the physical segment size is expanded independently for each physical zone as described above, the number of physical segments existing in the physical zone must be managed for each physical zone. In order to reduce the number of physical segments existing in the physical zone, the number of physical segments existing in the physical zone may be reduced in accordance with the physical zone in which the number of physical segments existing in the physical zone is minimized. Good. For example, when 8 physical segments exist in each physical zone, it is necessary to increase the size of one physical zone to reduce the number of physical segments from 8 to 4. Sometimes, for all other physical zones, the size may be increased to reduce the number of physical segments from eight to four.

  As described above, as the number of defective blocks increases, the physical segment is expanded (that is, the number of physical blocks included in the physical segment increases), thereby causing a problem caused by the increase in the number of defective blocks. Occurrence is prevented. This control will be described in detail later. In order to facilitate this control, the number of physical segments existing in each physical zone is preferably a numerical value given as a power of 2 at any stage, and the number of physical segments combined at the stage transition Is preferably a numerical value given as a power of 2. Also, the number of physical blocks in each physical segment, the number of physical sectors in each physical block, and the number of logical sectors in each logical block corresponding to each physical block are numerical values given by powers of 2, respectively. Is desirable.

  In the redundant area 26 of each physical page, additional data such as an error correction code, logical address information, and a block status (flag) is stored. The error collection code is used for detecting and correcting an error included in user data stored in the user area 25. The block status (flag) is a flag indicating pass / fail of the physical block. A block status (flag) indicating a defective block is written to a defective physical block to which data cannot be normally written.

  The logical address information is information for determining the correspondence relationship between the physical block and the logical block. A physical block in which this logical address information is not stored in the redundant area 26 is determined to be a free block.

  As described above, one physical block includes a plurality of physical pages. Data cannot be overwritten on these physical pages. For this reason, even when only the data stored in one physical page is rewritten, the data stored in all the physical pages in the physical block including the physical page must be rewritten. In this case, data stored in all physical pages of the physical block including the physical page to be rewritten is written to another erased physical block (empty block). Therefore, the correspondence between the logical block and the physical block dynamically changes every time data is rewritten in the flash memory 2.

  The memory controller 3 creates an address conversion table describing the correspondence between logical blocks and physical blocks, and refers to the address conversion table to specify a logical address specified by the host system 4 to the flash memory 2. To physical address. This address conversion table can be created for each physical segment. The address translation table is created based on the logical address information stored in the redundant area 26 of the first physical page of the physical block. Therefore, when creating an address translation table for a certain physical segment, the physical segment The logical address information must be sequentially read from the redundant area 26 of the physical block included in the. Therefore, as the size of the physical segment (the number of physical blocks included therein) is smaller, the processing time for creating the address translation table is reduced and faster memory access is possible.

  As shown in FIG. 1, the memory controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error correction code) block 11, and a ROM 12. And have.

  The microprocessor 6 executes various processes based on the firmware stored in the ROM 12. The firmware in the ROM 12 includes a program for controlling each part of the memory controller 3 such as the host interface block 7 and the flash memory interface block 10. For example, based on this program, the processes such as management of the physical segment and creation of the address conversion table described above are executed.

  The host interface block 7 transmits / receives data, logical addresses, status information, external commands, and the like to / from the host system 4 through the external bus 13 under the control of the microprocessor 6. The flash memory interface block 10 transmits and receives data, physical addresses, status information, internal commands, and the like to and from the flash memory 2 via the internal bus 14 under the control of the microprocessor 6.

  The work area 8 is a work area used by the microprocessor 6. In the work area 8, for example, the above-described address conversion table describing the correspondence between logical blocks and physical blocks, and a free block search table for searching for free blocks are created.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 by the flash memory interface block 10 is temporarily held in the buffer 9 and then transferred to the host system 4 through the host interface block 7. Data to be written to the flash memory 2 input from the host system 4 to the host interface block 7 is temporarily held in the buffer 9 and then transferred to the flash memory 2 through the flash memory interface block 10.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  In the flash memory system 1 according to the present embodiment having the above-described configuration, the operation according to the principle of the present invention performed by the memory controller 3 will be described in detail below.

  FIG. 3 shows a configuration of logical zones and logical blocks in a logical address space shared by the memory controller 3 and the host system 4.

  The logical address space is divided into a number of logical sectors (typically 512 bytes). LBA (Logical Block Address) shown in (a) of FIG. 3 is a serial number assigned to all logical sectors. Basically, the LBA, which is an address in units of logical sectors, is used as a logical address provided from the host system 4 to the memory controller 3.

  As shown in FIGS. 3A and 3B, the memory controller 3 manages a set of, for example, 256 logical sectors having continuous LBAs as one logical block. The memory controller 3 divides the logical address space into, for example, 8000 logical blocks (slightly less than the total of 8192 physical blocks in the flash memory 2), and LBN (logical block number) is assigned to these logical blocks. A serial number called is assigned.

  As shown in FIGS. 3B and 3C, the memory controller 3 has, for example, 1000 logical blocks (slightly less than 1024 physical blocks included in one physical zone in the flash memory 2). Are managed as one logical zone. In other words, a logical address space including 8000 logical blocks is divided into 8 logical zones (the same number as the physical zones in the flash memory 2) and managed. For the eight logical zones, areas in the logical address space are allocated in a predetermined distribution unit. For example, an area in the logical address space is allocated to each logical zone in units of one block (one logical block) (that is, each area in the logical address space is in 256 sectors (256 logical sectors)). To the logical zone). By performing such distribution, logical blocks having consecutive LBNs are distributed and allocated to different logical zones. A serial number called LZN (logical zone number) is assigned to the eight logical zones. Further, for each logical zone, a serial number called LZIBN (block number in logical zone) is assigned to 1000 logical blocks included therein.

  The distribution unit can be appropriately set, but is preferably a set including the number of logical sectors given by a power of 2. In addition, the number of logical sectors included in one logical block is usually set so that the area included in one logical block is equal to the storage area of user data included in one physical block. . However, when a plurality of physical blocks are allocated to one logical block, the number of logical sectors included in one logical block depends on the number of physical blocks allocated to one logical block. Is set. For example, when two physical blocks are allocated to one logical block, the area included in one logical block is equal to the storage area of user data included in two physical blocks. The number of logical sectors included in one logical block is set.

  Even if access concentrates on a specific area where LBAs in the logical address space continue by performing the distribution of the logical address space as described above, if the specific area is wider than the above distribution unit, The access is distributed across multiple logical zones (ie multiple physical zones). As shown in FIGS. 3B and 3C, when the area in the logical address space is allocated to each logical zone in units of 256 sectors (256 logical sectors), the area where access is concentrated is 257 sectors. In the above area, the access is distributed to at least two logical zones. Thereby, it is suppressed that access concentrates only on a specific physical zone, and as a result, it is suppressed that an acquired defective block concentrates only on a specific physical zone.

FIG. 4 shows the LBA (Logical
The bit structure of (Block Address) is shown.

In FIG. 4, each “*” mark represents each bit. The LBA is a binary value of 21 bits, for example, and identifies all the logical sectors (256 × 8000 logical sectors) in the logical address space. The upper predetermined number of bits (for example, upper 13 bits) of the LBA is LBN, and the lower remaining number of bits (for example, lower 8 bits) is LSN (logical sector number). Here, LSN is a serial number assigned to all logical sectors included in each logical block. The number of logical sectors included in each logical block is preferably a numerical value given by a power of 2, that is, 2 ⁱ (i is an integer, for example, i = 8 and 256). Accordingly, LSN is obtained by extracting the lower i bits of the LBA, and LBN is obtained by extracting the upper several remaining bits.

The number of logical zones is also preferably a numerical value given as a power of 2, that is, 2 ^j (j is an integer, for example, j = 3 and 8). Thereby, as shown in FIG. 4, the lower j bits (for example, the lower 3 bits) of the LBN are LZN, and the upper several remaining bits (for example, the upper 10 bits) are LZIBN. Thus, setting the lower j bits of the LBN to LZN corresponds to setting the i + 1-th bit to the i + j-th bit as LZN, counting from the lower level of the LBA. In other words, if the distribution unit is a set including a logical sector of a numerical value given by a power of 2, and the number of logical zones is a numerical value given by a power of 2, based on a specific bit of the LBA, It is possible to determine a logical zone to which a logical sector (or a logical block to which the logical sector belongs) is allocated. The method for discriminating the logical zones to be distributed in this way is adopted in this embodiment because the logical address space is distributed and allocated to a plurality of logical zones as shown in FIGS. 3B and 3C. This is one technique. By using this method, it is not necessary to perform division calculation for LBN in the memory controller 3 when determining the logical zone to be accessed. Further, the total number of logical sectors included in one logical zone is not limited to a numerical value given as a power of 2, and the total number of logical sectors included in one logical zone can be easily changed. There is an advantage.

  FIG. 5 shows the correspondence between logical zones, physical zones, and physical blocks controlled in the memory controller 3. By looking at both FIG. 3 and FIG. 5, an overall picture of the relationship between the logical address space and the physical address space should be understood.

  For example, eight logical zones as shown in FIG. 5A are associated with the same number (ie, eight) physical zones as shown in FIG. 5B in a one-to-one relationship. . As shown in FIG. 5B, serial numbers called PZN (physical zone numbers) are assigned to these physical zones. Each physical zone includes, for example, 1024 physical blocks (slightly more than the number 1000 of logical blocks in each logical zone). All physical blocks have serial numbers called PBA (physical block numbers). Further, for each physical zone, a serial number called PZIBN (physical zone block number) is assigned to 1024 physical blocks included therein.

  FIG. 6 shows the bit structure of PBN (physical block number).

As shown in FIG. 6, the PBA is a 13-bit binary value, for example, and identifies all physical blocks (for example, 8192 physical blocks). Numbers number of physical zone is given a power of 2, i.e., 2 ^p number (p is an integer, for example, in p = 3, 8 pieces) if the upper p bits of the PBA (e.g. upper 3 bits) Is PZN, and the lower few remaining bits (for example, the lower 10 bits) are PZIBN.

  By the way, in the example shown in FIG. 5B, each physical zone is configured by a set of physical blocks having continuous PBAs. However, similarly to the relationship between logical blocks and logical zones shown in FIG. 3, each physical zone is constituted by a set of physical blocks having non-contiguous PBAs (in other words, physical blocks having continuous PBAs are represented by One advantage of this is that congenital bad blocks can be prevented from concentrating on a specific physical zone.

  FIG. 7 shows the configuration of the physical block.

  As shown in FIG. 7, one physical block is composed of a predetermined number (for example, 64) physical pages. Each physical page is composed of a plurality of (for example, four) physical sectors. For each physical block, a serial number called PPN (physical page number) is assigned to all (for example, 64) physical pages included therein. Further, for each physical block, a serial number called PSN (physical sector number) is given to all (for example, 256) physical sectors included therein.

  Although not shown, the logical block has the same configuration as the above physical block. That is, one logical block is composed of a predetermined plurality (for example, 64) logical pages. Each logical page is composed of a predetermined plurality of (for example, four) logical sectors. For each logical block, a serial number called LPN (logical page number) is assigned to all (for example, 64) logical pages included therein. Further, for each logical block, a serial number called LSN (logical sector number) is assigned to all (for example, 256) logical sectors included therein.

  FIG. 8 shows the bit structure of LSN and PSN.

  As shown in FIG. 8, both LSN and PSN are, for example, 8-bit binary values, and identify all 256 sectors described above. Predetermined bits (for example, upper 6 bits) of LSN and PSN are LPN and PPN, respectively, and identify all of the 64 pages described above.

  By the way, between the corresponding logical block and physical block, for example, management is performed so that a logical page and a physical page in which LPN and PPN have the same value correspond to each other. However, as a modification, the corresponding logical page and physical page LPN and PPN may have different values between the corresponding logical block and physical block. For example, by adopting a method in which the LPN of each logical page corresponding to each physical page is recorded in the redundant area 26 of each physical page, the correspondence between the logical page and the physical page can be changed. Can be managed.

  Now, as already described, the memory controller 3 divides each physical zone into a plurality of physical segments. When writing data to the flash memory 2, the memory controller creates an address conversion table for the physical segment to be accessed (physical segment corresponding to the logical segment to be accessed). In accordance with the principle of the present invention, the memory controller 3 expands a physical segment by combining the physical segment with another physical segment as the number of acquired defective blocks increases in a physical segment. The physical segment control performed by the memory controller 3 will be specifically described below with reference to FIGS. 9 to 17 in association with the address conversion table creation process.

  FIG. 9 shows a configuration of a logical segment defined on the logical address space.

  FIG. 9A shows a logical zone of LZN # 0. As shown in FIG. 9B, this logical zone is divided into, for example, eight logical segments (a predetermined maximum number of logical segments). The number of logical segments in the logical zone is preferably a numerical value given as a power of two. As shown in FIG. 9B, serial numbers called LSGN (logical segment numbers) are assigned to all logical segments in the logical zone. Each logical segment is composed of a set of logical blocks having non-contiguous LZIBN. In other words, logical blocks with consecutive LZIBNs are distributed in different logical segments.

  In the present embodiment, there are eight logical segments in the logical zone. At this time, the logical segment numbers assigned to the eight logical segments are indicated by “LSGN # 0 to # 7” in FIG. 9B. Each logical segment indicated by “LSGN # 0 to # 7” includes 125 logical blocks. In the initial stage (first stage), the eight logical segments are associated with the eight physical segments in a one-to-one relationship.

  In the second stage, the eight logical segments become four groups of two, and the four groups are associated with the four physical segments. That is, the logical segments of LSGN # 0 and LSGN # 1 are the first group, the logical segments of LSGN # 2 and LSGN # 3 are the second group, and the logical segments of LSGN # 4 and LSGN # 5 are the third group. , LSGN # 6 and LSGN # 7 are logical segments. Two logical segments belonging to the same group are associated with the same physical segment. In FIG. 9B, the logical segment group numbers of LSGN # 0 and LSGN # 1 correspond to GN # 0, and the logical segment group numbers of LSGN # 2 and LSGN # 3 correspond to GN # 1. The group numbers of the logical segments of LSGN # 4 and LSGN # 5 correspond to GN # 2, and the group numbers of the logical segments of LSGN # 6 and LSGN # 7 correspond to GN # 3.

  In the third stage, the eight logical segments become two groups of four, and the two groups are associated with the two physical segments. That is, the logical segments of LSGN # 0 to # 3 are the first group, and the logical segments of LSGN # 4 to # 7 are the second group. Four logical segments belonging to the same group are associated with the same physical segment. In FIG. 9B, the logical segment group numbers of LSGN # 0 to # 3 correspond to GN '# 0, and the logical segment group numbers of LSGN # 4 to # 7 correspond to GN' # 1. To do.

Number of logical zones ^{2 j} number (j is an integer, for example, in j = 3, 8 pieces), the number of logical segments ^{2 s} number (s is an integer, for example, in s = 3, 8 The logical segment number (LSGN) corresponds to the value indicated by the bits from the (j + 1) th bit to the (j + s) th bit counted from the lower side of the LBN. For example, by the number of logical zones 2 ³ (8), when the number of logical segments is 2 ³ (8), as shown in FIG. 10A, the fourth bit counted from the lower side of the LBN The value indicated by the bits up to the sixth bit corresponds to the logical segment number (LSGN). Note that GN (group number) shown in FIG. 9B corresponds to the values indicated by the 5th to 6th bits counted from the lower side of the LBN, and GN ′ (group number) is the lower order. This corresponds to the value indicated by the sixth bit counted from the side.

<Description of the first stage>
FIG. 11 shows the correspondence between the logical segments in the logical zone of LZN # 0 and the physical segments in the physical zone of PZN # 0 in the first stage. As shown in FIG. 11B, there are eight physical segments (predetermined maximum number of physical segments) in the physical zone of PZN # 0 as in the logical zone side. A serial number called PSGN (physical segment number) is assigned to all physical segments in the physical zone. Each physical segment of PSGN # 0 to # 7 includes 128 physical blocks. The logical segment and the physical segment are associated with each other in a one-to-one relationship, and are managed so that the logical segment and the physical segment in which LSGN and PSGN have the same value correspond to each other. Here, as shown in FIG. 12A, LSGN corresponds to the value indicated by the fourth to sixth bits counted from the lower side of LBN. As shown in FIG. 12B, PSGN corresponds to the value indicated by the 4th to 6th bits counted from the upper side of PBA (the number of physical zones is 2 ^p (p is an integer, For example, when p = 3 and 8), and the number of physical segments is 2 ^s (s is an integer, for example, s = 3 and 8), the physical segment number is the upper side of the PBA. (Corresponding to the values indicated by the bits from the (p + 1) th bit to the (p + s) th bit).

<Explanation of the second stage>
Thereafter, when at least one physical segment among the eight physical segments reaches a predetermined coupling level, the process proceeds to the second stage. Examples of the predetermined coupling level include when the number of defective blocks in the physical segment reaches a predetermined number, or when it becomes impossible to secure an empty block in the physical segment.

  FIG. 13 shows the correspondence between the logical segments in the logical zone of LZN # 0 and the physical segments in the physical zone of PZN # 0 in the second stage. As shown in FIG. 13B, the number of physical segments in the physical zone of PZN # 0 is reduced from eight to four, and the number of physical blocks included in each physical segment is from 128 to 256. Increase to pieces. That is, when transitioning from the first stage to the second stage, PSGN # 0 and PSGN # 1 physical segments, PSGN # 2 and PSGN # 3 physical segments, PSGN # 4 and PSGN # 5 physical segments, and PSGN # 6 and PSGN # 7 physical segments are combined. At this time, only a physical segment in which the number of defective blocks reaches a predetermined number or a physical segment for which an empty block cannot be secured may be combined (for example, only a physical segment of PSGN # 3 When the number of bad blocks in the segment reaches a predetermined number or when it becomes impossible to secure an empty block in the physical segment, only the physical segments of PSGN # 2 and PSGN # 3 are combined. However, in order to avoid complicated management, physical segments that do not need to be combined (physical segments other than PSGN # 2 and PSGN # 3) are similarly combined.

  The physical segment of PSGN '# 0 obtained by combining the physical segments of PSGN # 0 and PSGN # 1 is associated with the logical segments of LSGN # 0 and LSGN # 1. Therefore, the 125 logical blocks included in the logical segment of LSGN # 0 can be associated with any of the 256 physical blocks included in the physical segment of PSGN '# 0. The 125 logical blocks included in the segment can be associated with any of the 256 physical blocks included in the physical segment of PSGN '# 0. Similarly, the physical segments of PSGN '# 1 obtained by combining the physical segments of PSGN # 2 and PSGN # 3 are associated with the logical segments of LSGN # 2 and LSGN # 3. The PSGN '# 2 physical segment obtained by combining the PSGN # 4 and PSGN # 5 physical segments is associated with the logical segments LSGN # 4 and LSGN # 5. The physical segment of PSGN '# 3 obtained by combining the physical segments of PSGN # 6 and PSGN # 7 is associated with the logical segments of LSGN # 6 and LSGN # 7.

  That is, in the second stage, two logical segments corresponding to GN (group number) # 0 (logical segments of LSGN # 0 and LSGN # 1) are associated with the physical segment of PSGN '# 0, and GN (group Number) 2 logical segments corresponding to # 1 (LSGN # 2 and LSGN # 3 logical segments) are associated with PSGN '# 1 physical segment, and 2 logical segments corresponding to GN (group number) # 2 Logical segments (LSGN # 4 and LSGN # 5 logical segments) are associated with PSGN '# 2 physical segments, and two logical segments (LSGN # 6 and LSGN # 7) corresponding to GN (group number) # 3 Are associated with the physical segment of PSGN '# 3. Here, GN (group number) corresponds to the value indicated by the 5th to 6th bits counted from the lower side of the LBN, as shown in FIG. 14A. As shown in FIG. 14B, PSGN 'corresponds to the values indicated by the 4th to 5th bits counted from the upper side of the PBA.

<Explanation of the third stage>
After the transition to the second stage, the transition to the third stage is made when at least one physical segment of the four physical segments reaches a predetermined coupling level. Examples of the predetermined coupling level include when the number of defective blocks in the physical segment reaches a predetermined number, or when it becomes impossible to secure an empty block in the physical segment.

  FIG. 15 shows the correspondence between the logical segments in the logical zone of LZN # 0 and the physical segments in the physical zone of PZN # 0 in the third stage. As shown in FIG. 15B, the number of physical segments in the physical zone of PZN # 0 is reduced from four to two, and the number of physical blocks included in each physical segment is from 256 to 512. Increase to pieces. That is, when moving from the second stage to the third stage, the physical segments PSGN '# 0 and PSGN' # 1 and the physical segments PSGN '# 2 and PSGN' # 3 are combined. At this time, as described above, only the physical segment in which the number of defective blocks has reached a predetermined number or the physical segment in which a free block can no longer be secured may be combined, but avoiding complicated management. Therefore, physical segments that do not need to be combined are similarly combined.

  PSGN "# 0 physical segment (PSGN # 0- # 3 physical segment combined), which combines PSGN '# 0 and PSGN' # 1 physical segments, includes LSGN # 0- # 3 Therefore, the 125 logical blocks included in the logical segment of LSGN # 0 can be associated with any of the 512 physical blocks included in the physical segment of PSGN "# 0. Thus, the 125 logical blocks included in the logical segments LSGN # 1 to # 3 can be associated with any of the 512 physical blocks included in the physical segment PSGN "# 0. Similarly, the physical segment of PSGN "# 1 that combines the physical segments of PSGN '# 2 and PSGN' # 3. The instrument (psgn # physical segment bound with physical segment of 4 to # 7), the logical segments of LSGN # 4 to # 7 are associated.

  That is, in the third stage, four logical segments corresponding to GN ′ (group number) # 0 (LSGN # 0 to # 3 logical segments) are associated with PSGN ″ # 0 physical segments and GN ′ ( Four logical segments (LSGN # 4 to # 7 logical segments) corresponding to (group number) # 1 are associated with PSGN "# 1 physical segments. Here, GN ′ (group number) corresponds to the value indicated by the sixth bit as counted from the lower side of the LBN, as shown in FIG. 16A. As shown in FIG. 14B, PSGN 'corresponds to the value indicated by the fourth bit counted from the upper side of the PBA.

<Description of the predetermined coupling level>
The number of physical blocks included in each physical segment is set to be larger than the number of logical blocks included in the logical segment associated with the physical segment. Therefore, the number of effective blocks obtained by subtracting the number of congenital and acquired bad blocks from the number of physical blocks included in each physical segment is the number of logical blocks included in the logical segment associated with the physical segment. If there is more, the free block cannot be secured in the physical segment.

  In addition, even if the number of valid blocks included in each physical segment is equal to or less than the number of logical blocks included in the logical segment associated with the physical segment, the physical block used (data is stored). If there are few physical blocks), it is not possible to secure an empty block in the physical segment. In other words, even when the number of valid blocks included in each physical segment is equal to or less than the number of logical blocks included in the logical segment associated with the physical segment, it is not necessary to combine a plurality of physical segments. In some cases.

  Considering these points, when the number of valid blocks included in each physical segment is equal to or less than the number of logical blocks included in the logical segment associated with the physical segment, the physical segment is included. A plurality of physical segments may be combined, but a plurality of physical segments may be combined after waiting for a free block to be secured in the physical segment.

  FIG. 17 shows a configuration example of an address conversion table created by the memory controller 3.

  When a predetermined event related to a certain logical segment occurs at any stage described above (for example, when a data write request for a logical block in the logical segment is received from the host system 4), the memory controller 3 The address translation table for the physical segment associated with the logical segment is created as follows. That is, the memory controller 3 scans all the physical blocks in the physical segment corresponding to the logical segment and stores them in the redundant area 26 of each physical block (for example, the redundant area of the first page of each physical block). Read the additional data (logical address information, block status, etc.). Then, the memory controller 3 creates an address conversion table as shown in FIG. 17 for the physical segment based on the logical address information read from each physical block in the physical segment.

  Here, as the logical address information, information that can specify a logical block, for example, LBN and LZIBN can be used, but it is preferable to use LZIBN with a small amount of information. Since LZIBN is a serial number assigned to the logical block included in the logical zone, even if all the physical segments in the physical zone are combined, it is written as logical address information in the redundant area of each physical block. The logical block corresponding to each physical block can be specified based on the LZIBN. Assuming that the serial number assigned to the logical block included in the logical segment is used as the logical address information, if the logical address information is not rewritten when the physical segments are combined, the number is duplicated. It becomes impossible to specify the logical block corresponding to.

  In this address conversion table, for example, as shown in FIG. 17, the LZIBN of each logical block included in the logical segment and the PZIBN of the physical block corresponding to each logical block are described in association with each other. . Here, when there is no physical block corresponding to the logical block, that is, when data corresponding to the logical block is not written in any physical block, information indicating that fact (“ "No") is described in the form associated with the logical block. For example, data corresponding to the logical block of LZIBN # 24 is not written in any physical block.

  When writing or reading data, the memory controller 3 converts a logical address into a physical address based on the correspondence between the logical block and the physical block described in the addressless conversion table as described above. When data is written to an empty block, the correspondence between the logical block and physical block corresponding to the data changes, so the address conversion table is updated.

  Since the address translation table is created in units of physical segments, the smaller the size of the physical segment, the smaller the processing load for creating the address translation table, and the memory access ends in a shorter time. Considering this, the size of the physical segment is minimized in the first stage. When it becomes impossible to operate in the first stage, that is, when it becomes impossible to secure an empty block, the process moves to the second stage, and further, when it becomes impossible to operate in the second stage. Then, the process proceeds to the third stage. By moving to the next stage in this way, the size of the physical segment is increased stepwise, so the processing load for creating the address translation table increases, but it is avoided that it becomes inoperable. Thus, there is a trade-off relationship between a request for reducing the processing load for creating the address conversion table and a request for avoiding the inoperability. According to the present embodiment, the size of the physical segment is adjusted stepwise so as to reduce the processing load for creating the address translation table as much as possible within a range that can satisfy the requirement to avoid inoperability.

  If the operation cannot be performed in the second stage, there is no physical segment in the physical zone, and an address conversion table is created for each physical zone.

  When the memory controller 3 reads the additional data (logical address information, block status, etc.) of all the physical blocks in a certain physical segment as described above, the memory controller 3 not only creates an address conversion table but also each physical block. Based on the block status, the number of defective blocks in the physical segment is grasped, and the level of the free block securing capability of the physical segment (typically, the number of free blocks that can be secured) is grasped. Then, the memory controller 3 determines whether or not the physical segment is normally usable (or is highly likely to be unusable) based on the grasped level of the free block securing capability. As a specific method of this determination, for example, the following method can be adopted.

  That is, the number of logical blocks allocated to one physical segment in each stage is m (for example, 125 in the first stage, 250 in the second stage, 500 in the third stage), and one physical segment in each stage. The number of physical blocks included in n is n (eg, 128 in the first stage, 256 in the second stage, 512 in the third stage), and the minimum allowable number of spare physical blocks set in advance is k (eg, 1). When the number of bad blocks in the physical block exceeds “nmk” (predetermined threshold value), the physical segment may not be normally usable (or may not be normally usable). Is determined to be high), and multiple segments are combined.

  The above determination method does not take into consideration whether each physical block is empty (that is, whether data is stored, in other words, whether it is unused). It can also be taken into account. That is, when the number of empty (unused) logical blocks in the logical segment becomes 0, a plurality of segments may be combined.

  In the first embodiment described above, each physical zone is divided into a plurality of physical segments, an address conversion table is created in units of physical segments, and when the number of defective blocks increases, a plurality of physical segments are combined. Control to make the physical segment larger. As a modification, the same control may be performed on the physical zone instead of the control performed on the physical segment.

  Next, a second embodiment according to the present invention in which such control is performed on the physical zone will be described.

  In the second embodiment, the address conversion table is created for each physical zone without dividing the physical zone into physical segments. Further, in the initial stage, the size of the physical zone is minimized, and when an empty block cannot be secured in the physical zone, a plurality of physical zones are combined to move to the next stage.

  In the second embodiment described below, there are 64 physical zones in the first stage (initial stage), and each physical zone includes 128 physical blocks. When shifting from the first stage (initial stage) to the second stage, the number of physical zones decreases from 64 to 32, and the number of physical blocks included in each physical zone increases from 128 to 256. . When shifting from the second stage to the third stage, the number of physical zones decreases from 32 to 16, and the number of physical blocks included in each physical zone increases from 256 to 512.

  The number of logical zones is 64, which is the same as the number of physical zones in the first stage (initial stage), and each logical zone includes 125 logical blocks. In the first stage (initial stage), one logical zone is associated with one physical zone, and in the second stage, two logical zones are associated with one physical zone, In the third stage, four logical zones are associated with one physical zone.

<Description of the first stage>
FIG. 18 shows the correspondence between the physical zones and logical zones in the first stage (in FIG. 18, only the logical zones LZN # 0 to # 7 and the physical zones associated with these logical zones are shown. It is shown).

  As shown in FIG. 18, one physical zone including 125 physical blocks is associated with one physical zone including 128 physical blocks. For example, the physical zone of PZN # 0 is associated with the logical zone of LZN # 0, the physical zone of PZN # 1 is associated with the logical zone of LZN # 1, and the physical zone of PZN # 2 is associated with LZN #. Two logical zones are associated.

As shown in FIG. 18A, the logical address space is distributed so that logical blocks having consecutive LBNs are distributed in different logical zones, as in the case of the first embodiment. In the second embodiment, since the number of logical zones is ²⁶ (64), logical blocks are allocated based on the value of the lower 6 bits of LBN. That is, as shown in FIG. 19A, the lower 6 bits of the LBN correspond to the LZN of the logical zone of the distribution destination.

As shown in (b) of FIG. 18, the physical address space, ^{2 6} are divided into physical zones (64), the physical block of ^{2 seven} that PBA is continuous because each zone (128) It is included. That is, as shown in FIG. 19B, the upper bits excluding the lower 7 bits of the PBA, that is, the upper 6 bits of the PBA correspond to the PZN of the physical zone in which each physical block is included.

<Explanation of the second stage>
Thereafter, when at least one physical zone reaches a predetermined coupling level, the second stage is entered. Examples of the predetermined combination level include when the number of defective blocks in the physical zone reaches a predetermined number, or when it becomes impossible to secure an empty block in the physical segment.

  FIG. 20 shows the correspondence between the physical zones and the logical zones in the second stage (in FIG. 20, only the logical zones LZN # 0 to # 7 and the physical zones associated with these logical zones are shown. It is shown).

When the transition from the first stage to the second stage, because the physical zones are coupled two by two, the number of physical zones becomes 2 ⁵ (32), the number of physical blocks included in each physical zone 2 It becomes ⁸ pieces (256 pieces).

  In the second stage, two physical zones are associated with one physical zone. For example, the physical zone of PZN '# 0 that combines the physical zones of PZN # 0 and PZN # 1 is associated with the logical zones of LZN # 0 and LZN # 1 corresponding to GN (group number) # 0. The physical zone of PZN ′ # 1 obtained by combining the physical zones of PZN # 2 and PZN # 3 is associated with the logical zones of LZN # 2 and LZN # 3 corresponding to GN (group number) # 1.

  Here, GN (group number) corresponds to the value indicated by the upper 5 bits of LZN, that is, the bits from the 2nd bit to the 6th bit counted from the lower side of LBN, as shown in FIG. 21A. As shown in FIG. 21B, PZN ′ corresponds to the upper bits excluding the lower 8 bits of PBA, that is, the value indicated by the upper 5 bits of PBA.

<Explanation of the third stage>
After the transition to the second stage, the transition to the third stage is made when at least one physical zone reaches a predetermined coupling level. Examples of the predetermined combination level include when the number of defective blocks in the physical zone reaches a predetermined number, or when it becomes impossible to secure an empty block in the physical segment.

  FIG. 22 shows the correspondence between the physical zones and logical zones in the third stage (in FIG. 22, only the logical zones LZN # 0 to # 7 and the physical zones associated with these logical zones are shown. It is shown).

When the transition from the second stage to the third stage, the physical zone is coupled two by two, the number of physical zones becomes 2 ⁴ (16), the number of physical blocks included in each physical zone 2 It will be ⁹ (512).

  In the third stage, four physical zones are associated with one physical zone. For example, PZN "# 0 physical zone (PZN" # 0 physical zone combined with PZN # 0 to # 3 physical zones) that combines PZN '# 0 and PZN' # 1 physical zones, A physical zone (PZN) of PZN ″ # 1 in which the physical zones of LZN # 0 to # 3 corresponding to GN ′ (group number) # 0 are associated and the physical zones of PZN ′ # 2 and PZN ′ # 3 are combined. The logical zones of LZN # 4 to # 7 corresponding to GN ′ (group number) # 1 are associated with PZN ″ # 1 physical zone obtained by combining the physical zones of # 4 to # 7.

  Here, GN ′ (group number) corresponds to the value indicated by the upper 4 bits of LZN, that is, the bits from the 3rd bit to the 6th bit counted from the lower side of LBN, as shown in FIG. 23A. . As shown in FIG. 23B, PZN ″ corresponds to the upper bits excluding the lower 9 bits of PBA, that is, the value indicated by the upper 4 bits of PBA.

  Since LZIBN is a serial number in each logical zone, when LZIBN is used as logical address information, when a plurality of logical zones are associated with the same physical zone, it corresponds to a physical block included in the physical zone. It becomes impossible to determine which logical zone the logical block is included in. Therefore, a non-overlapping serial number (hereinafter referred to as LBI (logical block index)) is assigned to a logical block included in a plurality of logical zones that may be associated with the same physical zone, and the assigned LBI is assigned a logical address. It is preferably used as information. In the case of the second embodiment, for example, the LBI may be a combination of the upper 7 bits of the LBN and the lower 2 bits of the LBN.

  As described in the first embodiment and the second embodiment of the present invention, the areas covered by one address conversion table are different at each stage. That is, in the first embodiment, the size of the physical segment (the number of physical blocks included in the physical segment) differs at each stage, and in the second embodiment, the size of the physical zone (included in the physical zone) at each stage. The number of physical blocks is different. Therefore, it is preferable to store information indicating what stage is currently operating (hereinafter referred to as physical address space management information) in a specific physical block in the flash memory. Then, when the next stage is entered, the physical address space management information may be rewritten. In the case of the first embodiment, for example, the number of physical segments in the physical zone may be stored as physical address space management information. In the case of the second embodiment, for example, the number of physical zones may be stored as physical address space management information.

  As mentioned above, although two embodiment of this invention was described, these are the illustrations for description of this invention, and are not the meaning which limits the scope of the present invention only to these embodiment. Therefore, the present invention can be implemented in modes other than the above-described embodiments without departing from the gist thereof.

1 is a block diagram showing an overall configuration of a flash memory system 1 according to a first embodiment of the present invention. 2 is a diagram showing a configuration of a physical address space of a memory cell array in the flash memory 2. FIG. FIG. 3 is a diagram showing a configuration of logical zones and logical blocks in a logical address space shared by a memory controller 3 and a host system 4. The figure which shows the bit structure of LBA (logical block address). The correspondence relationship between logical zones, physical zones, and physical blocks is shown. The figure which shows the bit structure of PBN (physical block number). The figure which shows the structure of each physical block. The figure which shows the bit structure of LSN and PSN. The block diagram which shows the structure of the logical segment defined on a logical address space. The figure which shows the bit structure of LBN in the 1st step to the 3rd step. The figure which shows the correspondence of the logical segment and physical segment in a 1st step. The figure which shows the bit structure of LBN and PBA in a 1st step. The figure which shows the correspondence of the logical segment and physical segment in a 2nd step. The figure which shows the bit structure of LBN and PBA in a 2nd step. The figure which shows the correspondence of the logical segment and physical segment in a 3rd step. The figure which shows the bit structure of LBN and PBA in a 3rd step. The figure which shows the structural example of the address conversion table which the memory controller 3 produces. The figure which shows the correspondence of the logical zone and physical zone in a 1st step. The figure which shows the bit structure of LBN and PBA in a 1st step. The figure which shows the correspondence of the logical zone and physical zone in a 2nd step. The figure which shows the bit structure of LBN and PBA in a 2nd step. The figure which shows the correspondence of the logical zone and physical zone in a 3rd step. The figure which shows the bit structure of LBN and PBA in a 3rd step.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 13 External bus 14 Internal bus 25 User area 26 Redundant area 31 Unit area management part 32 Address management Part 33 Physical area coupling part

Claims (8)

A memory controller that controls access to a flash memory that is erased in physical block units based on logical addresses in logical sector units given from a host system,
Unit area management means for managing a correspondence relationship between a plurality of unit logical areas, each of which is a set of a plurality of logical sectors, and a plurality of unit physical areas, each of which is a set of a plurality of physical blocks; ,
Address management means for managing the correspondence between the logical address included in each unit logical area and the physical address included in each unit physical area corresponding to each unit logical area;
A physical region combining means that combines two or more unit physical regions into an expanded unit physical region;
The unit area management means associates two or more unit logical areas corresponding to the two or more unit physical areas before combination with the expanded unit physical area after combination.
Memory controller. At least one unit physical area of the two or more unit physical areas combined by the physical area combining means includes a preset number of defective blocks or more.
The memory controller according to claim 1. The number of the plurality of unit physical regions and the number of the two or more unit physical regions combined by the physical region combining means are both numerical values given as powers of 2.
The memory controller according to claim 1 or 2. Logical block area distribution means for distributing a plurality of logical block areas continuous in a logical address space to the plurality of unit logical areas;
Each of the logical block areas includes a plurality of the logical sectors in which the logical addresses are continuous,
The number of the logical sectors belonging to the logical block area and the number of the plurality of unit logical areas are both numerical values given as powers of 2.
The memory controller according to claim 1. When the number of the logical sectors belonging to the logical block area is 2 ⁱ and the number of the plurality of unit logical areas is 2 ^j , i + 1 counted from the lower side of the logical address of the logical sector Identifying the unit logical area including the logical block area to which the logical sector belongs and the unit physical area corresponding to the unit logical area based on the value of the bit from the bit to the i + jth bit.
The memory controller according to claim 4. Flash memory that is erased in physical block units,
A flash memory system comprising the memory controller according to claim 1. A method for controlling access to a flash memory to be erased in physical block units based on logical addresses in logical sector units given from a host system,
Managing a correspondence relationship between a plurality of unit logical areas, each of which is a set of a plurality of logical sectors, and a plurality of unit physical areas, each of which is a set of a plurality of physical blocks;
Managing a correspondence relationship between a logical address included in each unit logical area and a physical address included in each unit physical area corresponding to each unit logical area;
Combining two or more unit physical areas into an expanded unit physical area;
A step of associating two or more unit logical areas corresponding to the two or more unit physical areas before combination with the expanded unit physical area after combination. Control method. Determining whether or not there is a free block in each unit physical area;
When it is determined that there is no empty block in each unit physical area, the two or more unit physical areas are combined.
The control method according to claim 7.

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