JPH01135189A - Picture memory - Google Patents

Abstract

PURPOSE:To eliminate flicker of a displayed picture by dividing a picture memory into two memories, frame memory and buffer memory and controlling the write/readout so as to attain rewrite at an optimum position between the two memories. CONSTITUTION:Data transfer between the memories 1, 2 is executed when a reference comparison signal E is at a 'H' level, that is, at the time of 14th readout. When the signal E reaches the 'H' level, a signal D at the output of an AND circuit 8 goes to the 'H' level during a TW period and an address B latched by a latch circuit 4 during the TR is outputted as a write address of the memory 2 from a switch circuit 3, data read from the memory 1 is outputted from a data latch circuit during a period TR by using a write pulse G from a write pulse generating circuit 7 and written in the memory 2. That is, the data of the memory 1 of the same memory location is written in the address of the memory 2 from which the data is read by 14 times. Thus, the flicker of the displayed picture is avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video image memory for writing and reading out digital video signals in a video processing device.
In particular, it relates to improvements in the control operation of the control circuit.

[Conventional technology]

FIG. 3 is a block diagram of a conventional image memory write/read circuit. In the figure, 6 is a latch circuit for read data, and 9 is an image memory.

Next, the operation will be explained. Writing to the image memory is performed by writing image data A to a memory address specified by a write address signal B using a write pulse C. Reading from the image memory is possible because the memory chip select signal J is always enabled.
A write address and a read address are specified by specifying the read address using the address signal B sent in a time-division manner, and the image data signal H of the memory address is outputted at any time. This output data is latched by a latch circuit 6 in response to a read data latch signal, and is output as image data output I. FIG. 4 shows the operation timing.

The data read here is 6 bits, and can be expressed as image information as data of 2b=64 gradations. This is called brightness data, but in order to display this 6-bit brightness data on a display device, the intensity of brightness expressed by 6 bits at a certain point is replaced with lighting time.
The bit digital value is converted into a pulse width.

The method of converting into this pulse width will be explained below.

One screen of the video signal is updated every 1/60 seconds, and the contents of the image memory are also rewritten every 1/60 seconds.

Focusing on one point on the display device, this point is also turned on/off every 1/60 seconds, or the brightness of the point is changed every 1/60 seconds, as described above. This is 6
It is expressed as bit-64 gradation brightness data. In other words, when all 6 bits of data are "1", the brightness is W
It shows that it is the ax value, and when it is all "0", it shows the Min value, that is, the point is not lit (black).

In order to convert this 6-bit luminance data into a pulse width (length) corresponding to the data within 1/60 second, the 6 bits are divided into the lower 3 bits and the upper 3 bits, and the lower and upper 3 bits are compared to the standard comparison value. Each time is compared separately and converted to pulse width.

As shown in Fig. 5, 1/60 seconds is divided into 14 stages, the lower 3 bits are divided into each substage a of T I"' T7, and the upper 3 bits are divided into each substage of T8 to TI4. Then, the lighting of the substage is controlled by the data. Here, the substage t2 between T ll'' T + 4 has a period seven times as long as the substage 1 from T1 to T7.

Such an operation is performed for 1/60 second to convert it into a pulse width of a certain length.

This situation will be explained in more detail using the flowchart shown in FIG. That is, this conversion operation is as shown in FIG.
First, load the lower 3 bits of the data (Step S1)
, 61', step S2), and 6M, outputs "H" or "L" of a predetermined pulse width (step S3). Thereafter, in steps 84 to S6, it is sequentially compared with the comparison values 58.48.38.2M, 1H, and ON, so that a pulse with a pulse width equal to the value of the lower three bits is output. Next, in step S8,
The upper three bits are loaded and first compared with the comparison value Qll (step S9). At this time, the upper 3 bits and the comparison value Ql
“H” or “L” with a pulse width 7 times that of the lower 3 bits is output depending on whether it is large or small with + (step 510).
. In the following steps 311 to S12, the comparison value is 18.
, 211°3H, 48, 51 (by comparing with
Together with the pulse corresponding to the value of the lower 3 bits, the conversion of the 6-bit luminance data into a pulse width is completed (step 5).
13). The above operation is then repeatedly executed every 1/60 seconds (step 514).

Although the above explanation focused on one point, the same operation must be performed for the entire screen on the display device in 1/60 seconds. Therefore, by comparing other points during the time between comparing one point and another (for example, between 6M and 5H in Figure 6), time loss can be eliminated and the entire screen can be efficiently collected in 1/60 seconds. is converted into pulse width.

The 6-bit data read from the image memory as described above is displayed on the display device.

Looking at writing to and reading from image memory, writing is performed in order from the lower address to the upper address of the memory every 1/60 seconds, while reading is as described above in the conversion to pulse width. As shown, the specified addresses are not compared in order from lower to upper, but in a fixed pattern, each address in all memory is compared the above number of times in 1/60 seconds, that is, 7 times at the bottom and 7 times at the top. Each is read out a total of 14 times. Therefore 1/60
14 reads for every 1 write to memory per second
This is performed once for all memory addresses.

[Problem that the invention seeks to solve]

Since the conventional image memory write/read circuit is configured as described above, writing and reading are performed asynchronously. For example, data is rewritten between the comparison of T7 and the comparison of T8 in FIG. I can't control it,
There was a problem that flickering occurred on the display screen.

This invention was made to solve the above-mentioned problems, and aims to provide an image memory that can eliminate flickering on a display screen and improve image quality.

[Means for solving problems]

In the image memory according to the present invention, in addition to the field memory, a buffer memory of the same capacity is installed as the image memory, and the writing of the video signal is divided into two parts: writing to the field memory and reading from the buffer memory. The timing of data transfer between the buffer memory and the buffer memory is controlled to the optimum timing by a transfer control signal generating circuit.

[Effect]

In the present invention, the transfer control signal generation circuit detects the optimum data transfer timing from the field memory to the buffer memory, and generates the transfer memory address and data as well as its write pulse, so that Since the rewriting is controlled to be executed after 14 reads per address and before the first read of the next field occurs, flickering on the display screen is eliminated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an image memory according to an embodiment of the present invention, and in the figure, the same or corresponding parts as in FIG. 3 are designated by the same reference numerals. 1 is an image field memory in which image data A is written to a specified address B by a write signal C;
4 is a circuit that latches the designated address B based on the read launch signal, 7 is a circuit that generates a write pulse G based on the AND of the launch signal and the reference comparison signal E, and 3 is specified by the AND value mentioned above. An address switch circuit 5 selects address B and designated address B latched by the latch circuit 4;
This is a data latch circuit that outputs data.

Further, 2 is an image buffer memory in which the image data output from the data latch circuit 5 is written using the selected output address F and the write pulse G, and the image data is output based on the launch signal, and 6 is the image data from the image buffer memory 2. This is a launch circuit that latches the data using a latch signal and outputs it as read image data I. Reference numeral 10 denotes a transfer control signal generation circuit that detects the optimum data transfer timing from the field memory to the buffer memory 2 and generates a transfer control signal, and the address switch circuit 3
, an address launch circuit 4, data latch circuits 5 and 6, a write pulse generation circuit 7, and an AND circuit 8.

Next, the operation will be explained.

FIG. 2 shows an operation timing diagram of each component in the present invention. In the figure, T, TR, and 'rw indicate write/read periods. Writing to the image field memory 1 is the same as in the conventional method, and data A is written by a write pulse C to an address B that is entered during the T period of the launch signal. During the TR period, data is read from the image field memory 1 and data is read from the image buffer memory 2.
The data read from the buffer memory 2 is compared with a reference comparison value in a manner similar to the conventional method, and converted into a pulse width corresponding to the reference comparison value.

Data transfer between memories 1 and 2 is performed when the reference comparison signal E is “H”.
" level, that is, when the 14th read occurs.During the read period from the 1st to the 13th time, the output of the AND circuit 8 is always at the "L" level, and therefore the G signal is always at the "H" level during this period. In addition, the address B which is not latched by the latch circuit 4 is output as is for the F signal.However, the address latch circuit 4 latches the B signal, and the latch circuit 5 latches the read data of the memory 1. This is always done by standing up.

When the E signal is at the "H" level, the output of the AND circuit 8 becomes "H" during the period when the D signal is at the "H" level, that is, the T period in FIG.
” level, the address B latched by the latch circuit 4 during the TR period is output from the switch circuit 3 as the write address of the memory 2, and the data read from the memory 1 during the TR period by the write pulse G from the write pulse generation circuit 7. is output from the data latch circuit 5 that has latched the data, and is written to the memory 2. That is, as shown in the timing diagram of FIG. Data will be written. Since this is done for all memory areas, data will not be rewritten during the comparison, and data will always be rewritten after the 14th read.

In this way, since data is written after the 14th reading, flickering on the display screen is eliminated and image quality can be improved.

Note that in the above embodiment, frame memory 1. Although the buffer memory 2 is shown as having a type of memory that can also be used as an 8-bit input/output pin, a 1-bit manual/output separation type memory may be used in 1.2.

〔Effect of the invention〕

As described above, according to the image memory according to the present invention, the image memory is divided into two memories, a frame memory and a buffer memory, and writing is performed so that rewriting can be performed at an optimal position between the two memories.

Since reading is controlled, flickering on the display screen can be eliminated and image quality can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an image memory according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of an embodiment of the invention, and FIG. 3 is a block diagram showing a conventional video image memory control circuit. 4 is a timing chart in the prior art, FIG. 5 is a diagram showing a comparison method related to the present invention, and FIG. 6 is a flowchart showing the comparison method in FIG. In the figure, 1 is an image field memory, 2 is an image buffer memory, 3 is an address switch circuit, 4 is an address latch circuit, 5 is a latch circuit for field memory data, 6 is a latch circuit for buffer memory data, and 7 is a write pulse generation 8 is an AND circuit, and lO is a transfer control signal generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) An image memory in which A/D converted video information is written and read at any time, including a field memory for writing the video information, and a field for reading the video information transferred from the field memory. A buffer memory with the same capacity as the memory, and a transfer control signal generation circuit that detects the optimal data transfer timing that does not overlap writing and reading and generates a data transfer control signal from the field memory to the buffer memory. An image memory characterized by comprising: