JPH01134936A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the characteristics of writing and erasing operations by a method wherein electrode layers are formed in lamination through the intermediary of insulating layers comprising oxide films which are three layer structured by forming nitrooxide layers on both surfaces thereof. CONSTITUTION:A polysilicon made floating gate electrode 15 is formed on the surface of a silicon substrate 11 through the intermediary of an insulating layer 14. Next, another polysilicon made floating gate electrode 17 is formed on the electrode 15 through the intermediary of another insulating layer 16. Then, the other insulating layer 18 is formed encircling the electrodes 15 and 17. The insulating layers 14, 16, 18 are mainly formed of oxide films 141, 161, 181 comprising silicon oxide. Nitrooxide layers 142, 162, 182 are formed on respective both sides of the oxide films 141, 161, 181. Through these procedures, the characteristics of writing and erasing operations can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for reducing traps in the insulating layer and making it difficult for traps to occur when electrode layers are laminated with an insulating layer interposed therebetween. The present invention relates to a semiconductor device and a method for manufacturing the same.

[Prior Art] For example, EPROM, E2 ROM, etc. 17) In a nonvolatile memory, a floating gate electrode is formed on the surface of a silicon semiconductor substrate with an insulating layer of silicon oxide film interposed therebetween, and a floating gate electrode is further formed on the floating gate electrode. In this case, a control gate electrode is formed through an insulating layer made of a silicon oxide film.

In such semiconductor devices, traps are easily induced due to damage such as dry etching performed during the manufacturing process, and traps are easily induced in this insulating layer. Then,
In EPROM, E2 ROM, etc., the data charge retention characteristics deteriorate, making it difficult to improve reliability as a memory.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points. It is an object of the present invention to provide a semiconductor device in which reliability in operating characteristics can be reliably obtained by reducing traps and making it difficult to induce traps, and also to provide a method for manufacturing such a semiconductor device.

Means for Solving Problem L] That is, in the semiconductor device according to the present invention, when an electrode layer is formed on the surface of a semiconductor substrate via an insulating layer made of an oxide film, the above-mentioned insulating layer The oxide film has a three-layer structure in which nitride layers are formed on each side of the oxide film, and for this purpose, a nitrogen-based reaction such as NH3 is used to form the oxide film layer. A rapid heat treatment is performed in a gas to form nitroxide layers on both sides of the oxide film, and an electrode layer is formed on the three-layer insulating layer with nitroxide layers formed on both sides. It is something.

Then, the electrode layer is further surrounded by an oxide film layer, and this oxide film layer is subjected to rapid heating treatment in a nitrogen-based reactive gas atmosphere in the same manner as described above.

[Function] If an EPROM or an E2 PROM is configured in this way, the outer periphery of the floating gate electrode and the control gate electrode will be surrounded by an insulating layer with a 31-layer structure in which nitroxide layers are formed on both sides of the oxide film. This results in a state in which there are fewer traps and in which traps are less likely to occur. Therefore, for example, the data charge retention characteristics can be stably set, and the reliability of the operating characteristics of semiconductor devices such as EPROM and E2 PROM can be effectively improved. The three-layer insulating layer described above can be easily obtained by rapid heating treatment of the oxide film layer in a nitrogen atmosphere, and such semiconductor devices are designed to have stable characteristics. It can be easily manufactured.

[Embodiments of the invention] The present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional configuration of one memory element portion in an EPROM according to an embodiment of the present invention, in which a drain region 12 and a source region 13 are formed in a P-well region portion of a silicon substrate 11. has been done. and,
On the surface of this silicon substrate 11 is an insulating film that becomes a tunnel oxide film! A floating gate electrode 15 made of polysilicon is formed via 114 . A control gate electrode 17 made of polysilicon is further formed on this floating gate electrode 15 with an insulating layer 16 in between, and is insulated so as to surround the floating gate electrode 15 and the control gate electrode 11. [118 is formed.

Here, the insulators 1114.1B and 17 are silicon oxide (silicon oxide) obtained by heat treatment in an oxygen atmosphere, respectively.
Oxide films 141, 161 and 1 made of (Si 02 )
The silicon oxide films 141, 161 and 181 are each coated with nitroxide m<nitride oxide $9) on both sides of the silicon oxide films 141, 161 and 181, respectively.
42, 162 and 182 are formed, and each of these insulating layers 14, 16, and 18 has a three-layer structure.

On the silicon substrate 11, 20 BPSG layers are formed so as to cover the electrode parts.
SG layer 20 layer type 0 and the drain 12 and source 1
Metal wirings 21 and 22 made of aluminum are taken out from three parts, respectively. 23 is a protective passivation.

FIG. 2 sequentially shows the manufacturing process of a semiconductor device such as the one described above, particularly one memory cell portion of an EPROM. First, as shown in FIG. 2A, in the P well formation region of the silicon substrate 11, A field oxide film region is formed by the so-called LOCO8 method, and an S layer with a thickness of 200 to 500 layers is formed on such a silicon substrate 11.
Oxidation lll31 is formed by iO2. This oxide film 3
A layer 32 of 1,000 to 2,000 layers of silicon nitride (<813 N4) was further formed on top of the silicon nitride layer 32, and its pattern shape was set by photolithography and etching techniques. And this silicon nitride l! ! 3
Boron ions are implanted into the silicon substrate 11 using No. 2 as a mask to form a stopper region 33 of a P+ channel. field oxide 11934 was formed.

The oxide film 31 and silicon nitride layer 32 are removed in this state, and in this removed state they are shown in FIG.
Gate oxidation with silicon oxide film of 200 to 500 people as shown in I! 135 is formed.

Once the gate oxide 1135 is formed in this way,
This semiconductor substrate 11 is set in a nitrogen-based gas atmosphere and rapidly heated to form a nitroxide layer 3 on each side of the gate oxide 1135 as shown in the second diagram.
1.352 is formed.

Here, a method for forming the gate oxide film 35 with nitroxide layers 351 and 352 formed on both sides will be described in detail. Figure 3 shows gate oxidation m35 on silicon substrate 1.
1, the silicon substrate 11 is first set in a processing chamber, and in this state, the first step 51 of evacuation of the chamber is performed. .

Once the processing chamber has been evacuated to a vacuum state, a second step 53 of introducing a reactive gas such as 82 and HCffi into the chamber is carried out, followed by a third step 53.
The temperature is raised to remove a poor quality natural oxide film formed on the surface of the silicon substrate 11 in the air or by chemical treatment. For example, in this step 53, 6
A heat treatment is performed for 0 seconds, and the temperature is lowered in a fourth step 54.

Once the temperature inside the chamber is lowered in this way,
In the fifth step 55, the inside of the chamber is evacuated and depressurized, and in the sixth step 56, 02 (oxygen) or 02 and H
CR (hydrochloric acid gas) is introduced. Once the silicon substrate 11 in the chamber is set in the oxygen atmosphere in this way, the temperature of the silicon substrate 11 in the chamber is raised in a seventh step 57, and a gate oxide film 35 is formed on the surface of the silicon substrate 11. A silicon oxide film is formed as shown in FIG. Here, the temperature raising process in step 57 uses a heat source such as a halogen lamp or an arc lamp to rapidly raise the temperature.
By rapidly oxidizing the surface of 1, a silicon oxide film is formed.

After the gate oxide film of silicon oxide is formed on the surface of the silicon substrate 11 in this way, the inside of the chamber is raised in an eighth step 58, and then in a ninth step 59.
Evacuate the chamber by depressurizing it.

In the next tenth step 60, NH3, which is a nitrogen-based reactive gas, is introduced into the vacuum-evacuated chamber, and in the eleventh step 61, with the reactive gas introduced, the silicon substrate 11 is to be rapidly heated by rapid heating means using the above halogen lamp or arc lamp,
Rapid nitridation (RTN) is performed. This nitriding step is performed at, for example, 1150° C. for 30 seconds.

After the nitriding process is performed in this manner, a temperature-lowering process is performed in a twelfth process 62, and nitrogen is introduced into the chamber in a thirteenth process 63, and the silicon substrate 11 is taken out.

FIG. 4 shows a schematic configuration of an apparatus for carrying out the above-described processing, in which a silicon substrate 11 is inserted and supported in a quartz chamber 65. Gas introduction ports 66 and 67 are formed in this chamber 65, N2 is introduced from the introduction port 67, and NH2 is introduced from the introduction port 67.
Reactive gases such as 3,02, N2, and Cβ are selectively introduced. A discharge port 68 is further formed in the chamber 65, and the inside of the chamber 65 is selectively depressurized and evacuated through the discharge port 68 by a vacuum pump (not shown).

A halogen lamp 6 is provided on the outer periphery of the quartz chamber 65.
A heating mechanism according to 9 is provided. The halogen lamp 69 rapidly heats the silicon substrate 11 in the chamber 65. Although details are not shown, the above heating temperature is observed by a temperature sensor within the quartz chamber 65, and the halogen lamp 69 is controlled so that this heating temperature is set to the target temperature state. I have to.

That is, by introducing a nitrogen-based reaction gas NH3 into the chamber 65 as in the tenth step 60 and performing rapid nitriding in the next step 61, a night O oxide layer is formed on both sides as shown in the second diagram. 351.352 is formed, and the structure is such that a silicon oxide layer exists between the nitroxide layers 351 and 352. here,
The rapid nitriding (RTN) step in the eleventh step 61 is 1
．． The condition of the night O oxide layer was confirmed by Auger analysis, which was carried out at 1100 to 1250 DEG C. for 30 seconds to 300 seconds, and the condition was as shown in FIG. 5. Here, the silicon oxide film of 105 people was rapidly heated in NHs at 1150°C and subjected to rapid nitriding treatment (R
It was confirmed that by adjusting the heating time, a three-layer oxide film layer having nitroxide layers on both sides was formed. It was confirmed that even if the thickness of the silicon oxide film was made even thicker, a similar three-layer structure could be obtained; It is necessary to lengthen the nitriding treatment time by heating. In this figure, the interface is the interface between the gate oxide film 35 and the silicon substrate 11.

Once the gate oxide layer 1135 with the nitroxide layers 351 and 352 on both sides is formed in this way, the first polysilicon layer 36 of N1 type is formed to a thickness of 3000 to 5000 nm, as shown in FIG. 2E. 2F on this polysilicon layer 36.
As shown in , an oxide film layer 37 of silicon oxide is formed by thermal oxidation. Then, this oxidized m-layer 37 is subjected to rapid nitriding treatment in the same manner as in the case of the gate oxide film 35, and as shown in FIG.
Nitro oxide layers 371 and 372 are formed on both surfaces as shown in FIG.

Once oxide 11137 with nitroxide layers 371 and 372 on both sides is formed in this way,
On top of that is a second polysilicon It! with a thickness of 3,000 to 5,000 as shown in FIG. 2H. form 38. Then, in this state, using the resist as a mask, the second polysilicon 11138, the oxide film @37, and the first polysilicon l
113B is removed by etching, e.g.
The floating gate and control gate in the first and second polysilicon! ! 36 and 38
so that it is cut out and formed by. Then, a thermal oxide layer 139 is formed on the outer periphery of these gate groups as shown in FIG. 2 (■), and as shown in FIG. Nitrooxide layers 391 and 392 are formed. And this includes the source, drain, and BPS.
By forming an interlayer insulating layer made of G, an aluminum wiring layer, etc., a semiconductor device as shown in FIG. 1 is constructed.

Figure 6 shows how the number of traps decreases when the silicon oxide 111 layer is made into a three-layer structure with nitroxide layers on both sides. Electrons were injected into the silicon oxide film and changes in gate voltage were measured. A state in which there is little change in gate voltage vg means that there are few electrons or holes trapped in the silicon oxide film. become. That is, compared to the case where the rapid nitriding time was 0 seconds, the traps were sufficiently reduced when the rapid nitriding time was 10 seconds and 30 seconds.

A possible reason for the decrease in the number of traps is that the strain bond, which is said to be the cause of the St -0 trap, is relaxed as nitridation progresses rapidly. In other words, in the case of only a silicon oxide film, there is a distorted stray bond near the interface of St-8 (02), but by performing rapid nitriding, a certain type of nitroxide film is formed near the interface. It is thought that this formation reduces the strain at the interface and reduces the number of traps.

Therefore, with such a three-layer structure, for example, EPR
If the gate oxide film layer or other insulating layer of OM, Et PROM is formed, there will be no deterioration of the charge retention state, and even if data is written and erased repeatedly, the threshold voltage will decrease. This is a state in which it is not possible.

Figure 7 shows a short channel, for example, an N-channel MO.
This shows an example of configuring an S transistor, in which an insulating layer 72 made of a silicon oxide film formed on a silicon substrate 71 is coated with a nitroxide layer 721 on both sides.
It is structured in a three-cabin structure with 722 and 722 cabinets. Then, an electrode 73 made of polysilicon is formed on this insulating layer 72, and the outer periphery of this electrode 73 is further surrounded by an insulating layer 74 made of an oxide film, and this insulating layer 74 also has nitroxide layers 741, 742 on both sides.
It has a three-layer structure with .

That is, when the MOS transistor is configured in this manner, both the deterioration of GM due to hot electrons and the change in VT are extremely small, and good operating characteristics can be obtained.

[Effects of the Invention] As described above, in the semiconductor device according to the present invention, an insulating film with fewer traps is formed, and an insulating film in which traps are less likely to occur. For example, in EPROM, E2PROM, etc., it suppresses the drop in the threshold voltage and effectively improves the write and erase operation characteristics, and in the case of configuring MOS transistors, the threshold level is It is something that becomes stabilized. Such an insulating film can be easily and effectively formed by nitriding treatment by rapid heating using, for example, a halogen lamp, an arc lamp, or the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional structure of one memory element portion of an EPROM, which is an example of a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2J sequentially explain the manufacturing process of the semiconductor device. FIG. 3 is a diagram showing the flow of the insulating film formation process in the above manufacturing process, FIG. 4 is a configuration diagram illustrating an example of a processing apparatus used in the above insulating film forming process, and FIG. 5 is a curve diagram showing the results of Auger analysis of the above-mentioned insulating film part, and Figure 6 shows the gate voltage ■ in relation to the rapid nitriding time.
FIG. 7 is a diagram showing the relationship between g and the amount of electron injection, and FIG. 7 is a diagram showing a cross-sectional structure of an N-channel MOS transistor according to another embodiment of the present invention. 11... Silicon substrate, 14.16.18,... Insulating layer, 141.161.181... Silicon oxide film,
142.143.162.163.182.183...
・Night O oxide layer, 15... Floating gate, 17... Control gate, 35.37.3
9... Gate oxide film, 351.352.371.37
2.391.392... Nitro oxide layer, 36
．． 38...first and second polysilicon layers. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 A Figure 2 B Figure 2 C Second diagram Figure 2 E Figure 2 F Figure 2 G Figure 2 H '39 Figure 2 1 Fig. 2 J Fig. 3 ζ; Fig. 4 Fig. 5

Claims (4)

[Claims] (1) In a semiconductor device in which an electrode layer is laminated on a semiconductor substrate with an insulating layer formed of an oxide film interposed therebetween,
A semiconductor device characterized in that the insulating layer has a three-layer structure in which nitroxide layers are formed on both sides. (2) The electrode layer is composed of a floating gate electrode and a control gate electrode that constitute a nonvolatile memory, and the electrode layer is formed between the semiconductor substrate and the floating gate electrode, and between the floating electrode and the control gate electrode, respectively. 2. The semiconductor device according to claim 1, wherein an insulating layer having a three-layer structure is interposed. (3) The semiconductor device according to claim 1, wherein the electrode layer constitutes a short channel MOS transistor, and the electrode layer is surrounded by the insulating layer having the three-layer structure. . (4) forming an oxide film layer on the surface of the semiconductor substrate;
The semiconductor substrate on which the oxide layer has been formed is set in a nitrogen-based reactive gas atmosphere, and the semiconductor substrate is rapidly heated to form a nitroxide layer on each side of the oxide film layer to form a three-layer insulating layer. and forming an electrode layer on the insulating layer of the three-layer structure, the electrode layer being etched into a predetermined pattern shape and further covered with an oxide film layer. 1. A method of manufacturing a semiconductor device, characterized in that the oxide film layer has a three-layer structure with nitroxide layers formed on both sides by rapid heating.