JPH01134625A - Micro-program controller - Google Patents

Abstract

PURPOSE:To decrease the number of the steps of a micro-program, to eliminate a micro-instruction between sub-routines and to speed up a processing by calling plural sub-routines with one micro-instruction. CONSTITUTION:A micro-program, which is the aggregate of a micro-instruction, is stored into the control memory CS1 of a micro-program controller and an instruction selected by a selector 2 is stored temporarily into a register CSR 3. The output of the CSR 3 is decoded by a control memory control circuit CSC 4 and distributed to respective types of a control part. Either of the output selected by a selector 10 and the output of a hardware generating address HWC or an adder 6 is held by an address register 7. Either of the outputs of a branching control circuit BRC 5 or a selector 8 is held at a register CCA 9, an address control circuit 12 gives the control address carried out next, the output of the circuit 12 is temporarily held by a coincidence address register 13 and the coincidence of the contents of the register 13 and the selector 8 is obtained by a coincidence circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device that allows a plurality of subroutines to be called with one microinstruction.

(Prior Art) Conventionally, this type of microprogram control device has been able to call only one subroutine with one microinstruction.

(Problems to be Solved by the Invention) The conventional microprogram control device described above can only call one subroutine with one microinstruction, so when multiple subroutines are sequentially called and executed, The same number of steps as the number of microinstructions are required. As described above, the conventional microprogram control device has a problem in that it is not possible to call a plurality of subroutines with one microinstruction.

(Means for Solving the Problems) In order to solve the above-mentioned conventional problems, the microprogram control device provided by the present invention uses a microinstruction that instructs to call n subroutines in succession using one microinstruction. means for storing, and when the microinstruction is executed, an address next to the address of the microinstruction and the start address of each subroutine from the nth subroutine to the second subroutine are sequentially stored in an address stack. storage means; means for registering the start address of the first subroutine after the storage by the storage means; and the second to nth addresses stored in the address stack after the execution of the first subroutine is finished; and means for sequentially fetching and executing the first addresses of the subroutines up to and including a means for registering the next address of the address of the microinstruction stored in the address stack after finishing the execution of the n-th subroutine. Features.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a microprogram control device according to an embodiment of the present invention.

In the figure, 1 is C3 (control memory), 2 is selector, and 3 is C3
R14 is a control storage control circuit (C3C), 5 is a branch control circuit (BRC), 6 is an adder, 7 is CIA, 8 is a selector, 9 is OCA, 10 is a selector, 11 is an address stack (CAX), 12 is Address control circuit (C3AC),
Reference numeral 13 indicates a coincidence address register (CEA), and 14 indicates a coincidence circuit.

A microprogram, which is a collection of microinstructions, is stored in the C81. C3R3 is a register that temporarily holds the microinstruction selected by selector 2 and output from C8I.

C3C4 decodes the output of C3R3 and distributes control signals to each control section. CIA7 is an address register that holds either the output of selector 10, a hardware generated address (given by HW C), or the output of adder 6, and OCA9 holds the output of selector 8 or the output of BCR5. This is an address register that holds one of these. The C3AC12 controls giving the CS address of the next microinstruction to be executed. C.E.
A13 temporarily holds the output of the selector 10 and performs 1. - number circuit 14 matches the contents of CEA 13 with the contents of selector 8.

FIG. 2 is a configuration diagram of an information processing system to which the microprogram control device of this embodiment is applied.

This information processing system includes a main memory device fi (MEM) 20
The microprogram control device of this embodiment includes two central processing units (CPUs) 22, two channel control devices (IOPs) 23, and a bus 21 that connects them. include.

FIG. 3 is a block diagram showing the configuration of the CPU 22 in FIG. 2.

The CPU 22 includes a main memory access control unit (MBU) 30, an arithmetic control unit <EXU) 31, and a prefetch control unit (PFU) 3.
2 and a microprogram control unit (C3U) 33, and the microprogram control device of this embodiment includes a C3U3
This falls under 3.

The MBU 30 has a cache memory that stores only important programs for the purpose of realizing high-speed processing, and controls access to this cache memory and the MEM 20. The EXU 31 has an arithmetic circuit and a soft visible register, and performs arithmetic control. The PFU 32 performs prefetch control of instructions and operands.

Next, the operation of this embodiment will be explained.

When the initial setting of the system is completed, the CPU 22 executes the first program. First, the first machine instruction of this program is fetched from the MEM 20 via the bus 21 according to the specified instruction counter. This is a process activated by the PFU 32 to access the MBU 30. The MBU 30 checks whether or not there is a cache hit, and if there is a miss, accesses the MEM 20 to bring the data block by block to the cache, store it there, and send it to the PFU 32. The PFU 32 decodes the first machine instruction sent from the MBU 30, generates the CS address of the microinstruction for executing this II machine instruction, and
Send to 33. The CS address sent to the C3U33 is set in the CIA 7 via the selector 10.

The output of CIA7 is selected by selector 8 and given to C8I under the control of C3AC12.

The output of C3I is set to C8R3 via selector 2. The output of C3R3 is decoded by C5C4, and the QFJJ microprogram step of the a machine instruction is executed.

FIG. 4(a) is a flowchart showing an example of a microprogram sequence in a conventional microprogram control device, and FIG. 4(b) is a flowchart showing an example of a microprogram sequence in the microprogram control device of this embodiment. . Figure 5 (a) and (b)
are time charts showing the operations of FIGS. 4(a) and 4(b), respectively.

For example, in FIG. 4(a), when subroutines B and C are successively called from microprogram A to execute a certain machine instruction, the conventional microprogram control device executes microinstruction ^0゜A1. It is necessary to execute A2, which is a microinstruction that calls B from , and after executing B, execute A3, which is a microinstruction that calls C. The time chart in this case is as shown in FIG. 5(a). 82. B, ^3. C1^4. A
5, and the machine command ends after completing the above flow.

In the same case, the microprogram control device of this embodiment can call subroutines B and C by simply executing step 82, as shown in FIG. 4(b). The time chart in this case is as shown in FIG. 5(b).
, AI, 82 (A2-1. A2-2>.

B, C, 84. It becomes A5, and there is no need to execute 83.

This is achieved by storing the address of A4 and the start address of C in CAXll and then jumping to the start address of subroutine B.

In other words, when A1 is executed, FPtJ32 performs prefetch control of A2, and since A2 is a microinstruction that calls B and C, control to store the return addresses of A4 and C in CA It will be done. This storage instruction is performed by C3AC12, and A
The address of A2 is obtained by adding 1 to the address of A2 by the adder 6, and the address of the selector 10. CIA7. Selector 8. Adder 6. Selector 8. The data is stored in CAXll through the selector 10. Further, the address of A2 output from the selector 8 to the adder 6 is also output to C81 at the same time, and the address of A2 is output from the selector 8 to the adder 6.
The start addresses of B and C are obtained from the contents of 82 read from 82, passed through selector 2, and held in C3R3. The start address of B is given to the selector 10 by ARGI,
The start address of C is given to the selector 8 by ARGO.

BRC5 receives the instruction from C3C4, and if there is no branch, the lower 2 of the next CS address (output of selector 8)
In the case of a 2 w a y branch, the lower 2 bits of the next CS address and 1 bit indicating the branch decision result are
In the case of a 4-way branch, two bits indicating the branch determination result are output to the selector 2 as a select signal to control the branch.

CB A 13 is used as a matching address holding register when calling another routine that is not a subroutine. That is, before borrowing other routines, CEA13
A microinstruction is executed to set a matching address to CE A, which causes the start address of the borrow routine (given by ARGI) to be selected by selector 10, and CE A
It is set to 13. Then CA X the return address.
Set it to 11 and then jump to the borrow routine.

When a microinstruction with the same address as the address held in CEA 13 is read by the borrow routine and a match is detected by the minus number circuit 14, the return address stacked in CAXll is selected by the selector 8 and the original routine continues. is executed.

(Effects of the Invention) As described above, the present invention has the advantage that the number of steps in a microprogram can be reduced by calling a plurality of subroutines with one microphone instruction.

Further, since microinstructions are not required between subroutines, the number of dynamic steps is reduced, and processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a microprogram control device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of an information processing system to which the microprogram control device of this embodiment is applied.
Figure 3 is a block diagram showing the configuration of the CPU in Figure 2;
FIG. 4(a) is a flowchart showing an example of a microprogram sequence in a conventional microprogram control device, FIG. Figure (a) is a time chart showing the operation of Figure 4 (a), Figure 5 (b) is a time chart showing the operation of Figure 4 (b).
) is a time chart showing the operation. 1... Control memory (C8), 2... Selector, 3...
・C3R14...Control memory control circuit (C3C), 5.
... Branch control circuit (BRC), 6... Adder, 7...
・CIA, 8...Selector, 9...CCA, 10・
...Selector, 11...Address stack (CAX)
, 12...address control circuit (C3AC), 13...
- Coincidence address register (CEA), 14... Coincidence circuit, 20... Main memory (MEM), 22... Central processing unit (CPU), 23... Channel control device (I
OP), 21... Bus, 30... Main memory access control unit (MBU), 31... Arithmetic control unit (EXU), 3
2... Prefetch control unit (PFU), 33... Microprogram control unit (C3U).

Claims (1)

[Claims] means for storing a microinstruction for instructing to call n subroutines in succession with one microinstruction; storage means for sequentially storing the start address of each subroutine up to the 1st subroutine in an address stack; After finishing the execution, the start addresses of the second to nth subroutines stored in the address stack are sequentially retrieved and executed, and after finishing the execution of the nth subroutine, the first addresses of the second to nth subroutines stored in the address stack are stored in the address stack. A microprogram control device comprising means for jumping to an address next to the address of the microinstruction.