JPH01134545A - Speed-up circuit for transfer of block data - Google Patents

Abstract

PURPOSE:To simplify the structure of a data buffer and to realize the high-speed transfer of data by using a pipeline register as a data buffer and in place of a main memory. CONSTITUTION:A pipeline register 43 stores data into a main memory via a signal line 45 by an access received from a processor via a signal line 44. These stored data are transferred to the processor via a signal line 46 and processed there. The address of the data stored in the register 43 is held by an address latch 48. A valid bit register 50 holds a valid bit showing that the register 43 is valid. The contents 52 of the latch 48 are sent to a comparator 53 in response to a request 51 received from the processor. The comparator 53 receives the contents 54 of the address given to the main memory from the processor and compares both signals 52 and 53 with each other. Based on this comparison result 60 and a valid bit 58, the access requests are given to the main memory and the register 43.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed digital data transfer circuit suitable for high-speed access to a main memory device.

[Conventional technology]

FIG. 4 is a block diagram of this type of conventional high-speed circuit. □ As shown in the figure, the conventional high-speed circuit uses memory as a data buffer for storing data read from the main memory.

In the figure, a memory 11 stores data stored in a main storage device (not shown) via a signal line 13, which is accessed via a signal line 12 from a processor (not shown). The data stored in this memo 'Jll is transferred to a processor (not shown) via the signal line 14 and processed. The address of the data stored in this memory 11 is held in an address latch 16.

Further, the data in the main memory held in the address latch 16 matches the data stored in the memory 11, and therefore a valid bit indicating that the memory 11 is valid is held in the valid bit register 18. . The contents 20 of the address latch 16 are sent to a comparison circuit 21 in response to a request 22 from a processor (not shown), and the comparison circuit 21 manually reads the contents 23 of an address accessed from a processor (not shown) to a main storage device (not shown). death,
Compare both signals. Then, the access control circuit 25
An access request 27 to a main storage device (not shown) from a processor (not shown) is input, and the content 29 of the valid bit register 18 and the comparison result 30 of the comparison circuit 21 are input manually. Then, based on these, an access request 32 is output to the main storage device (not shown), and an access request 35 to the memory 11 is further output to the selector 33.

The access control circuit 25 also controls the lower two bits 3 of the main memory access address from the processor (not shown).
7 is input and used to select the target word in memory 11. Here, the selector 33 selects the address to be stored in the memory 11 word by word based on the control signal 40 from the address counter 39, and sends the access request 41 to the memory 11.
Output to.

[Problem 3 to be Solved by the Invention The conventional high-speed circuit described above uses memory as a data buffer, but has the following drawbacks. That is, when storing a plurality of words read from the main memory into the memory, an address is given to each word using an address counter and a selector. Therefore, there is a problem that the circuit becomes complicated and the number of parts increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed block data transfer circuit that can sufficiently speed up access to a main memory device, have a simple circuit configuration, and reduce the number of components.

[Means for solving problems]

The block data transfer high-speed circuit of the present invention includes a main memory device that can transfer multiple words of data with one access, and a main memory device that is connected to this main memory device and that reads and processes block data from this main memory device. In an information processing device having a processor for a specific purpose, the information processing device is composed of vertically connected registers, each register is composed of a pipeline register that can be read from the processor, and the data read from the main memory is readable from the processor. A data buffer to store, an address latch that holds the address of the data stored in this data buffer in the main storage device, and the data in the main storage device held in this address latch and the data stored in the data buffer. match, and therefore, whether the valid bit register that holds a valid bit indicating that the data buffer is valid, the contents held in the address latch, and the contents of the address accessed from the main memory from the processor match. Based on the access request from the processor to the main memory, the content of the valid bit in the valid bit register, and the comparison result of the comparison circuit, an access request to the main memory or access to the data buffer is made. and an access control circuit that outputs requests.

Therefore, when the block data transfer speed-up circuit according to the present invention is used as a data buffer, the access time is sufficiently short compared to accessing the main memory, and each word is read and transferred from the main memory. Since a pipeline register is used that does not require giving an address, the data buffer can be simplified and data transfer can be speeded up.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of a block data transfer speeding up circuit according to the present invention. Unlike the conventional case, this embodiment uses a pipeline register as a data buffer.

In the figure, a pipeline register 43 stores data stored in a main storage device (not shown) via a signal line 45 by access from a processor (not shown) via a signal line 44 . Here, it is assumed that the main memory device can transfer four words in one access. The data stored in this pipeline register 43 is transferred to a processor (not shown) via a signal line 46 and processed.

The address of the data stored in the pipeline register 43 is held in the address latch 48.

Furthermore, the data in the main memory (not shown) held in the address latch 48 matches the data stored in the pipeline register 43, and therefore the valid bit indicating that the pipeline register 43 is valid is set as a valid bit. It is held in register 50. Address latch 4 above
The content 52 of 8 is a request 51 from a processor (not shown).
is sent to the comparator circuit 53 according to the comparator circuit 53.
3 inputs the content 54 of the address accessed from the processor to the main memory and compares both signals 52 and 53. Then, the access control circuit 56 inputs an access request 57 from the processor to the main memory, and further inputs the contents 58 of the valid bit register 50 and the comparison circuit 53.
The comparison result of 60 is manually generated. Then, based on these, an access request 61 is output to the main storage device, and an access request 62 is further output to the pipeline register 43.

The access control circuit 56 also controls the lower two bits 6 of the main memory access address from the processor (not shown).
3 is input and used to select the target word in the pipeline register 43.

Next, details of the pipeline register 43 will be explained.

FIG. 2 is a block diagram showing details of the pipeline register 43 of FIG. 1.

The 4-word data transferred by accessing the main memory (not shown) once is stored in registers 65, 66, 6.
One word each is stored in 7.6.8. The data selector 70 selects one register from among the four registers 65, 66, 67, and 68 in response to a selection signal sent from the access control circuit 56 via the signal line 62, and transmits its contents to the signal line 46. Output to.

FIG. 3 is a diagram showing a situation in which data sent when the main storage device (not shown) is accessed is stored in these registers 65, 66, 67, and 68.

That is, when the main memory (not shown) is accessed, four consecutive words of data 71, 72, 73 are sent via the signal line 45.
．． 74, is sent to registers 65, 66, 67, and 78.

The first data 71 is stored in the register 65 via registers 68, 67, and 66. The second data 72 is sent to register 66 via registers 68 and 67, and the third data 73 is sent to register 67 via register 68.
The final data 74 is stored in register 68.

Next, the operation will be explained.

There are two types of operations in this embodiment for reading out the main memory from the processor.

The first case is when the read request address from the processor matches the contents of the address latch 48 and the valid bit register 50 is set. At this time, the access control circuit 56 uses the lower two bits of the access address on the signal line 63 to select one of the registers 65 to 68 in the pipeline register 43 via the signal line 62, and sends it to the processor (not shown). request data transfer. In response, the pipeline register 43 transfers the target data to a processor (not shown) via the signal line 46.

The second case is when the access request address from the processor and the contents of address latch 45 do not match, or when valid bit register 50 is reset. At this time, the access control circuit 56 issues a request to transfer 4-word data to the main storage device (not shown) via the signal line 45.

At this time, an access address to the main memory (not shown) is given via the signal line 44.

Data read from the main memory (not shown) is stored in the pipeline register 43, as shown in FIG. At the same time as storing in this pipeline register 43,
One word requested by a processor (not shown) is passed from pipeline register 43 to the processor via signal line 46.

Then, the address latch 48 is updated to the part of the current access address excluding the lower two bits, and the valid bit register 50 is set.

〔Effect of the invention〕

As explained above, the present invention provides a pipeline register which requires a sufficiently short access time compared to the main memory, and which eliminates the need to give each address when consecutively transferring multiple words when reading the main memory. The data buffer used, address latch, comparison circuit, control circuit,
By using a simple circuit consisting of registers, it is possible to reduce the number of parts while maintaining the same performance compared to the conventional circuit that uses memory as a data buffer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the block data transfer speeding up circuit according to the present invention, FIG. 2 is a block diagram showing details of the pipeline register used as a data buffer in FIG. 1, and FIG. 5 is a diagram showing a situation when four words of data are stored in each configuration register from a storage device to a pipeline register. FIG. 4 is a diagram showing a conventional block data transfer speed-up circuit. 43...Pipeline register, 48...
...Address latch, 50...Valid bit register, 53...
- Comparison circuit, 56...Access control circuit, 65-68...Register, 70...Data selector. Applicant: NEC Corporation Representative

Claims (1)

[Scope of Claims] An information processing device comprising a main memory device that can transfer multiple words of data with a single access, and a processor connected to the main memory device that reads and processes block data from the main memory device. , a data buffer for storing data read from the main memory, which is composed of pipeline registers each register being readable by the processor, and storing data in the data buffer; The data buffer is valid when the data stored in the data buffer matches the address latch that holds the address of the data stored in the main memory, the data in the main memory held in this address latch, and the data stored in the data buffer. a valid bit register that holds a valid bit indicating that there is a valid bit; a comparison circuit that determines whether the content held in the address latch matches the content of the address accessed from the main memory from the processor; and an access control circuit that outputs an access request to a main memory device or a data buffer based on the content of the valid bit of the valid bit register and the comparison result of the comparison circuit. block data transfer acceleration circuit.