JPH01134536A - Multi-processor system and its test method - Google Patents

Abstract

PURPOSE:To load the test programs into all processors with high efficiency by connecting a test ROM to a main processor only and loading the data on the main processor to other processors. CONSTITUTION:For a main processor board 1 connected with a test board 11, an instruction of a test ROM 16 is given to a processor 12 together with the test programs of all processors are stored in a DRAM 15 at application of a power supply. Other processors fetch the instructions of a boot ROM via a system bus 4. Such a program is set into the boot ROM so that the processors except a main processor are kept waiting until the test programs are loaded into their own local memories. As a result, the test programs are automatically loaded into all processors.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system used in numerical control devices and the like.

(Prior Art) A typical numerical control device uses a plurality of microprocessors to simultaneously execute a large amount of software to control the operation of a robot or machine tool at high speed and reliably.

In the multiprocessor systems used in these numerical control devices, in order to ensure that the control operations are performed reliably,
For example, each part of the hardware is inspected when the power is turned on. Various kinds of test software have been developed in the past, and these test software can be used, for example, to connect individual processors to their dedicated RA via a system bus.
It will be loaded into M.

FIG. 2 is a block diagram showing an example of a multiprocessor system.

The three processors 1 to 3 are each built into an independent processor board (#1 to #3) and connected to a system bus 4, and the system bus 4 also includes a mass storage 5 that can be accessed in common from each processor. , shared resource board 6 are connected. The shared resource port 6 includes a serial port, parallel port, shared memory, etc., as well as a boot ROM 61. A bootstrap routine read from the boot ROM 61 stores the first block of the program loaded into each processor at startup. specify.

That is, at the same time as the power is turned on, all processors access the boot ROMal via the system bus 4, and the cell 1st program specified by this accesses the boot ROMal.
and the system program are read from the mass storage 5 and loading is executed. Once the predetermined data and programs are loaded, this boot RoM6
1 is separated and each processor board (#1 to #
3) Operate according to the program in local memory.

Therefore, when executing a test program for testing the hardware of such a multiprocessor system, it is necessary to load test software into the mass storage 5 in advance in place of the system software.

(Problem to be Solved by the Invention) However, the above shared resource port 6 cannot be accessed from the external storage means.
The conventional method of loading a test program via a serial port, etc., and then loading the system software again after the test was completed was extremely time-consuming and inefficient. Therefore,
A method of loading a test program by replacing the boot ROM 61 with a test ROM for testing has also been considered. However, even with this method, it is still necessary to remove the board from the apparatus main body and replace the ROM, and it is still not possible to perform the test with sufficient efficiency.

The present invention has been made in view of the above points, and is a system in which a predetermined routine is written from a boot ROM etc. via a system bus when power is turned on, and a test ROM is written in a local bus of one processor. The aim is to provide a multiprocessor system in which test programs can be automatically loaded to all processors once they are connected.

(Means for Solving the Problems) According to the present invention, in a multiprocessor system in which a plurality of processors having a common memory area and a dedicated memory area share a boot loader, a boot loader is provided on a board of a specific processor. A connector means for connecting the processor to a read-only memory, and a prohibition means for prohibiting access from the common memory area until the contents of the read-only memory are stored in a dedicated memory area of each processor. However, it is possible to provide a multiprocessor system characterized in that the storage contents of the read-only memory connected to the connector means are loaded into all the processors at a predetermined timing.

(Function) In the multiprocessor system of the present invention, a read-only memory storing a test program is connected by the connector means of the main processor, and data of the main processor is loaded into each processor via the system bus after power is turned on. Can be done.゛(Example) Hereinafter, one example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a plurality of processor boards (#1
FIG. 3 is a block diagram showing a configuration when a test board 11 is connected to a main processor board including one specific processor 1 among the processors 1 to #3) through a connector 10.

A DRAM 15 constituting a dedicated memory area is connected to the data bus 13 and address bus 14 of the main processor 12, and a test ROM 16 storing a test program is connected through the connector 10. There are decoders 17 and 18 on the processor 12 side and the test board 11 side, respectively, and the decoder 17 is an AND gate G.
1 to the system path access control unit 19, and outputs the select command for the original address (Q(1(1(1)(1~QFFFFF>), and also selects the DRAM 15 via AND gate G2 and ORGATE) G5. A clock is also supplied to the flip-flop 20. Another command output (100000 to IFFFFF) is supplied to the select terminal of the DRAM 15 via an OR gate Gi5.

The data bus 13 is connected to the data buffer 2! via D
It is connected to the RAM 15 and to a data buffer 22 having a bidirectional buffer function between the system bus 4 and the system bus 4 . Further, address data from the processor 12 is used to specify an address in the DRAM 15 via an address bus 14, and this address bus 14 connects the connector 10 and the address buffer 23.

The flip-flop 20 has its set output terminal connected to the decoder 18 of the test board 11 and the AND gate G2 via the connector 10, and its reset output terminal connected to the AND gate G1. Then, after power is turned on according to an address command specified from the address bus 14, the main processor 12 attempts to execute an instruction from address 0, but the flip-flop 20, which was cleared from the beginning, is reset by the decoder 17, and the gates Gl and G2 are reset. Therefore, the DRAM 15 is not selected, and instructions from the boot ROM connected via the system bus 4 are fetched. However, the above flip-flop 20
Since the two data buffers 21 and 22 of the data bus 13 are controlled to be in a read-inhibited state via the decoder 18, when the test board 11 is connected, there is no connection between the system bus 4 and the main processor 12. It is disabled, and instructions from the test ROM 16 are given to the main processor 12 instead of instructions from the boot ROM.

In this case, the main processor 12 is stored in the test ROM 16.
By writing test programs for other processors as well as test programs for the main processor 12, these programs can be copied from the main processor 12 to the DRAM of the processor board itself and other processor boards. D.R.
In AM15, when the power is turned on, the flip-flop 20 is reset and the decoder 17 outputs (1oooooo to IFF).
FFF), and this address space is used for copying from the test ROM 16 to the DRAM 15. Copying to the DRAMs of other processor boards can be done by various means, but here the main processor 12 has a hardware configuration that allows direct access to those DRAMs.

On the other hand, processors other than the main processor 12 fetch instructions from the boot ROM in the same way as when starting a normal system. At this time, after first executing the initialization and self-test processes in the boot ROM, a loop waits for the system software completion flag from the main processor 121. This flag is located in the DRAM on each processor board, and is located in the DRAM on each processor board.
2 sets this flag when the loading of the test program to the other processors is completed. When this flag is set, the processor sets each flip-flop 20 and assigns the DRAM to the original address (oooooooo~0FFFFFF), and then to the predetermined address, that is, the start address of the system software. Jump. When the flip-flop 20 is set, the test ROM 16 on the test board connected to the main processor 12 is inhibited, so the main processor 12 also
It will now operate according to the data in it.

In this way, in a multiprocessor system configured to share a boot ROM, a connector 1o is provided on a specific processor board, the test board 11 storing a test program is connected thereto, and the instruction that the processor 12 attempts to fetch is connected to the connector 1o. If configured to forcibly remove the
is supplied with a test program to the main processor 12.
Since the test ROM is not connected to the other processors, the program in the ROM will be executed. Therefore, if you write a program in the ROM to identify a specific processor as the main processor and, if not, wait until it is loaded into its own local memory, you can test it on a specific processor board. Once the board is connected, the test program is automatically loaded onto all processors in the system.

As above, this invention has been described in some detail with respect to its most preferred embodiment, but the description of the preferred embodiment does not include variations in detailed parts of the configuration or contrary to the spirit of the invention as described in the claims. It is clear that various modifications or combinations thereof may be made.

(Effects of the Invention) As explained above, according to the present invention, the test ROM
By simply connecting the test board to the main processor board containing the test board, test programs can be loaded to all processors, providing a multiprocessor system that can shorten testing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a main processor board and a test board according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional system. 11... Test board, 12... Main processor, 15... DRAM, 16... Test ROM. 21.22...Data buffer. Patent applicant FANUC Corporation

Claims (2)

[Claims] (1) In a multiprocessor system in which a plurality of processors having a common memory area and a dedicated memory area share a boot loader, a connector means provided on the board of a specific processor and connecting the processor to a read-only memory; storage in the read-only memory connected to the connector means, and prohibiting means for prohibiting access from the common memory area until the storage contents of the read-only memory are stored in a memory area dedicated to each of the processors; A multiprocessor system characterized in that content is loaded to all processors at a predetermined timing. (2) In a test method for a multiprocessor system in which multiple processors having a common memory area and a dedicated memory area share a bootloader, a test board storing a test program is connected to a specific processor board, and the A method for testing a multiprocessor system, comprising transferring a test program from a processor to its dedicated memory area and the common memory area, and then loading the test program into each processor and executing the test program.