JPH01133351A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH01133351A JPH01133351A JP62292415A JP29241587A JPH01133351A JP H01133351 A JPH01133351 A JP H01133351A JP 62292415 A JP62292415 A JP 62292415A JP 29241587 A JP29241587 A JP 29241587A JP H01133351 A JPH01133351 A JP H01133351A
- Authority
- JP
- Japan
- Prior art keywords
- resist pattern
- pattern
- region
- forming
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 239000007943 implant Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 abstract description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052796 boron Inorganic materials 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
くイ）産業上の利用分野
本発明はイオン注入法による抵抗素子を組み込んだ半導
体集積回路のＮＰＮ トランジスタのｈ□制御を容易な
らしめた製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION B) Field of Industrial Application The present invention relates to a manufacturing method that facilitates h□ control of an NPN transistor in a semiconductor integrated circuit incorporating a resistance element formed by ion implantation.
（ロ）従来の技術
バイポーラ型ＩＣは、コレクタとなる半導体層表面にベ
ース・エミッタを２重拡散して形成した縦型のＮＰＮ
トランジスタを主体として構成されている。その為、前
記ＮＰＮ トランジスタを製造するベース及びエミッタ
拡散工程は必要不可欠の工程であり、コレクタ直列抵抗
を低減する為の高濃度埋込層形成工程やエピタキシャル
層成長工程、各素子を接合分離する為の分離領域形成工
程や電気的接続の為の電極形成工程等と並んでバイポー
ラ型ＩＣを製造するのに欠かせない工程（基本工程）で
ある。(b) Conventional technology A bipolar IC is a vertical NPN formed by doubly diffusing a base and an emitter on the surface of a semiconductor layer that serves as a collector.
It is mainly composed of transistors. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation process for each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.
一方、回路的な要求から他の素子、例えばＰＮＰトラン
ジスタ、抵抗、容量、ツェナーダイオード等を同一基板
上に組み込みたい要求がある。この場合、工程の簡素化
という点から可能な限り前記基本工程を流用した方が好
ましいことは言うまでもない。しかしながら、前記ベー
ス及びエミッタ拡散工程はＮＰＮトランジスタの特性を
最重要視して諸条件が設定される為、前記基本工程だけ
では集積化が困難な場合が多い。そこで、基本的なＮＰ
Ｎ トランジスタの形成を目的とせず、他の素子を組み
込む為もしくは他素子の特性を向上することを］］的と
して新規な工程を追加することがある。例えば前記エミ
ッタ拡散によるカソード領域とでツェナーダイオードの
ツェナー電圧を制御するアノード領域を形成する為のＰ
＋拡散工程、ベース領域とは比抵抗が異る抵抗領域を形
成する為のＲ拡散工程やインプラ抵抗形成工程、ＭＯＳ
型よりも大きな容量が得られる窒化膜容量を形成する為
の窒化膜形成工程、ＮＰＮ）−ランジスタのコレクタ直
列抵抗を更に低減する為のコレクタ低抵抗領域形成工程
等がそれであり、全てバイポーラＩＣの用途や目的及び
コスト的な面から検討して追加するか否かが決定される
工程（オブション工程）である。On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration being given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, basic NP
A new process may be added not for the purpose of forming a transistor, but for incorporating other elements or improving the characteristics of other elements. For example, P is used to form an anode region that controls the Zener voltage of the Zener diode together with the cathode region formed by the emitter diffusion.
+ Diffusion process, R diffusion process to form a resistance region with a different resistivity from the base region, implant resistance formation process, MOS
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN) transistors. This is a process (optional process) in which it is decided whether or not to add it after considering the use, purpose, and cost aspects.
上記オブション工程を利用して形成したインプラ抵抗を
第３図に示す。同図において、（１）はＰ型半導体基板
、（２）はＮ＋型埋込層、（３）はＮ型エピタキシＡ・
ル層、（４）はＰ１型分離領域、（５）はアイランド、
（６）はＮＰＮ）ランジスタのＰ型ベース領域、（７）
及び（８）はＮＰＮ トランジスタのＮ＋型エミッタ領
域及びコレクトコンタクト領域、（９）はイオン注入に
よる抵抗領域、（１０）はベース拡散で形成したコンタ
クト領域である。FIG. 3 shows an implant resistor formed using the above optional process. In the same figure, (1) is a P-type semiconductor substrate, (2) is an N+ type buried layer, and (3) is an N-type epitaxy A.
(4) is a P1 type isolation region, (5) is an island,
(6) is the P-type base region of the NPN) transistor, (7)
and (8) are the N+ type emitter region and collector contact region of the NPN transistor, (9) is a resistance region formed by ion implantation, and (10) is a contact region formed by base diffusion.
尚、第３図のインプラ抵抗は例えば特公昭５７−２１８
２号公報に記載されている。Incidentally, the implant resistance shown in Fig. 3 is, for example, manufactured by Japanese Patent Publication Publication No. 57-218.
It is described in Publication No. 2.
（ハ）発明が解決しようとする問題点
しかしながら、近年のＩＣの多種・多様化の要望からイ
オン注入法を利用した高精度のインプラ抵抗を不純物濃
度を異ならしめて複数種類組み込みたい要求がある。こ
の様な場合、単純に工程を追加すれば可能ではあるが、
工程の複雑化及びコスト高という欠点がある。その為、
本願は高精度に制御した複数種類のインプラ抵抗を効率
良く組み込むことを目的とする。(c) Problems to be Solved by the Invention However, due to the recent demand for greater variety and diversification of ICs, there is a demand for incorporating multiple types of high-precision implant resistors using ion implantation with different impurity concentrations. In such a case, it is possible to simply add a process, but
This method has the drawbacks of complicating the process and increasing costs. For that reason,
The purpose of this application is to efficiently incorporate multiple types of implant resistances that are controlled with high precision.
（ニ）問題点を解決するための手段
本発明は衛士した欠点に鑑みてなされ、ポジ型レジスト
による１回目のレジストパターン（２７）を形成し、こ
のパターン（２７）を利用してボロン（Ｂ）の１回目の
イオン注入を行う工程と、ネガ型レジストによって前記
１回目のイオン注入で形成した領域の不純物濃度を変え
たくない領域を覆う２回［１のレジストパターン（３０
）を形成し、前回の工程で形成した酸化膜（２６）パタ
ーン又は１回目レジストパターン（３０）をマスクとし
て再度ホロン（Ｂ）の２回目のイオン注入を行う工程と
を具備することを特徴とする。(d) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and a first resist pattern (27) is formed using a positive resist, and this pattern (27) is used to form boron (B). ), and then two steps [1 resist pattern (30
) and performing a second ion implantation of holons (B) using the oxide film (26) pattern formed in the previous step or the first resist pattern (30) as a mask. do.
（ホ）作用
本発明によれば、１回目のレジストパターン（２７）に
よって高精度に形成したパターンをそのまま利用して２
回目のイオン注入を行うので、２回目のレジストパター
ン（３０）は１回目程高い精度で制御せずに済む。また
、２つの領域を形成するのに酸化膜パターン（２６）の
形成が１回で済む。(E) Function According to the present invention, the pattern formed with high precision by the first resist pattern (27) is used as it is to create a second resist pattern.
Since the second ion implantation is performed, the resist pattern (30) for the second time does not need to be controlled as precisely as the first time. Further, the oxide film pattern (26) only needs to be formed once to form two regions.
（へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
先４′第１図Ａに示す如く、Ｐ型のシリコン半導体基板
（２１）の表面にアンチモン（Ｓｂ）又はヒ素（Ａｓ）
等のＮ型不純物を―択的にドープしてＮ＋型埋込層（２
２）を形成し、基板（２１）全面に厚さ５〜１０μのＮ
型のエピタキシャル層（２３）を積層する。4' As shown in FIG. 1A, antimony (Sb) or arsenic (As) is added to the surface of the P-type silicon semiconductor substrate (21).
An N+ type buried layer (2
2) with a thickness of 5 to 10 μm on the entire surface of the substrate (21).
A mold epitaxial layer (23) is deposited.
次に第１図Ｂに示す如く、エピタキシャル層（２３）表
面からボロン（Ｂ）を選択的に拡散することによって、
埋込Ｍ！Ｊ（２２）を夫々取囲むようにエピタキシャル
層（２３）を貫通するＰ＋型の分離領域（２４）を形成
する。分離領域（２４）で囲まれたエピタキシャル層（
２３）が夫々の回路素子を形成する為のアイランド（２
５）となる。Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the epitaxial layer (23),
Embedded M! P+ type isolation regions (24) penetrating the epitaxial layer (23) are formed so as to surround each J (22). an epitaxial layer (
23) is an island (2) for forming each circuit element.
5).
次に第１図Ｃに示す如く、熱酸化を行ってエピタキシャ
ル層（２３）全面に酸化膜（２６）を形成し、スピンオ
ン塗布によって酸化膜（２６）上にポジ型のフォトレジ
ストを塗布、続いて反射型投影方式又は縮小投影露光方
式等の１μｍ以下の重ね合せ精度を有する露光装置を用
いて所望形状のパターンを焼付け、現像することによっ
て１回目のレジストパターン（２７〉を形成する。Next, as shown in FIG. 1C, an oxide film (26) is formed on the entire surface of the epitaxial layer (23) by thermal oxidation, and a positive photoresist is applied on the oxide film (26) by spin-on coating. A first resist pattern (27>) is formed by printing and developing a pattern of a desired shape using an exposure apparatus having an overlay accuracy of 1 μm or less, such as a reflection projection method or a reduction projection exposure method.
次に第１図りに示す如く、リアクティブ・イオン・エツ
チング等のドライエツチングで酸化膜（２６）を異方性
エツチングすることにより１回目レジストパターン（２
７〉に対応する酸化膜（２６）パターンを形成し、その
後１回目レジストパターン（２７）を除去又は残存させ
た状態でエピタキシャルＪｆｆｌ（２３）表面から１回
目のボロン（Ｂ）のイオン注入を行うことにより２つの
アイランド（２５）表面に同一の不純物濃度を有する第
１と第２の抵抗領域（２８）（２９）を夫々形成する。Next, as shown in the first diagram, the oxide film (26) is anisotropically etched by dry etching such as reactive ion etching to form the first resist pattern (26).
An oxide film (26) pattern corresponding to 7> is formed, and then the first boron (B) ion implantation is performed from the epitaxial Jffl (23) surface with the first resist pattern (27) removed or left. As a result, first and second resistance regions (28) and (29) having the same impurity concentration are formed on the surfaces of the two islands (25), respectively.
尚、電位的な問題が無ければ２つの抵抗領域（２８）（
２９）は同一アイランド（２５）に設けても良い。１回
目のイオン注入は比抵抗を高くする側の第１の抵抗領域
（２８）の不純物濃度に合わせてボロン（Ｂ）のドーズ
量と加速電圧が選択される。In addition, if there is no potential problem, two resistance regions (28) (
29) may be provided on the same island (25). In the first ion implantation, the boron (B) dose and acceleration voltage are selected in accordance with the impurity concentration of the first resistance region (28) on the side where the specific resistance is to be increased.
次に第１図Ｅに示す如く、１回目のレジストパターン（
２７）を除去又は残した状態でその表面にネガ型のフォ
トレジスト膜をスピンオン塗布し、今度はプロキシミテ
ィ露光方式や投影露光方式によって所望形状のパターン
を焼付け、現像することによって２回目のレジストパタ
ーン（３０）を形成する。２回目のレジストパターン（
３０）は１回目のレジストパターン（２７）より遮へい
部分を小さくし、酸化膜（２６）パターンの開孔部分を
前回のパターンより拡大して開孔する。その為、２回目
のレジストパターン（３０）の開孔部分には前の工程で
イオン注入した領域の表面と１回目レジストパターン（
２７）又は酸化膜（２６）パターンのエツジ部分が露出
することになる。２回目のレジストパターン（３０）の
一部分（３１）は抵抗領域（２８）の両端を除く表面を
直接覆い、第１の抵抗領域（２８）のコンタクト部分だ
けを露出する。Next, as shown in FIG. 1E, the first resist pattern (
27) is removed or left, a negative photoresist film is applied on the surface by spin-on coating, and a pattern of a desired shape is printed using a proximity exposure method or a projection exposure method, and developed to create a second resist pattern. (30) is formed. Second resist pattern (
In step 30), the shielding part is made smaller than that of the first resist pattern (27), and the opening part of the oxide film (26) pattern is made larger than that of the previous pattern. Therefore, the opening part of the second resist pattern (30) has the surface of the region where ions were implanted in the previous step and the first resist pattern (30).
27) or the edge portion of the oxide film (26) pattern is exposed. A portion (31) of the second resist pattern (30) directly covers the surface of the resistive region (28) except for both ends, exposing only the contact portion of the first resistive region (28).
そして、エピタキシャル層（２３）表面から前回の工程
で形成した１回目レジストパターン（２７）又は酸化膜
（２６）パターンを再びマスクとして２回目のボロン（
Ｂ）のイオン注入を行う。第２の抵抗領域（２９）には
ボロン（Ｂ）が重ねてイオン注入されるので、この段階
で比抵抗を低くする側即ち第２の抵抗領域（２９）の不
純物濃度を決めるように２回目イオン注入のドーズ量が
設定される。また、第２の抵抗領域（２９）の不純物濃
度は後で形成する電極とのオーミックコンタクトが行え
るような不純物濃度とし、それ由第１の抵抗領域（２８
）の両端にも２回目のイオン注入をすることによって第
２の抵抗領域（２９）と同一不純物濃度を有する電極配
設用のコンタクト領域（３２）を形成する。コンタクト
領域（３２）の間の第１の抵抗領域（２８）は２回目レ
ジストパターン（３０）の一部分（３１）で覆われてい
るので２回目のボロン（Ｂ）がイオン注入されない。そ
の為、２回目レジストパターン（３０）の一部分（３１
）で覆われた部分の不純物濃度は１回目のイオン注入に
より設定された不純物濃度がそのまま残り、この領域が
インプラ抵抗の抵抗値を実質的に決定する領域となる。Then, using the first resist pattern (27) or oxide film (26) pattern formed in the previous step from the surface of the epitaxial layer (23) as a mask, a second boron (
Perform B) ion implantation. Since boron (B) is ion-implanted into the second resistance region (29) in a layered manner, the impurity concentration on the side that lowers the specific resistance, that is, the second resistance region (29), is determined at this stage. The ion implantation dose is set. Further, the impurity concentration of the second resistance region (29) is set to such an impurity concentration that ohmic contact can be made with the electrode to be formed later, and therefore the impurity concentration of the first resistance region (28
) to form a contact region (32) for electrode arrangement having the same impurity concentration as the second resistance region (29). The first resistive region (28) between the contact regions (32) is covered with a portion (31) of the second resist pattern (30), so that the second boron (B) ion implantation is not performed. Therefore, part of the second resist pattern (30) (31
The impurity concentration in the portion covered by ) remains the same as the impurity concentration set by the first ion implantation, and this region becomes a region that substantially determines the resistance value of the implant resistor.
また、不純物濃度が低いので前述したコンタクト領域（
３２）が必要となる。その後１回目及び２回目レジスト
パターン（２７）（３０）を除去し、全体をＣＶＤの酸
化膜（２６）で覆うと共にコンタクト領域（３２）を一
定深さにまで拡散する熱処理を行う。尚、２回目のイオ
ン注入の段階で１回目レジストパターン（２７）の有無
は問わないが、残しておいた場合にはエツチング工程が
１回省ける利点と酸化膜（２６）の膜厚を薄くできる利
点を有する。In addition, since the impurity concentration is low, the contact region (
32) is required. Thereafter, the first and second resist patterns (27) and (30) are removed, the entire structure is covered with a CVD oxide film (26), and a heat treatment is performed to diffuse the contact region (32) to a certain depth. It does not matter whether or not the first resist pattern (27) is present at the stage of the second ion implantation, but if it is left, the advantage is that one etching step can be omitted and the thickness of the oxide film (26) can be made thinner. has advantages.
次に第１図Ｆに示す如く、第１と第２の抵抗領域（２８
）（２９）の両端に酸化膜（２６）を開孔したコンタク
トホールを設け、エピタキシャル層（２３）全面に周知
の蒸着又はスパッタ技術によりアルミニウム層を形成し
た後、このアルミニウム層をパターニングすることによ
って所定の電極（３３）を配設する。Next, as shown in FIG. 1F, the first and second resistance regions (28
) (29) by providing contact holes in the oxide film (26), forming an aluminum layer on the entire surface of the epitaxial layer (23) by well-known vapor deposition or sputtering techniques, and then patterning this aluminum layer. Predetermined electrodes (33) are arranged.
上述した製法により形成した第１の抵抗領域（２８）の
平面図は第２図の如くになる。同図において、（２５）
はアイランド、（２８）は第１の抵抗領域、（３２）は
コンタクト領域、（３４）はコンタクトホール、そして
（３１）は第１図りにおける２回目レジストパターン（
３０）の一部分の形状を示す。第１の抵抗領域（２８）
の線幅とコンタクト領域（３２）の大きさは第１図Ｃの
１回目のレジストパターン（２７）によって既に決定さ
れるので、このインプラ抵抗の抵抗値はフンタクト領域
（３２）間の距離では無く２回目レジストパターン（３
０）の一部分（３１）が覆う抵抗領域（２８）の長さで
決まる。その為本実施例ではコンタクト孔（３４）の大
きさを第１の抵抗領域（２８）の線幅以下とすることに
よってフンタクト領域（３２）の不純物濃度の変化によ
る抵抗値の変動が最も少い構造とし、この構造とするこ
とにより２回目レジストパターン（３０）の一部分（３
１〉の側端部（３５）をコンタクト領域（３２）の側端
部（３６）と一致させである。その為、インプラ抵抗の
占有面積を最も小さくでき、マスクずれによる抵抗値の
変動を僅ど無視できると共にポジ型レジストとＲＩＨに
よる高精度の１回目のフォトエツチングの精度を損うこ
とが無い。A plan view of the first resistance region (28) formed by the above manufacturing method is shown in FIG. In the same figure, (25)
(28) is the first resistor region, (32) is the contact region, (34) is the contact hole, and (31) is the second resist pattern in the first drawing (
30) shows the shape of a part of it. First resistance region (28)
Since the line width and the size of the contact area (32) are already determined by the first resist pattern (27) in Figure 1C, the resistance value of this implant resistance is not the distance between the contact areas (32). Second resist pattern (3
0) is determined by the length of the resistive region (28) covered by the portion (31). Therefore, in this embodiment, by making the size of the contact hole (34) smaller than the line width of the first resistance region (28), the variation in resistance value due to the change in impurity concentration of the contact region (32) is minimized. With this structure, a part (3) of the second resist pattern (30) is formed.
1> side edge (35) is aligned with the side edge (36) of the contact area (32). Therefore, the area occupied by the implant resistor can be minimized, and variations in resistance value due to mask displacement can be slightly ignored, and the precision of the first photoetching, which is highly accurate using a positive resist and RIH, is not impaired.
衛士した本願の製造方法によれば、１回目のフォトエツ
チングを高精度に行って第１と第２の抵抗領域（２８）
（２９）を形成した後、１回目のレジストパターン（２
７）をそのまま利用して第２の抵抗領域（２９）だけに
２回目のイオン注入を行うので、高精度の比抵抗の異る
複数種類のインプラ抵抗を簡単に組み込むことができる
。しかも高精度のフォトエツチングを２回繰り返さず済
むので、工程の簡略化とコストダウンが図れる。According to the manufacturing method of the present invention, the first photo-etching is performed with high precision to form the first and second resistance regions (28).
After forming (29), the first resist pattern (2
Since the second ion implantation is performed only in the second resistance region (29) using 7) as is, it is possible to easily incorporate a plurality of types of implant resistances having different specific resistances with high precision. Moreover, since high-precision photoetching does not need to be repeated twice, the process can be simplified and costs can be reduced.
（ト）発明の詳細
な説明した如く、本発明によれば比抵抗の異る複数種類
の高精度のインプラ抵抗をＩＣ内に共存させることがで
きる利点を有する。また、高精度のフォトエツチングを
２回繰り返さず番ζ済むので、工程の簡略化とコストダ
ウンが図れる利点を有する。(g) As described in detail, the present invention has the advantage that a plurality of types of high-precision implantable resistors having different specific resistances can coexist in an IC. Further, since high-precision photoetching can be completed without repeating it twice, there is an advantage that the process can be simplified and costs can be reduced.
第１図Ａ乃至第１図Ｆは本発明を説明する為の断面図、
第２図は本発明を説明する為の平面図、第３図は従来例
を説明する為の断面図である。
（２１）はＰ型半導体基板、 （２７）は１回目のレジ
ストパターン、 （２８）は第１の抵抗領域、 （２９
）は第２の抵抗領域、（３０）は２回目のレジストパタ
ーンである。1A to 1F are cross-sectional views for explaining the present invention,
FIG. 2 is a plan view for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example. (21) is a P-type semiconductor substrate, (27) is the first resist pattern, (28) is the first resistance region, (29)
) is the second resistance region, and (30) is the second resist pattern.
Claims (1)
込層を形成する工程、 前記基板の上に逆導電型のエピタキシャル層を形成する
工程、 前記エピタキシャル層を分離して複数個のアイランドを
形成する工程、 前記エピタキシャル層の表面の絶縁膜上にフォトレジス
ト膜を形成し、前記アイランド上に開孔部を有する１回
目のレジストパターンを形成する工程、 前記１回目レジストパターンを利用して前記絶縁膜を選
択的にドライエッチングすることにより絶縁膜パターン
を形成し、この絶縁膜パターン又は前記１回目レジスト
パターンをマスクとして一導電型の不、鈍物をイオン注
入することにより同一不純物濃度を有する少なくとも２
個以上の抵抗領域を形成する工程、 全面に再度フォトレジスト膜を形成し、一方の抵抗領域
の表面にはその全部又は主要部分を覆うようなレジスト
パターンを他方の抵抗領域の表面にはその全部を露出し
且つパターンのエッジ部分をも露出するような開孔部を
拡大したレジストパターンを有する２回目のレジストパ
ターンを形成し、このパターンを利用して選択的に一導
電型の不純物をイオン注入することにより前記一方の抵
抗領域の不純物濃度より前記他の抵抗領域の不純物を増
大させ、比抵抗の異なる２種類の抵抗領域を形成する工
程とを具備することを特徴とする半導体集積回路の製造
方法。(1) A step of forming a buried layer of an opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, and a step of separating the epitaxial layer into a plurality of layers. forming a photoresist film on the insulating film on the surface of the epitaxial layer, and forming a first resist pattern having an opening on the island; using the first resist pattern; Then, the insulating film is selectively dry-etched to form an insulating film pattern, and using this insulating film pattern or the first resist pattern as a mask, an impurity of one conductivity type is ion-implanted to form the same impurity. concentration of at least 2
The process of forming more than one resistor region, a photoresist film is formed again on the entire surface, and a resist pattern covering the entire or main part of one resistor region is placed on the surface of the other resistor region. A second resist pattern is formed with an enlarged opening to expose the edges of the pattern, and this pattern is used to selectively ion-implant impurities of one conductivity type. manufacturing a semiconductor integrated circuit, comprising the step of: increasing the impurity concentration in the other resistance region by increasing the impurity concentration in the one resistance region, thereby forming two types of resistance regions having different specific resistances; Method.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292415A JPH01133351A (en) | 1987-11-19 | 1987-11-19 | Manufacture of semiconductor integrated circuit |
| US07/271,748 US4898837A (en) | 1987-11-19 | 1988-11-15 | Method of fabricating a semiconductor integrated circuit |
| KR1019880015291A KR920004174B1 (en) | 1987-11-19 | 1988-11-19 | Method of fabricating a semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292415A JPH01133351A (en) | 1987-11-19 | 1987-11-19 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133351A true JPH01133351A (en) | 1989-05-25 |
Family
ID=17781491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62292415A Pending JPH01133351A (en) | 1987-11-19 | 1987-11-19 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133351A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773963A (en) * | 1981-08-31 | 1982-05-08 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
| JPS6199364A (en) * | 1984-10-22 | 1986-05-17 | Fujitsu Ltd | Forming method of resistance layer |
-
1987
- 1987-11-19 JP JP62292415A patent/JPH01133351A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773963A (en) * | 1981-08-31 | 1982-05-08 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
| JPS6199364A (en) * | 1984-10-22 | 1986-05-17 | Fujitsu Ltd | Forming method of resistance layer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3865649A (en) | Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate | |
| GB1573496A (en) | Bipolar transistors and method of manufacturing the same | |
| JPH0787194B2 (en) | Lateral bipolar transistor and method of forming lateral p-n-p transistor, bipolar transistor and lateral p-n-p transistor | |
| US5913114A (en) | Method of manufacturing a semiconductor device | |
| US3933528A (en) | Process for fabricating integrated circuits utilizing ion implantation | |
| US4898837A (en) | Method of fabricating a semiconductor integrated circuit | |
| JPH0536901A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01133351A (en) | Manufacture of semiconductor integrated circuit | |
| JPH02352A (en) | Manufacture of semiconductor integrated circuit | |
| JP3298476B2 (en) | Method for manufacturing MOS transistor | |
| JPH01133343A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01171263A (en) | Manufacture of semiconductor integrated circuit | |
| JPS6123665B2 (en) | ||
| JP3013385B2 (en) | Method for manufacturing semiconductor device | |
| JPH01133352A (en) | Manufacture of semiconductor integrated circuit | |
| KR920004174B1 (en) | Method of fabricating a semiconductor integrated circuit | |
| JPH02135770A (en) | Semiconductor integrated circuit | |
| JPH01133354A (en) | Semiconductor integrated circuit and manufacture thereof | |
| JPH01161749A (en) | Manufacture of semiconductor integrated circuit | |
| JPS6241422B2 (en) | ||
| JPH01175252A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01161764A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01133350A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01130553A (en) | Manufacture of semiconductor integrated circuit | |
| JPH02137258A (en) | Manufacture of semiconductor integrated circuit device |