JPH01132133A - Cell arrangement system - Google Patents

Abstract

PURPOSE:To make it possible to decide an effective cell arrangement for a circuit having regularity to a certain extent by repeating the exchange of the cells or movement thereof within a band-shaped region in a horizontal or vertical direction, thereby improving the evaluation function value of the arrangement. CONSTITUTION:In the cell arrangement of a standard cell type or gate array type LSI block or chip, there are provided means 5 for limiting the region where specified one or plural signal lines and cells to be connected to the signal line or lines are arranged within a band-shaped region horizontal or vertical direction, and means 6 which repeats exchange of the cells or the movement thereof within the region limited by the means 5 so as to improve the evaluation function value of the arrangement. Moreover, for instance, there are provided means 3, 4 which specify the signal lines passing in a horizontal direction and the signal lines passing in a vertical direction of the signals of a given circuit by evaluating the signal names or the state of connections of the circuit, and means 7 which performs the movement and exchange in the region in which the cell arrangement positions are limited.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a cell placement system for a standard cell type or gate array type LSI, and in particular to a cell placement system for a circuit that can specify the area where signal lines in the negative part are placed. It's about systems.

(Prior Art) Conventionally, when determining the cell arrangement of a standard cell type or gate array type LSI.

Either the circuits inside the LSI are handled as a whole, or the cell set of the circuit is divided into several subsets by evaluating the hierarchical structure of the circuit or the number of nets between subsets of the circuit. A cell placement method is used in which the areas in which each subset is placed are then limited and fixed, and the placement is improved within each area.

In addition, when designing the LSI layout manually, it is necessary to decide in advance the direction and area in which specified signal lines 1 such as data buses and control signals are to be arranged before arranging functional cells. Therefore, an LLR layout with good performance and small area is obtained. When obtaining the layout of one block or the entire chip of an LSI through automatic design, the conventional cell placement methods such as the standard cell and gate array are used for circuits with a high degree of disorder, resulting in a layout with almost no disorder. Some circuits, such as ROM, RAM, PLA data buses, etc., are designed manually or by automated design systems that have the ability to arrange cells in an array. however,
The latter method cannot be used for designing general circuits because the functions and configurations of circuits that can be handled are limited.

(Problem to be solved by the invention) The general method of finding a cell arrangement with a small area and good performance for a given circuit in a block or chip configured using a standard cell or gate array method is extremely difficult. Moreover, conventional methods cannot handle highly disordered circuits.

Although good cell placement can be obtained, there is a drawback that good cell placement cannot be obtained for circuits with some degree of regularity.

The present invention applies to circuits that have some degree of regularity.

The purpose is to perform cell placement that can determine effective cell placement.

(Means for Solving the Problems) The present invention arranges one or more specified signal lines and cells connecting the signal lines in a cell arrangement of a standard cell type or gate array type LSI. It is characterized by comprising means for limiting an area within a horizontal or vertical strip-shaped area, and means for repeatedly exchanging or moving cells within the area limited by the means to improve the evaluation function value of placement. The present invention provides a cell placement system that does the following. Furthermore, in addition to this, among the signal lines of a given circuit, the signal lines to be passed in the horizontal direction and the signal lines to be passed in the vertical direction are determined by evaluating the signal line name or the connection state of the circuit. The present invention provides a cell placement system characterized by comprising means for specifying and means for moving and exchanging in area units that limit cell placement positions.

(Function) According to the present invention, the layout design of a block or chip of a standard cell type or gate array type LSI can be more efficiently and effectively performed, and the CAD
This also facilitates cell placement processing.

(Example) Hereinafter, an example of the present invention will be described based on the accompanying drawings.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, 1 is a circuit input means, 2 is a parameter setting means, 3 is a horizontal direction signal line specifying means, 4 is a vertical direction signal line specifying means, 5 is a placement area limiting means, 6 is a limited area moving means, 7 is a cell placement means.

FIG. 2 shows an example of the layout and wiring of a standard cell type LSI. In Figure 2, 8 is a standard cell,
9 is a cell row, and 10 is a wiring. As shown in this figure, in the standard cell type LSI, cells 8 are arranged in several rows, and wiring is performed using the wiring area (channel) between the cell rows 9. In this embodiment, the cell placement area is arranged in the third row. Model it using the grid graph shown in the figure. In FIG. 3, 11 is a cell column, 12 is a grid point, 13 is an arrangement area, 14 is a horizontal arrangement area, and 15 is a vertical allocation area.

Each cell is placed at one of the grid points 12. Furthermore, when limiting the area in which cells are to be placed in advance, a placeable area 13 is defined for the cells.

In the following sentence, the grid point 12 in the i-th column and j-th row is (11j)
The placeable area 13 is the lower left grid point CQ.

b) and the upper right grid point (re t), [(11,b)
.

(r, t)]. Here, the horizontally arrangable area 14 is (Q, r), and the vertically arrangable area is (by
t). They respectively mean a set of cell columns and a set of cell rows that can be arranged.

The cell placement procedure in this example is shown below.

First, the circuit input means 1 is used to input circuit connection data, and the primary parameter setting means 2 inputs the number of cell rows to construct a lattice graph.

The placement area 13 of each cell is ((1,1)=(c,r
)), from here on, C indicates the maximum number of cell columns, and r indicates the maximum number of cell rows. Next, the horizontal direction signal line specifying means 3 determines the signal line hi (i=1.2.
..., specify A). This can be done by inputting the signal line name that has been given in advance by the data file, or if the same data is not given, specifying the signal line name connected to the data bus buffer as a horizontal signal line. The zero-order arrangement area limiting means 5 selects the signal line hi (i ==
1.2. ..., the vertical arrangement area 15 of the cell connected to A) is (r* i/A+1.r* i/A+2)
shall be.

Similar processing is performed in the vertical direction. First, the vertical signal line specifying means 4 determines the signal line v to be wired in the vertical direction.
Specification characterized by j (j = 1 t 2 t..., B) is performed by the signal line name described in advance in the data file, or by pattern recognition of the control line. Using the placement area limiting means 5, the horizontal placement possible area 14 of the cell connected to the signal line vj (j = 1.2..., B) specified by the vertical signal line specifying means 4 is determined. C umbrella j / B + 1, c 11 j / B
+2).

Next, the limited area moving means 6 moves or exchanges the horizontally arrangable area 14 or the vertically arrangable area 15 in units of areas that limit the arrangement position, as shown in FIGS. 4 and 5. I will explain using. FIG. 4 shows how the horizontally movable area 14 moves.

In FIG. 4, 16 is a cell, 17 is a net between cells,
18 indicates a movement operation, and the horizontally arrangable area 14 is
There is a one-to-one correspondence with the signal line specified by the vertical signal line specifying means 4. The moving operation 18 allows the horizontal arrangement area 14 of all cells connected to the signal line specified by the vertical signal line specifying means 4 to be horizontally arranged in correspondence with another specified signal line. Area 14
It means a series of operations in which all given cells of all the horizontally arrangable areas 14 sandwiched between the moved distances are shifted one area at a time in the opposite direction to the movement. FIG. 5 shows how two horizontally arrangable areas 14 are exchanged.

The exchange operation 19 means a series of operations for exchanging the horizontally arrangable areas 14 of all cells connected to each of the two specified signal lines. The limited area moving means 6 repeats the moving operation 18 and the replacing operation until no improvement can be obtained so as to minimize the total wiring length. Finally, in the cell placement means 7, the replacement operation is repeated for the purpose of minimizing the total wiring length within the area where each cell can be placed, using the cell 8 as a unit, until no improvement can be obtained.

In addition, in the limited area moving means 6 and cell placement means 7 of this embodiment, the number of cuts, the degree of wiring congestion, etc. can be easily implemented as an evaluation function instead of the total wiring length. Further, although a creep-friendly method has been shown as a method for obtaining improvement, a method of repeating movement exchange may also be used even if no improvement is necessarily achieved, such as a simulated annealing method.

(Effects of the Invention) The present invention has conventionally been difficult to optimize in standard cell method or gate array method LSI. For circuits with some degree of regularity.

A more regular cell arrangement can be efficiently obtained,
This is particularly effective when automating placement.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram of an embodiment of the present invention, Fig. 2 is a layout diagram of a standard cell type LSI, Fig. 3 is an explanatory diagram of a lattice graph, and Figs. 4 and 5 are movement of the placement area. , is an explanatory diagram of exchange. 1... Circuit input means, 2... Parameter setting means, 3... Horizontal direction signal line specifying means, 4... Vertical direction signal line specifying means, 5... Arrangement area limiting means, 6.
...Limited area moving means, 7...Cell arrangement means, 9.
... Cell row, 11... Cell column, 12... Grid point. 13... Arrangeable area, 14... Horizontal arrangement possible area, 15... Vertical arrangement possible area, 16...
Cell, 18...Move operation, 19...Exchange operation. Patent Applicant Matsushita Electric Industrial Co., Ltd. -, -7, Ige Gosu 1 Figure 1 Figure 2 Column Published Figure 4 + 6 Figure 5

Claims (3)

[Claims] (1) In cell placement of a standard cell type or gate array type LSI block or chip, the area where one or more specified signal lines and the cells connected to the signal lines are placed is formed into a horizontal or vertical strip. What is claimed is: 1. A cell placement system comprising: means for limiting the cell placement within a region; and means for repeatedly exchanging or moving cells within the region limited by the means to improve a placement evaluation function value. (2) Among the signal lines of a given circuit, the signal lines to be passed in the horizontal direction and the signal lines to be passed in the vertical direction are specified by evaluating the signal line name or the connection state of the circuit. The cell arrangement system according to claim 1, further comprising means. (3) Claim No.
The cell placement system described in item 1) or (2).