JPH01132129U - - Google Patents
Info
- Publication number
- JPH01132129U JPH01132129U JP2680388U JP2680388U JPH01132129U JP H01132129 U JPH01132129 U JP H01132129U JP 2680388 U JP2680388 U JP 2680388U JP 2680388 U JP2680388 U JP 2680388U JP H01132129 U JPH01132129 U JP H01132129U
- Authority
- JP
- Japan
- Prior art keywords
- switching element
- mos fet
- resistor
- load
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の第１の実施例を示す回路構成
図、第２図は本考案の第２の実施例を示す回路構
成図、第３図は従来例を示す回路図である。
１……直流電源、２……ＮチヤネルＭＯＳ Ｆ
ＥＴ、３……負荷、４，５，６，７，８，９，１
０……抵抗、１１，１２，１３，１４……トラン
ジスタ、１５……定電圧ダイオード、１６，１７
，２１，２２……ダイオード、１８，１９……コ
ンデンサ、２０……ＰＵＴ。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. 1...DC power supply, 2...N channel MOS F
ET, 3...Load, 4, 5, 6, 7, 8, 9, 1
0... Resistor, 11, 12, 13, 14... Transistor, 15... Constant voltage diode, 16, 17
, 21, 22...diode, 18, 19... capacitor, 20...PUT.
Claims (1)
で構成される閉回路において、前記直流電源の正
端子を第１のスイツチング素子、抵抗及びダイオ
ードを介して前記ＭＯＳ ＦＥＴのゲート端子に
接続し、前記ダイオードの他端を定電圧ダイオー
ド、コンデンサの充電回路及びＰＵＴのゲート端
子に接続し、前記直流電源に並列に接続した抵抗
とコンデンサの接続点を前記ＰＵＴのアノード端
子及び第２のスイツチング素子と接続し、前記充
電回路の他端と第３のスイツチング素子を接続し
、前記第１のスイツチング素子を開閉するように
制御信号を与えて負荷への電源を供給及び停止す
ることを特徴とするＭＯＳ ＦＥＴ制御回路。 In a closed circuit composed of a DC power supply, an N-channel MOS FET, and a load, the positive terminal of the DC power supply is connected to the gate terminal of the MOS FET via a first switching element, a resistor, and a diode, and the The other end is connected to a constant voltage diode, a capacitor charging circuit, and a gate terminal of a PUT, and a connection point between a resistor and a capacitor connected in parallel to the DC power source is connected to an anode terminal of the PUT and a second switching element; A MOS FET control circuit, characterized in that the other end of the charging circuit is connected to a third switching element, and a control signal is given to open and close the first switching element to supply and stop power to the load. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2680388U JP2519521Y2 (en) | 1988-02-29 | 1988-02-29 | MOSFET control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2680388U JP2519521Y2 (en) | 1988-02-29 | 1988-02-29 | MOSFET control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01132129U true JPH01132129U (en) | 1989-09-07 |
| JP2519521Y2 JP2519521Y2 (en) | 1996-12-04 |
Family
ID=31248758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2680388U Expired - Lifetime JP2519521Y2 (en) | 1988-02-29 | 1988-02-29 | MOSFET control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2519521Y2 (en) |
-
1988
- 1988-02-29 JP JP2680388U patent/JP2519521Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2519521Y2 (en) | 1996-12-04 |