JPH01131919A - Terminal equipment - Google Patents

Abstract

PURPOSE:To output natural sound with simple constitution by only writing received voice data on a voice memory until silence is detected, and demodulating voice data stored in the voice memory at a constant cycle to a part equivalent to the silence at a time when the silence of the received voice data is detected. CONSTITUTION:The received data is written on the voice memory 12 sequentially by controlling a readout address generation circuit 19 so as to update a readout address at every receipt of the voice data. A silence detection circuit 16 holds a write address by an address latch 17 at a time when the silence is detected in the received voice data. A comparator 20 operates a clock generation circuit 18 and a demodulation circuit 13 only while no coincidence between the output of the address latch 17 and that of the readout address generation circuit 19 is obtained, and demodulates the voice data outputted sequentially from the sound memory 12 according to the readout address outputted from the readout address generation circuit 19 at the demodulation circuit 13, then outputs it as voice. In such a way, it is possible to constitute a terminal equipment to demodulate the natural voice quite easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a terminal device that receives audio data and outputs it as audio.

2. Description of the Related Art A conventional terminal device of this type has a configuration as shown in FIG. Audio data is input from an input terminal 1, demodulated into an audio signal by a demodulation circuit 2, and output from a speaker 3. In such a conventional terminal device, if audio data is not regularly and continuously input to the input terminal 1, the audio output from the speaker 3 may become unnatural.

This will be explained using FIG. 4. Figure 4e) is the original audio signal. As shown in Figure 4(b), the audio signal is converted into a digital signal, divided into sets of digital signals of a certain length, and stored, and when reading audio data from the database, these sets are treated as one unit. It will be read and transmitted to the terminal via the transmission network. Therefore, due to fluctuations in database access time, fluctuations in delay time on a transmission network such as a packet network, etc., the audio data input to the input terminal 1 becomes discontinuous as shown in Figure 4(C), and the audio demodulation circuit The signal demodulated in step 2 is also discontinuous as shown in FIG. 4(d), and unnatural sound is output from the speaker 3. Note that the audio signals in FIGS. 4(8-) and 4(d) show simple waveforms for the sake of explanation.

Problems to be Solved by the Invention As mentioned above, in conventional terminal devices, due to fluctuations in database access time or delay time on the transmission network,
The voice data input to the terminal device is irregular or discontinuous, and the voice demodulated by the terminal device is also discontinuous and unnatural.

The present invention has been made in view of this point, and an object of the present invention is to provide a terminal device that has a simple configuration and is capable of outputting natural sound.

Means for Solving the Problems In order to solve the above problems, the present invention provides an audio memory for storing audio data, a silence detection circuit for detecting silence in the audio data, and a write address for generating a write address for the audio data. A generator, an address latch that holds the write address at the time when silence is detected by the silence detection circuit, a clock generation circuit that generates a clock that defines the cycle for reading audio data stored in the audio memory, and a read address. It includes a read address generation circuit that generates a read address, a demodulation circuit that demodulates audio data into audio, and a comparator that compares the output of the address latch with the output of the read address generation circuit. The received audio data is sequentially written into the audio memory by controlling the read address generation circuit to update the writing read address in the audio memory, and the silence detection circuit writes the write address at the time when silence is detected in the received audio data as the address. By holding the comparator in the latch, the comparator operates the clock generation circuit and the demodulation circuit only when the output of the address latch and the output of the read address generation circuit do not match. The audio data that is sequentially output is demodulated by a demodulation circuit and output as audio.

Effect of the present invention With the above-described configuration, the received audio data is only written into the audio memory until silence is detected, and at the time when silence is detected in the received audio data, the audio stored in the audio memory is written. Since the data is demodulated at a constant cycle up to the portion corresponding to silence, even if the reception interval of audio data is irregular, demodulation is performed regularly, so natural audio without discontinuities can be output. Can be done.

Embodiment FIG. 1 is a block diagram showing an embodiment of a terminal device of the present invention. In FIG. 1, 1o is an input terminal for audio data, 11 is an input terminal for receiving timing of audio data, and 12 is an input terminal for audio data reception timing.
13 is an audio memory that stores audio data; 13 is a demodulation circuit that demodulates the audio data into audio and outputs it to the output terminal 14; 16;
1 is a write address generation circuit that generates a write address for audio data; 16 is a silence detection circuit that detects silence in the received audio data; and 17 is a silence detection circuit that holds the write address at the time when silence is detected by the silence detection circuit 16. Address latch 18 is a clock generation circuit that generates a clock that defines the reading cycle of audio data stored in the audio memory 12;
9 is a read address generation circuit that generates a read address for audio data, and 2Q is a comparator that compares the output of the address latch 17 with the read address that is the output of the read address generation circuit 19. FIG. 2 is a waveform diagram of each part to explain this embodiment. In the figure, (&) indicates the audio data input to the input terminal 1o, and (b) indicates the reception timing input to the input terminal 11. , (0) is the write address output from the write address generation circuit 15, and (d) is the silence detection circuit 1.
6 is the signal output when silence is detected, (6) is the output of the address latch 17, (f') is the output of the comparator 2o, (g) is the output of the clock generator 18, (middle) indicates a read address output from the read address generation circuit 19. The input terminal 1o and the input terminal each receive audio data (Fig. 2(a)) and reception timing (second
(b)) is input, the audio data input to the input terminal 1o is transferred to the audio memory according to the write address (see FIG. 2(C)) output from the write address generation circuit 15. Written in 12. Further, the write address is sequentially updated according to the reception timing input to the input terminal 11. - When the silence detection circuit 16 detects silence in the audio data, it outputs the signal shown in FIG.
It is held at 7. The comparator 20 compares the output of the address latch 17 and the output of the read address generation circuit 19, and if the two are not equal, outputs a signal as shown in FIG. As shown in FIG. 2(g), the clock generating circuit 18 generates a clock that defines the read timing of the audio data and outputs it to the read address generating circuit 19, which generates the read address as shown in FIG. 2(h). The audio data that is updated sequentially is sequentially read out from the audio memory 12, demodulated by the demodulation circuit 13, and output as audio to the output terminal 14.In this read operation, the read address becomes equal to the output of the address latch. The reading operation is stopped until the silence detection circuit 16 detects silence again and the contents of the address latch 17 change. Therefore, the audio is regularly demodulated between the silent parts of the audio. It turns out.

Effects of the Invention As described above, according to the present invention, it is possible to extremely easily configure a terminal device that demodulates natural voice even when the period of received voice data is irregular, and it is extremely practical in practice. Useful.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a terminal device according to an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the operation of each part of the same, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is a block diagram of each part of the same. FIG. 3 is a waveform diagram for explaining the operation of FIG. 12...Audio memory, 13...Demodulation circuit, 15...Write address generation circuit, 16...
... Silence detection circuit, 17 ... Address latch, 18 ... Clock generation circuit, 19 ...
...Read address generation circuit, 2°...Comparator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4

Claims (1)

[Claims] An audio memory that stores audio data, a silence detection circuit that detects silence in received audio data, a write address generation circuit that generates an address to which the received audio data should be written, and the silence detection circuit that detects silence. an address latch that holds the write address at the time when the audio data is read out; a clock generator that generates a clock for sequentially reading audio data stored in the audio memory; a read address generator that generates an address from which the audio data should be read; The demodulation circuit demodulates the audio data sequentially output from the audio memory and outputs it as audio, and the comparator compares the output of the address latch with the output of the read address generator. writing the audio data to the corresponding address of the audio memory indicated by the output of the write address generator, and sequentially writing the received audio data to the audio memory by updating the write address output from the write address generator. At the same time, the write address at the time when silence is detected by the silence detection circuit is held in the address latch, and the comparator operates the clock generator and the demodulation circuit while the output of the address latch and the read address do not match. The audio data stored at the address indicated by the read address, which is the output of the read address generation circuit, is output from the audio memory to the demodulation circuit and the read address generator is updated. A terminal device characterized by outputting.