JPH01131192U - - Google Patents
Info
- Publication number
- JPH01131192U JPH01131192U JP2777588U JP2777588U JPH01131192U JP H01131192 U JPH01131192 U JP H01131192U JP 2777588 U JP2777588 U JP 2777588U JP 2777588 U JP2777588 U JP 2777588U JP H01131192 U JPH01131192 U JP H01131192U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- register
- memory
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Measurement Of Predetermined Time Intervals (AREA)
- Emergency Alarm Devices (AREA)
Description
第１図は本考案の一実施例を示すブロツク構成
図である。
１……押ボタンブロツク、２……パルスカウン
タ、３……記憶回路、４……減算デイジタルタイ
マ、５……表示ユニツト、６……ソーテイングユ
ニツト、７……シフトレジスタ、８……コンパレ
ータ回路、９……駆動回路、１０……警報ユニツ
ト、１１……セツトブロツク、１２……時刻タイ
マ、１３……レジスタ、１４……プリンタ。
FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Push button block, 2...Pulse counter, 3...Memory circuit, 4...Subtraction digital timer, 5...Display unit, 6...Sorting unit, 7...Shift register, 8...Comparator circuit , 9... Drive circuit, 10... Alarm unit, 11... Set block, 12... Time timer, 13... Register, 14... Printer.
Claims (1)
パルスカウンタと、前記パルスカウンタと接続さ
れパルス信号の値を登録記憶させる複数個の記憶
回路と、前記記憶回路の出力を入力する減算デイ
ジタルタイマと、前記記憶回路と順次接続された
ソーテイングユニツトおよびシフトレジスタを介
して出力される前記記憶回路の出力と前記減算デ
イジタルタイマの出力とを比較するコンパレータ
回路と、常時時刻がデイジタル信号でレジスタに
出力される時刻タイマと、前記コンパレータ回路
の出力により駆動回路を介して動作する警報ユニ
ツトと、前記コンパレータ回路の出力信号により
一時ホールドするレジスタと動作するプリンタと
を有することを特徴としたアラーム装置。 a pulse counter that integrates pulse signals from the push button block; a plurality of memory circuits that are connected to the pulse counter and register and store values of the pulse signals; a subtraction digital timer that inputs the output of the memory circuit; and the memory. a comparator circuit that compares the output of the storage circuit and the output of the subtraction digital timer, which are outputted via a sorting unit and a shift register connected to the circuit in sequence; and a time point at which the constant time is outputted to the register as a digital signal. An alarm device comprising: a timer; an alarm unit that operates via a drive circuit based on the output of the comparator circuit; and a printer that operates with a register that temporarily holds the alarm based on the output signal of the comparator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2777588U JPH01131192U (en) | 1988-03-02 | 1988-03-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2777588U JPH01131192U (en) | 1988-03-02 | 1988-03-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01131192U true JPH01131192U (en) | 1989-09-06 |
Family
ID=31250564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2777588U Pending JPH01131192U (en) | 1988-03-02 | 1988-03-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01131192U (en) |
-
1988
- 1988-03-02 JP JP2777588U patent/JPH01131192U/ja active Pending
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