JPH01129515A - Protecting circuit for pwm amplifier - Google Patents

Protecting circuit for pwm amplifier

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Publication number
JPH01129515A
JPH01129515A JP62287887A JP28788787A JPH01129515A JP H01129515 A JPH01129515 A JP H01129515A JP 62287887 A JP62287887 A JP 62287887A JP 28788787 A JP28788787 A JP 28788787A JP H01129515 A JPH01129515 A JP H01129515A
Authority
JP
Japan
Prior art keywords
circuit
power
signal
pwm
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62287887A
Other languages
Japanese (ja)
Inventor
Noriji Sasaki
佐々木 則治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62287887A priority Critical patent/JPH01129515A/en
Publication of JPH01129515A publication Critical patent/JPH01129515A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the breakdown of a power element by providing a control means for cutting off power source supply to a power amplifying circuit by a fact that a state that a detection voltage by a monitor means is in a prescribed value has continued for a prescribed time. CONSTITUTION:A monitor means is constituted of resistances 18-26, comparators 12, 13 and an OR gate 14. Also, a control means is constituted of a reference signal generating circuit 15, a counter 16 and a power source cutting-off circuit 17. When an 'H' level voltage is applied to an enable(EBL) terminal, the counter 16 counts a clock of a prescribed period supplied from the reference signal generating circuit 15. When an 'H' level voltage is outputted continuously from an OR gate 14, and during that time, the counter 16 has counted up to a count value which is set in advance, the counter 16 counts up, and also, generates an 'H' level signal. The power source cutting-off circuit 17 which received this signal cuts off electrifying to power elements 4-7 for forming a power amplifying circuit.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、PWM変調された信号を電流増幅するPWM
アンプを過大電流から保護するPWMアンプの保護回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a PWM modulated signal that is used for current amplification of a PWM modulated signal.
The present invention relates to a protection circuit for a PWM amplifier that protects the amplifier from excessive current.

従来の技術 第3図は本発明が適用されるP W M (P u 1
 s eWidth Modulation :パルス
幅変調)アンプの回路を示す回路図である。
Conventional technology FIG. 3 shows P W M (P u 1
FIG. 2 is a circuit diagram showing a circuit of a pulse width modulation (pulse width modulation) amplifier.

第3図において、■はアナログ入力信号を増幅するプリ
アンプ、2は三角波信号を発生ずる三角波発生回路、3
はプリアンプ1の出力信号と三角波発生回路2より出力
される三角波信号とを比較してアナログ入力信号をその
振幅に応じたPWM信号に変調するPWM回路である。
In Figure 3, ■ is a preamplifier that amplifies the analog input signal, 2 is a triangular wave generation circuit that generates a triangular wave signal, and 3
is a PWM circuit that compares the output signal of the preamplifier 1 with the triangular wave signal output from the triangular wave generating circuit 2 and modulates the analog input signal into a PWM signal according to the amplitude thereof.

PWM回路3は位相が互いに反転したPWM信号信号用
を発生し、PWM信号信号用力端子には1対のパワー素
子4及び5が接続され、PWM信号信号用力端子には1
対のパワー素子6及び7が接続され、これらパワー素子
はパワー増幅回路を形成している。1対のパワー素子は
電源Vccとアース間に直列接続され、その中間接続点
が信号の入出力点になっている。パワー素子4.5の出
力端とパワー素子6.7の出力端の各々にはインダクタ
8及び9の各々が接続され、このインダクタ8及び9の
他端間には、コンデンサ(C) 1.0と抵抗(RL)
11の並列回路が接続されている。
The PWM circuit 3 generates PWM signal signals whose phases are mutually inverted, a pair of power elements 4 and 5 are connected to the power terminal for the PWM signal signal, and a pair of power elements 4 and 5 are connected to the power terminal for the PWM signal signal.
A pair of power elements 6 and 7 are connected, and these power elements form a power amplification circuit. The pair of power elements are connected in series between a power supply Vcc and ground, and the intermediate connection point serves as a signal input/output point. Inductors 8 and 9 are connected to each of the output end of power element 4.5 and the output end of power element 6.7, and a capacitor (C) 1.0 is connected between the other ends of inductors 8 and 9. and resistance (RL)
Eleven parallel circuits are connected.

次に、以上の構成によるPWMアンプの動作を3へ−7 第4図の波形図を参照して説明する。Next, proceed to 3-7 for the operation of the PWM amplifier with the above configuration. This will be explained with reference to the waveform diagram in FIG.

第4図に示すようなアナログ入力信号がプリアンプ1に
入力されると、プリアンプ1は三角波信号との比較が可
能なレベルまで増幅して出力する。
When an analog input signal as shown in FIG. 4 is input to the preamplifier 1, the preamplifier 1 amplifies it to a level that allows comparison with a triangular wave signal and outputs it.

この増幅信号はPWM回路3によって、三角波発生回路
2より出力される三角波信号と比較され、両信号が交叉
する点の間を接続し、かつ交互にレベル変換した状態の
矩形波信号がPWM回路3からPWM信号として発生す
る。PWM信号は正極性信号Qとこれを反転させた負極
性信号Qとを同時に出力し、信号Qがパワー素子4と5
によって電流増幅され、信号Qがパワー素子6と7によ
って電流増幅される。電流増幅されだPWM信号の各々
はインダクタ8.9とコンデンサ10よす成る平滑回路
によって平滑されたのち、合成されて低抵抗の負荷抵抗
11に印加される。負荷抵抗11に供給される信号は、
平滑回路によって平滑されているためにアナログ入力信
号に相似した同一周波数のアナログ信号になっている。
This amplified signal is compared with the triangular wave signal output from the triangular wave generating circuit 2 by the PWM circuit 3, and a rectangular wave signal in a state where the points where both signals intersect is connected and the level is alternately converted is generated by the PWM circuit 3. It is generated as a PWM signal from The PWM signal simultaneously outputs a positive polarity signal Q and a negative polarity signal Q obtained by inverting the positive polarity signal Q, and the signal Q is outputted from the power elements 4 and 5.
The signal Q is current amplified by the power elements 6 and 7. Each of the current amplified PWM signals is smoothed by a smoothing circuit consisting of an inductor 8.9 and a capacitor 10, and then combined and applied to a low resistance load resistor 11. The signal supplied to the load resistor 11 is
Since it is smoothed by a smoothing circuit, it becomes an analog signal with the same frequency and similar to the analog input signal.

発明が解決しようとする問題点 しかし、以上のような従来の構成では、過大電圧が長時
間入力され、或いはPWM回路3の誤動作によってパワ
ー素子にXXH〃又はjs L /Lレベルの一定レベ
ルの電圧が長時間入力されると、パワー素子に最大定格
以上の電流が流れ、パワー素子の破壊を招く恐れがある
Problems to be Solved by the Invention However, in the conventional configuration as described above, if an excessive voltage is input for a long time, or if the PWM circuit 3 malfunctions, the voltage at a constant level of XXH or js L /L level is applied to the power element. If it is input for a long time, a current exceeding the maximum rating will flow through the power device, which may cause damage to the power device.

本発明は、前記のような従来の問題を解決するもので、
過大入力及び前段回路の誤動作等によるパワー素子の破
壊を防ぎ、PWMアンプの保護が図れるようにしたPW
Mアンプの保護回路を提供することを目的とするもので
ある。
The present invention solves the conventional problems as described above.
A PW that protects the PWM amplifier by preventing damage to the power element due to excessive input or malfunction of the preceding stage circuit.
The purpose of this invention is to provide a protection circuit for M amplifiers.

問題点を解決するだめの手段 本発明は、前記問題点を解決するだめ、アナログ入力信
号と基準になる三角波信号とを比較してパルス幅変調(
PWM)信号を生成し、パワー増幅回路を駆動するPW
M回路の出力電圧を検出するモニタ手段と、このモニタ
手段による検出電圧が一定値にある状態を所定時間継続
したことをもって前記パワー増幅回路への電源供給を遮
断する制御手段とを具備したものである。
Means for Solving the Problem In order to solve the above problem, the present invention performs pulse width modulation (pulse width modulation) by comparing an analog input signal with a reference triangular wave signal
PWM) which generates a signal and drives the power amplification circuit.
It is equipped with a monitor means for detecting the output voltage of the M circuit, and a control means for cutting off the power supply to the power amplification circuit when the voltage detected by the monitor means continues to be at a constant value for a predetermined period of time. be.

5・\−7 作用 本発明は前記構成により次のような作用を有する。5・\-7 action The present invention has the following effects due to the above configuration.

すなわち、PWMアンプに過大電圧が長時間入力され、
或いはPWM回路が誤動作してパワー素子に’ H/l
又はNL〃レベルの一定電圧が長時間入力された場合、
それがモニタ手段によって検知され、一定時間以上に及
んだ場合にパワー素子への電源供給が遮断される。した
がって、パワー素子に過大電流が流れることはなく、パ
ワー素子を破壊から保護することができる。
In other words, excessive voltage is input to the PWM amplifier for a long time,
Or the PWM circuit malfunctions and the power element becomes 'H/l.
Or, if a constant voltage at NL level is input for a long time,
This is detected by the monitoring means, and if it continues for a certain period of time or more, the power supply to the power element is cut off. Therefore, excessive current will not flow through the power device, and the power device can be protected from destruction.

実施例 以下、本発明の実施例について図面を参照しながら説明
する。第1図は本発明の一実施例におけるPWMアンプ
の保護回路のブロック図である。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a protection circuit for a PWM amplifier in an embodiment of the present invention.

本実施例においては、前記第3図のPWMアンプと同一
部分については同一符号を付してその説明を省略し、異
なる構成について説明する。本発明の特徴は、第3図に
示したPWMアンプに、モニタ手段と制御手段より成る
保護回路100を付加したことにある。
In this embodiment, the same parts as those of the PWM amplifier shown in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted, and the different configuration will be explained. A feature of the present invention is that a protection circuit 100 consisting of monitor means and control means is added to the PWM amplifier shown in FIG.

モニタ手段は、抵抗18〜26、コンパレータ12.1
3及びオアゲート14より構成される。まだ、制御手段
は、基準信号発生回路15、カウンタ16及び電源遮断
回路17より構成される。
Monitoring means include resistors 18 to 26 and comparators 12.1
3 and an or gate 14. The control means is still composed of a reference signal generation circuit 15, a counter 16, and a power cutoff circuit 17.

抵抗18.21.24は直列接続されて電源Vccとア
ース間に接続され、抵抗20及び22はPWM回路3の
Q出力端子に一端が接続されている。抵抗20の他端は
コンパレータ12の一方の入力端子に接続され、抵抗2
2の他端はコンパレータ13の一方の入力端子に接続さ
れている。コンパレータ12の他方の入力端子と抵抗1
8.21の接続点との間に抵抗19が接続され、コンパ
レータ13の他方の入力端子と抵抗21.24の接続点
との間に抵抗23が接続されている。コンパレータ12
及び13の各々の出力端子には電源Vccとの間に抵抗
25及び26が接続されている。
The resistors 18, 21, and 24 are connected in series between the power supply Vcc and the ground, and the resistors 20 and 22 have one end connected to the Q output terminal of the PWM circuit 3. The other end of the resistor 20 is connected to one input terminal of the comparator 12.
The other end of 2 is connected to one input terminal of the comparator 13. The other input terminal of comparator 12 and resistor 1
A resistor 19 is connected between the connection point of the resistor 8.21 and a resistor 23 is connected between the other input terminal of the comparator 13 and the connection point of the resistor 21.24. Comparator 12
Resistors 25 and 26 are connected between the output terminals of and 13 and the power supply Vcc.

コンパレータ12及び13の各出力はオアゲート140
2人力となり、両人力のいずれかに信号が印加されると
きにオアゲート14から出力信号が発生し、カウンタ1
6のイネーブル(EBL)端子に印加さ7・・−7 れる。
Each output of comparators 12 and 13 is connected to an OR gate 140.
When there are two human forces and a signal is applied to either of the two human forces, an output signal is generated from the OR gate 14, and the counter 1
6 is applied to the enable (EBL) terminal of 7...-7.

カウンタ16は、EBL端子に(k J(l/レベルの
信号が印加されているときにクロック (CLK)端子
に入力されるクロック信号をカウントする。クロック信
号は基準信号発生回路15より与えられる。
The counter 16 counts the clock signal input to the clock (CLK) terminal when a signal of (k J (l/level) is applied to the EBL terminal. The clock signal is provided from the reference signal generation circuit 15.

カウンタ16の出力端子Qの出力信号は電源遮断回路1
7に印加され、出力端子Qの出力信号が\\H〃のとき
にパワー素子群への電源供給がオフにされる0 次に、以上の構成の動作について第2図を参照して説明
する。なお、PWMアンプの動作は第3図で説明した通
りであるだめ、ここでの説明は省略する。
The output signal of the output terminal Q of the counter 16 is the power cutoff circuit 1
7, and when the output signal of the output terminal Q is \\H, the power supply to the power element group is turned off.Next, the operation of the above configuration will be explained with reference to Fig. 2. . Note that the operation of the PWM amplifier is the same as that described in FIG. 3, so the explanation here will be omitted.

PWMアンプに過大電圧が長時間入力され、或いはPW
M回路3が誤動作をする等により、PWM回路3の出力
Qがtt H/7レベル状態のままになったとすると、
その電圧は抵抗20を介してコンパレータ〕2に印加さ
れ、この電圧は抵抗19を介して与えられる電圧よりも
高いため、コンパレータ12の出力電圧はss Hl/
レベルになる。この\\H〃レベルを受けたオアゲート
14は\\H〃レベル電圧を出力し、これをカウンタ1
6のEBL端子へ印加する。
If excessive voltage is input to the PWM amplifier for a long time, or if the PWM
Suppose that the output Q of the PWM circuit 3 remains at the tt H/7 level due to a malfunction of the M circuit 3, etc.
The voltage is applied to the comparator] 2 via the resistor 20, and since this voltage is higher than the voltage applied via the resistor 19, the output voltage of the comparator 12 is ss Hl/
become the level. The OR gate 14 that receives this \\H level outputs a \\H level voltage, which is sent to the counter 1.
6 to the EBL terminal.

カウンタ16はEBL端子にIS Hnレベル電圧が与
えられると、基準信号発生回路15より供給される一定
周期のクロックをカウントする。オアゲート14よりt
t Hnレベル電圧が継続して出力され、その間に予め
設定したカウント値までカウンタ16がカウントした場
合、カウンタ16はカウントアツプと共にts Htt
レベル信号Sを発生する。この信号Sを受けた電源遮断
回路17はパワー増幅回路を形成するパワー素子4〜7
への通電を遮断する。
When the IS Hn level voltage is applied to the EBL terminal, the counter 16 counts the constant cycle clock supplied from the reference signal generation circuit 15. From orgate 14
If the t Hn level voltage is continuously output and the counter 16 counts up to a preset count value during that time, the counter 16 will count up and ts Htt.
A level signal S is generated. The power cutoff circuit 17 receiving this signal S is connected to the power elements 4 to 7 forming a power amplification circuit.
Cut off the power to.

まだ’I PWM回路3の出力Qがtt L l/レベ
ルになった場合、コンパレータ13は抵抗22を介して
与えられる参照電圧よりも抵抗23を介して与えられる
検出電圧の方が低くなるため、コンパレータ13は\\
H〃レベル電圧を出力する。これによって上記と同様に
オアゲート14の出力電圧が1\H〃レベルとなり、カ
ウンタ16より信号Sを発生させ、電源遮断回路17を
作動させることができる。
If the output Q of the 'I PWM circuit 3 reaches the tt L l/level, the detection voltage applied to the comparator 13 through the resistor 23 is lower than the reference voltage applied through the resistor 22. Comparator 13 is \\
Outputs H level voltage. As a result, the output voltage of the OR gate 14 reaches the 1\H level in the same manner as described above, the counter 16 generates the signal S, and the power cutoff circuit 17 can be activated.

9、/ 以上より明らかなように、PWM回路3の出力電圧をコ
ンパレータ12及び13で’ Hl/レベル及びss 
L l/レベルの状態を参照電圧と比較し、PWM回路
3の出力の継続に応じた検出信号を発生させ、更に、こ
の検出状態が一定時間以上継続したか否かをカウンタ1
6によって判定し、設定時間以上の継続に対してパワー
素子群への電流供給を断つようにしたため、過剰な電流
供給が生じるこ七によるパワー素子の破壊を防止するこ
とができる。
9. / As is clear from the above, the output voltage of the PWM circuit 3 is determined by the comparators 12 and 13 by 'Hl/level and ss
The state of the L l/level is compared with the reference voltage, a detection signal is generated according to the continuation of the output of the PWM circuit 3, and the counter 1 determines whether this detection state has continued for a certain period of time or more.
6, and the current supply to the power element group is cut off if the current supply continues longer than the set time, so it is possible to prevent the power elements from being destroyed due to excessive current supply.

発明の効果 以上述べたように本発明によれば、PWMアンプに過大
入力電圧が長時間印加され、或いはPWM回路が誤動作
をしてパワー素子に最大定格以上の過大電流が流れだ場
合でも、パワー素子への電流供給を遮断し、パワー素子
の破壊を防止し、PWMアンプを保護することができる
Effects of the Invention As described above, according to the present invention, even if an excessive input voltage is applied to the PWM amplifier for a long time, or if the PWM circuit malfunctions and an excessive current exceeding the maximum rating flows through the power element, the power can be maintained. It is possible to cut off current supply to the element, prevent damage to the power element, and protect the PWM amplifier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるPWMアンプの保護
回路のブロック図、第2図は第1図の回路の各部動作波
形図、第3図は従来例のPWMアンプの保護回路のブロ
ック図、第4図は第3図のアンプの各部動作波形図であ
る。 2 三角波発生回路、3−PWM回路、4〜7・・パワ
ー素子、8.9・・−インダクタ、10・・コンデンサ
、11.18〜26・・・抵抗、12.13・・・コン
パレータ、14・・オアゲート、15・・基準信号発生
回路、16  カウンタ。
Fig. 1 is a block diagram of a protection circuit for a PWM amplifier according to an embodiment of the present invention, Fig. 2 is a waveform diagram of each part of the circuit shown in Fig. 1, and Fig. 3 is a block diagram of a protection circuit for a conventional PWM amplifier. , FIG. 4 is an operational waveform diagram of each part of the amplifier shown in FIG. 3. 2 Triangular wave generation circuit, 3-PWM circuit, 4-7... Power element, 8.9...-Inductor, 10... Capacitor, 11.18-26... Resistor, 12.13... Comparator, 14 ...OR gate, 15..Reference signal generation circuit, 16 counter.

Claims (1)

【特許請求の範囲】[Claims] アナログ入力信号と基準になる三角波信号とを比較して
パルス幅変調(PWM)信号を生成し、パワー増幅回路
を駆動するPWM回路の出力電圧を検出するモニタ手段
と、このモニタ手段による検出電圧が一定値にある状態
を所定時間継続したことをもって前記パワー増幅回路へ
の電源供給を遮断する制御手段とを具備することを特徴
とするPWMアンプの保護回路。
A monitor means for generating a pulse width modulation (PWM) signal by comparing an analog input signal with a reference triangular wave signal and detecting an output voltage of a PWM circuit that drives a power amplification circuit; 1. A protection circuit for a PWM amplifier, comprising: control means for cutting off power supply to the power amplifier circuit when a state at a constant value continues for a predetermined period of time.
JP62287887A 1987-11-13 1987-11-13 Protecting circuit for pwm amplifier Pending JPH01129515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62287887A JPH01129515A (en) 1987-11-13 1987-11-13 Protecting circuit for pwm amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62287887A JPH01129515A (en) 1987-11-13 1987-11-13 Protecting circuit for pwm amplifier

Publications (1)

Publication Number Publication Date
JPH01129515A true JPH01129515A (en) 1989-05-22

Family

ID=17723007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62287887A Pending JPH01129515A (en) 1987-11-13 1987-11-13 Protecting circuit for pwm amplifier

Country Status (1)

Country Link
JP (1) JPH01129515A (en)

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* Cited by examiner, † Cited by third party
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EP0661802A1 (en) * 1993-12-31 1995-07-05 STMicroelectronics S.r.l. Operational amplifier protection circuit using, either in working conditions or at start-up, identical circuit elements for detecting permanent output abnormal conditions
EP1093220A1 (en) * 1999-10-15 2001-04-18 STMicroelectronics S.r.l. Method of anomalous offset detection and circuit
US6469575B2 (en) 2000-12-01 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Circuit for amplifying and outputting audio signals
JP2006211523A (en) * 2005-01-31 2006-08-10 Asahi Kasei Microsystems Kk Digital switching circuit
JP2007235526A (en) * 2006-03-01 2007-09-13 Matsushita Electric Ind Co Ltd Pulse modulation type power amplifier
JP2010272904A (en) * 2009-05-19 2010-12-02 Yazaki Corp Class-d amplifier failure detection apparatus
US8289708B2 (en) 2008-02-06 2012-10-16 Panasonic Corporation Electric equipment
CN111431592A (en) * 2020-03-30 2020-07-17 京信通信系统(中国)有限公司 Power amplifier protection method, power amplifier protection device and computer storage medium

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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