JP2007288431A - Pulse-modulation power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse-modulation power amplifier capable of being simply configured with few circuits, capable of being integrated on a small area with low power consumption, and capable of performing output control and protection within a short time from a clock shut down. <P>SOLUTION: The amplifier comprises a pulse modulator 1 for converting an input signal into a pulse train by making a clock and the input signal to be inputs, a clock detecting circuit 14 for outputting a signal different from that is to be outputted when the clock is normal after detecting stop of the clock when the clock is to be stopped, an output control circuit 2 for making a pulse train which is outputted by the pulse modulator and the output of the clock detecting circuit to be inputs, and an output circuit 3 for switching in response to an output pulse train outputted by the output control circuit. The output control circuit is designed to control switching of the output circuit to be stopped in response to a signal which is different from what is to be outputted by the clock detecting circuit at the time when the clock is normal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pulse modulation type power amplifier, and mainly relates to prevention of destruction of a class D audio amplifier when the clock is stopped.

  In recent years, class D audio amplifiers using pulse width modulation (hereinafter referred to as PWM modulation) or delta-sigma modulation have been used. Pulse modulation type power amplifiers such as class D amplifiers are more energy efficient than class A amplifiers and class B amplifiers that amplify analog signals, and are being actively put to practical use.

  FIG. 8 shows a block diagram of a general pulse modulation type power amplifier. A general pulse modulation type power amplifier includes a pulse modulator 1 that receives a clock A and an analog signal B, and an output circuit 3 that performs switching according to a pulse train C output from the pulse modulator 1. An output control circuit 2 including a drive circuit and an arithmetic circuit is inserted between the pulse modulator 1 and the output circuit 3 as necessary. The analog signal B is converted into a pulse train by the pulse modulator 1, and the output circuit 3 performs switching according to the high and low of the pulse train. The analog signal is restored by passing the signal from the output circuit 3 through the low-pass filter 4, and the load (speaker) 5 is driven. (For example, refer nonpatent literature 1).

  In addition, means for preventing current from continuously flowing to the output terminal of the pulse modulation type power amplifier has been proposed. FIG. 9 shows a block diagram of an audio output protection circuit proposed in Patent Document 1. In FIG. The same reference numerals as in FIG. 8 indicate the same elements. In this circuit, the low-pass filter 4 connected to the output terminal is composed of an inductor and a capacitor, and a current detection (mutual) inductor 6 is disposed so as to generate a mutual induction action with the inductor. The current detection inductor 6 is connected to a rectifier 7, and the output of the rectifier 7 is supplied to the flip-flop 8 via the low-pass filter 4a.

  The current flowing through the output terminal is detected by the current detection inductor 6. The current is converted into a voltage by the rectifier 7 and the low-pass filter 4a. When the voltage input to the flip-flop 8 becomes equal to or higher than a preset voltage value, the output terminal is regarded as short-circuited. At this time, an output stop signal is sent from the flip-flop 8 to protect the load and the output circuit from destruction.

  FIG. 10 shows a block diagram of a digital amplifier having a protection device proposed in Patent Document 2. In FIG. In this circuit, both ends of the inductor constituting the low-pass filter 4 connected to the output terminal are input to the amplifier 10. The output of the amplifier 10 is input to a filter circuit 11 that compensates for a deviation in linearity between the impedance and frequency of the inductor. The output of the filter circuit 11 is input to the microcomputer 13 via the detection circuit 12. The output control circuit 2 is configured such that the pulse train C is input to the drive circuit via the gate circuit, and the output of the microcomputer 13 is supplied as one input of the gate circuit. The output of the low-pass filter 4 is supplied to the load (speaker) 5 through the output relay 9, and the output relay 9 is controlled by the microcomputer 13.

The output of the filter circuit 11 is a detection signal of the current flowing through the inductor, and the microcomputer 13 compares the input current detection signal with a preset reference value. When an overcurrent flows through the inductor, the current detection signal exceeds the reference value of the microcomputer 13 and it is determined that the output is short-circuited. At this time, the gate circuit of the output control circuit 2 and the output relay 9 are operated by the output short circuit detection signal supplied from the microcomputer 13 to stop the output, so that the load and the output circuit can be protected from destruction. .
Class D / Digital amplifier design and production, CQ Publisher Japanese Patent Laid-Open No. 5-160649 JP 2005-203968 A

  In a pulse modulation type power amplifier, when EMI occurs or when a physical shock is applied, a pulse modulation occurs due to a problem in the clock generation means and the connection from the clock generation means to the pulse modulator. When the clock signal input to the device stops, it stops with a direct current flowing from the output terminal to a load such as a speaker or headphones. If the direct current exceeds the allowable current of the load, heat is generated and the human body is harmed, or the speaker or headphones connected to the output terminal or the pulse modulation type power amplifier itself is destroyed. Therefore, it is desirable to provide means for preventing current from continuing to flow through the output terminal.

  Conventionally, as in Patent Document 1 and Patent Document 2, an attempt has been made to protect this problem by directly measuring the current at the output terminal. However, the method of measuring the current at the output terminal requires various analog circuits, such as an analog amplifier, a reference voltage source, a high-precision comparator that compares with the reference current, and an analog filter that averages the measured values of voltage or current. In addition, the circuit is complicated and power consumption is large. In addition, since the signal of the output terminal is fed back and controlled, there is a problem that it takes time from output short-circuit determination to output control. Furthermore, in the configuration of Patent Document 1, it becomes difficult to integrate by using mutual inductance, and accordingly, an increase in mounting area becomes a problem.

  The present invention provides a pulse modulation type power amplifier that can be simply configured with a small number of circuits, can be integrated with a small area, low power consumption, and can be controlled and protected in a short time after the clock is stopped. The purpose is to do.

  In order to achieve the above object, a pulse modulation type power amplifier according to the present invention includes a pulse modulator that receives a clock and an input signal as input and converts the input signal into a pulse train. A clock detection circuit that outputs a signal different from the time, an output control circuit that receives the pulse train output from the pulse modulator and the output of the clock detection circuit, and switching according to the output pulse train output from the output control circuit The output control circuit controls the output circuit to stop switching in response to a signal output from the clock detection circuit that is different from that when the clock is normal.

  The pulse modulation type power amplifier of the present invention configured as described above prevents the current from continuing to flow to the output terminal by detecting the clock stop by the clock detection circuit and stopping the switching of the output circuit by the output control circuit when the clock stops. . Thereby, even when the clock is stopped, it is possible to prevent harm to the human body and destruction of the speaker or headphones connected to the output terminal or the pulse modulation type power amplifier itself. In addition, since the clock detection circuit of the present invention can be simply configured with a small number of circuits, it can be integrated with a small area and low power consumption, and further, since it is feedforward control from the clock, the clock detection circuit can be shortened. Output control and protection are possible over time.

  In the pulse modulation type power amplifier of the present invention configured as described above, the clock detection circuit includes an inverter to which the clock is input, an integrator to which the output of the inverter is input, and an output of the integrator to a predetermined reference value. And a comparator for detecting whether the output is out of the normal range by the comparator. It can be set as the structure which outputs a signal different from the time of normal.

  Alternatively, the clock detection circuit includes a frequency divider to which the clock is input, an integrator to which the output of the frequency divider is input, and an output of the integrator that is compared with a predetermined reference value in a normal range. And a comparator that detects whether the clock is within the normal range when the comparator detects that the integrator output is out of a normal range. It can be set as the structure to do.

  In the above configuration, the integrator can be configured with a low-pass filter.

  The output control circuit includes a first output control circuit that receives the output of the pulse modulator and the output of the clock detection circuit, a signal obtained by inverting the output of the pulse modulator, and the output of the clock detection circuit. A second output control circuit that receives the output of the first output control circuit, and the output circuit receives the output of the second output control circuit. The second output circuit can be configured such that the outputs of the first output circuit and the second output circuit are of a differential type.

  The pulse modulator may be configured to output any one of a pulse train that has been subjected to pulse width modulation (PWM), a pulse train that has been subjected to pulse density modulation (PDM), or a pulse train that has been subjected to delta-sigma modulation.

  Further, the output signal can be an audio signal.

(First embodiment)
FIG. 1 is a block diagram of a single output pulse modulation type power amplifier according to a first embodiment of the present invention. This pulse modulation type power amplifier is switched by a pulse modulator 1 that receives a clock A and an input signal B, an output control circuit 2 that receives an output signal C of the pulse modulator 1, and an output of the output control circuit 2. And the clock detection circuit 14 that receives the clock A and transmits the output inhibition signal E to the output control circuit 2. The clock detection circuit 14 detects the stop of the clock A, and generates an output inhibition signal E when the clock is stopped. The output signal D of the output circuit 3 passes through the low-pass filter 4 and is then supplied to the speaker and the headphones 5.

  The output control circuit 2 includes a NAND circuit 2a and a NOR circuit 2b, and each of the pulse modulator outputs C is supplied as one input. Further, the output inhibition signal E from the clock detection circuit 14 is supplied as the other input of the NOR circuit 2b. Further, a signal obtained by passing the output inhibition signal E through the inverter circuit 2c is supplied as the other input of the NAND circuit 2a. The calculation results by the NAND circuit 2a and the NOR circuit 2b are output as a pulse train.

  The output circuit 3 includes a PMOS transistor 3a and an NMOS transistor 3b, and the output of the output control circuit 2 is connected to the gate terminals of the PMOS transistor 3a and the NMOS transistor 3b. When the pulse train supplied from the output control circuit 2 is at a high voltage, the NMOS transistor 3b is turned on, and when the pulse train is at a low voltage, the PMOS transistor 3a is turned on. When the PMOS transistor 3a is turned on, the output terminal of the output circuit 3 is connected to the first power supply 21, and when the NMOS transistor 3b is turned on, the output terminal is connected to the second power supply 22. Therefore, the output signal D also becomes a pulse train and is converted into an analog signal by passing through the low-pass filter 4.

  The operation of the pulse modulation type power amplifier of FIG. 1 is shown in FIG. A, B, D, and E show the waveforms of the corresponding signals in FIG. When the clock A is operating normally, the pulse modulator 1 modulates the analog input signal B into a pulse train. The output control circuit 2 calculates the pulse modulator output C and outputs a pulse train. Based on the pulse train from the output control circuit 2, the output circuit 3 outputs a pulse train as the output signal D.

  When the stop of the clock A occurs, the clock detection circuit 14 detects the stop of the clock and sends an output inhibition signal E to the output control circuit 2. As a result, the operation of the output control circuit 2 is changed, and a high voltage is input to the PMOS transistor 3a of the output circuit 3 and a low voltage is input to the NMOS transistor 3b. Therefore, the PMOS transistor 3a and the NMOS transistor 3b are turned off, the output terminals are not connected to the first power supply 21 and the second power supply 22, and the current flowing through the load 5 is also stopped by the output signal D.

  On the other hand, in the configuration without the clock detection circuit 14, the following problem occurs. First, when the stop of the clock A occurs, the pulse modulator 1 cannot convert the analog input signal B into a pulse train and outputs an indefinite value. When this signal is input to the output control circuit 2 and calculated, the output control circuit 2 always outputs a high voltage or a low voltage. When a high voltage is always output, the NMOS transistor 3b of the output circuit 3 is always turned on, and a current continues to flow from the second power supply 22 as the output signal D. When a low voltage is always output, the PMOS transistor 3a of the output circuit 3 is always turned on, and current continues to flow from the first power supply 21 as the output signal D. Therefore, current continues to flow through the load 5 due to the output signal D, and heat generation and destruction occur.

  In the above description, a single-output pulse modulation type power amplifier is taken as an example. However, as shown in FIG. 3, a first output control circuit 2A having a pulse modulator output C and a clock detection circuit output E as inputs. A second output control circuit 2B that receives a signal obtained by inverting the pulse modulator output C and a clock detection circuit output E, and a first output circuit 3A that receives the output of the first output control circuit 2A. The second output circuit 3B may be provided with the output of the second output control circuit 2B as an input, and the output of the first output circuit 3A and the output of the second output circuit 3B may be differential outputs. .

(Second Embodiment)
A clock detection circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of the clock detection circuit 14 constituting the pulse modulation type power amplifier shown in FIG. 1 or 3 in this embodiment.

  The clock detection circuit of the present embodiment includes an inverter 15 that receives the clock A, an integrator 16 that receives the inverter output F, a first comparator 17 that compares the integrator output G and the reference voltage VREFH, It comprises a second comparator 18 that compares the integrator output G and the reference voltage VREFL, and an EX-NOR circuit 19 that receives the outputs of the first comparator 17 and the second comparator 18 as inputs. The integrator 16 is composed of a low-pass filter whose cut-off frequency (f = 1 / 2πCR) is sufficiently smaller than the clock frequency.

  The operation of this clock detection circuit will be described with reference to the waveform diagram of FIG. The clock A is input to the inverter 15, and the voltage of the output signal F is averaged by passing through the integrator 16. The output signal G of the integrator 16 is input to a comparator 17 that uses VREFH as a reference voltage and a comparator 18 that uses VREFL as a reference voltage. The outputs of the two comparators are input to the EX-NOR circuit 19, and when the two comparator outputs are different, the output of the EX-NOR circuit 19 is a low voltage, and when the two comparator outputs are equal, the EX-NOR circuit The output of 19 becomes a high voltage.

  When the clock A is operating normally, the signal G is smaller than VREFH and larger than VREFL as shown before the clock stop in FIG. Therefore, the comparator 17 outputs a low voltage because the input G is smaller than the reference voltage, and the comparator 18 outputs a high voltage because the input G is larger than the reference voltage. Thus, since the two comparator outputs are different, the output of the EX-NOR circuit 19 becomes a low voltage.

  When the clock stops, the signal voltage G after passing through the integrator 16 becomes larger than VREFH when the clock A sticks to a high voltage, and when the clock A sticks to a low voltage, the signal after the integrator 16 passes. The signal voltage G becomes smaller than VREFL. That is, in both the comparators 17 and 18, the input voltage becomes larger than the reference voltage or becomes smaller than the reference voltage. As a result, the outputs of the two comparators 17 and 18 become equal, and the output of the EX-NOR circuit 19 that receives the outputs of the two comparators 17 and 18 becomes a high voltage. As a result, it is determined that the clock A has stopped, and the output of the EX-NOR circuit 19 is transmitted to the output control circuit 2 of FIG.

(Third embodiment)
A clock detection circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing the configuration of the clock detection circuit 14 constituting the pulse modulation type power amplifier shown in FIG. 1 or 3 in this embodiment.

  The clock detection circuit of the present embodiment includes a frequency divider 20 that receives clock A, an integrator 16 that receives frequency divider output H, and a first that compares output G of integrator 16 and reference voltage VREFH. Comparator 17, a second comparator 18 for comparing the integrator output G and the reference voltage VREFL, and an EX-NOR circuit 19.

  The operation of this clock detection circuit will be described with reference to the waveform diagram of FIG. The clock A is input to the frequency divider 20, and the output signal H passes through the integrator 16 so that the voltage is averaged. The signal G of the integrator 16 is input to a comparator 17 using VREFH as a reference voltage and a comparator 18 using VREFL as a reference voltage. The outputs of the two comparators are input to the EX-NOR circuit 19. When the two comparator outputs are different, the output of the EX-NOR circuit is low, and when the two comparator outputs are equal, the output of the EX-NOR circuit is The output becomes a high voltage.

  When the clock A is operating normally, the signal H that has passed through the frequency divider 20 has a duty ratio of 50%. Therefore, when averaged by the integrator 16, the signal G becomes an intermediate value of the clock amplitude, and becomes a voltage smaller than VREFH and larger than VREFL. Therefore, the comparator 17 outputs a low voltage because the input G is smaller than the reference voltage, and the comparator 18 outputs a high voltage because the input G is larger than the reference voltage. Thus, since the two comparator outputs are different, the output of the EX-NOR circuit 19 becomes a low voltage.

  When the clock stops, the signal voltage G after passing through the integrator 16 becomes larger than VREFH when the clock A sticks to a high voltage, and when the clock A sticks to a low voltage, the signal after the integrator 16 passes. The signal voltage G becomes smaller than VREFL. That is, in both the comparators 17 and 18, the input voltage becomes larger than the reference voltage or becomes smaller than the reference voltage. As a result, the outputs of the two comparators 17 and 18 become equal, and the output of the EX-NOR circuit 19 that receives the outputs of the two comparators 17 and 18 becomes a high voltage. Thereby, it is determined that the clock has stopped, and the output of the EX-NOR circuit 19 is transmitted to the output control circuit 2 of FIG.

  In the above description, a block for converting an input signal into a pulse train is described as a pulse modulator. For example, this is a PWM modulator, a PDM modulator, a delta sigma modulator, or the like.

  In the above clock detection circuit, the comparator outputs a high voltage when the output G of the integrator 16 is larger than the reference voltage, and outputs a low voltage when the output G is smaller than the reference voltage. The EX-NOR circuit may be replaced with an EX-OR circuit by inverting the input / output relationship of the comparator.

  The pulse modulation type power amplifier of the present invention is useful for preventing destruction of pulse modulation type power amplifiers and peripheral devices such as class D audio amplifiers that handle audio signals, and for integrating destruction prevention circuits.

1 is a block diagram of a single-output pulse modulation type power amplifier according to a first embodiment of the present invention. Signal waveform diagram showing operation of the pulse modulation type power amplifier according to the same embodiment Block diagram of a pulse modulation type power amplifier in which the configuration of the embodiment is applied to a BTL configuration Circuit diagram of a clock detection circuit according to a second embodiment of the present invention Signal waveform diagram showing operation of the same clock detection circuit Circuit diagram of a clock detection circuit according to a third embodiment of the present invention Signal waveform diagram showing operation of the same clock detection circuit Block diagram of a conventional general pulse modulation power amplifier Block diagram of a conventional audio output protection circuit Block diagram of a conventional digital amplifier protection device

Explanation of symbols

1 Pulse Modulator 2 Output Control Circuit 2a NAND Circuit 2b NOR Circuit 2c Inverter 2A First Output Control Circuit 2B Second Output Control Circuit 3 Output Circuit 3a PMOS Transistor 3b NMOS Transistor 3A First Output Circuit 3B Second Output Circuit 4, 4a Low-pass filter 5 Load (speaker)
6 Current detection (mutual) inductor 7 Rectifier 8 Flip-flop 9 Output relay 10 Amplifier 11 Filter circuit 12 Detection circuit 13 Microcomputer 14 Clock detection circuit 15 Inverter 16 Integrator (low-pass filter)
17 Comparator having VREFH as reference voltage 18 Comparator having VREFL as reference voltage 19 EX-NOR circuit 20 Frequency dividers 21 and 22 Power supply

Claims (7)

A pulse modulator that receives the clock and the input signal as input and converts the input signal into a pulse train;
A clock detection circuit for detecting a stop of the clock and outputting a signal different from that when the clock is normal when the clock is stopped;
An output control circuit that receives the pulse train output from the pulse modulator and the output of the clock detection circuit; and
An output circuit that switches according to an output pulse train output by the output control circuit,
The output control circuit controls the output circuit to stop switching in accordance with a signal output from the clock detection circuit that is different from that when the clock is normal. The clock detection circuit includes:
An inverter to which the clock is input;
An integrator to which the output of the inverter is input;
A comparator for detecting whether the output of the integrator is within a normal range by comparing with a predetermined reference value;
The pulse modulation type power amplifier according to claim 1, wherein when the comparator detects that the output of the integrator is out of a normal range, a signal different from that when the clock is normal is output. The clock detection circuit includes:
A frequency divider to which the clock is input;
An integrator to which the output of the divider is input;
A comparator for detecting whether the output of the integrator is within a normal range by comparing with a predetermined reference value;
The pulse modulation type power amplifier according to claim 1, wherein when the comparator detects that the output of the integrator is out of a normal range, a signal different from that when the clock is normal is output.   4. The pulse modulation type power amplifier according to claim 2, wherein the integrator is constituted by a low pass filter. The output control circuit receives a first output control circuit that receives an output of the pulse modulator and an output of the clock detection circuit, an inverted signal of the output of the pulse modulator, and an output of the clock detection circuit And a second output control circuit
The output circuit includes a first output circuit that receives the output of the first output control circuit, and a second output circuit that receives the output of the second output control circuit,
2. The pulse modulation type power amplifier according to claim 1, wherein outputs of the first output circuit and the second output circuit are differential.   2. The pulse modulation type power amplifier according to claim 1, wherein the pulse modulator outputs one of a pulse train subjected to pulse width modulation (PWM), a pulse train subjected to pulse density modulation (PDM), or a pulse train subjected to delta sigma modulation. 3. .   7. The pulse modulation type power amplifier according to claim 6, wherein the output signal is an audio signal.

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