JP4016833B2 - Pulse width modulation amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width modulation amplifier in which a DC (direct current) offset included in a pulse width modulation output is removed.
[0002]
[Prior art]
DC offset included in the pulse width modulation output, that is, unnecessary DC component included in the pulse width modulation output generated by pulse width modulation amplification of the input signal whose DC level is not included in the time average value of the signal level. Pulse width modulation amplifiers that have been eliminated are conventionally known.
[0003]
As such a pulse width modulation amplifier, the DC offset included in the pulse width modulation output is detected, and the detection result is fed back to the sawtooth generator side used to generate the pulse width modulation signal as an error signal, There is one in which the direct current level of the sawtooth wave generated by the sawtooth wave generator is changed in accordance with the level of the error signal (see, for example, Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Publication No. 2-60089 [0005]
[Problems to be solved by the invention]
However, in the conventional pulse width modulation amplifier, when the error signal is detected, the time average of the pulse width modulation output is detected, and the peak-to-peak level of the pulse width modulation output is detected. A difference from 1/2 of the level is taken as an error signal, and a large number of circuits are required just to detect the error signal. Furthermore, when this error signal is fed back to the sawtooth generator side, a low-pass filter (LPF), a DC amplifier and an adder are used, which increases the manufacturing cost.
[0006]
The present invention has been made paying attention to this point, and it is an object of the present invention to provide a pulse width modulation amplifier capable of removing a DC offset included in a pulse width modulation output while reducing manufacturing costs. To do.
[0007]
[Means for Solving the Problems]
To achieve the above object, a pulse width modulation amplifier according to claim 1 is provided with a BTL output circuit, and outputs two pulse width modulation amplification signals from the BTL output circuit based on an input signal. , Comparing the level of each pulse width modulation amplified signal including a DC offset to generate a duty pulse, and integrating the duty pulse to output a signal of a level proportional to the DC offset and integration means, by combining the signals output by said integrating means to the input signal, possess a removing means for removing a DC offset included in the pulse width modulation amplifier signal, the integrating means is a low pass filter characterized in that it consists of.
[0008]
In order to achieve the above object, the pulse width modulation amplifier according to claim 2 is a pulse width modulation amplifier that outputs a pulse width modulation amplification signal based on an input signal, wherein the pulse width modulation amplification signal includes a DC offset. The comparator means for generating a duty pulse by comparing the level of the output with a predetermined value, an integrator means for outputting a signal of a level proportional to the DC offset by integrating the duty pulse, and an output by the integrator means by combining the signals in the input signal, possess a removing means for removing a DC offset included in the pulse width modulation amplifier signal, the integrating means is characterized by comprising a low-pass filter.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0010]
FIG. 1 is a block diagram showing an overall configuration of a pulse width modulation amplifier according to an embodiment of the present invention.
[0011]
As shown in the figure, the pulse width modulation amplifier of the present embodiment includes a left channel (Lch) pulse width modulation amplification unit 1 having a BTL (Balanced Transformer Less) output circuit that operates with a single power supply VBB. Similarly, a right channel (Rch) pulse width modulation amplifying unit 2 having a BTL output circuit operating with a single power supply and a triangular wave of a predetermined frequency are generated, and this triangular wave is supplied to the pulse width modulation amplifying units 1 and 2. It is mainly configured by the triangular wave generator 3 to be supplied.
[0012]
The Lch pulse width modulation amplifying unit 1 compares the level of the amplified input signal IN with the level of the triangular wave supplied from the triangular wave generator 3 with the input signal amplifying unit 11 that amplifies the input signal IN that is an audio signal. Thus, a pulse width modulation (PWM) unit 12 that generates a pulse signal having a duty ratio according to the level of the input signal IN, field effect transistors PNM1, PPM1, PNM2, PPM2, and the field effect transistors PNM1, PPM1, PNM2 , PPM2 switching MOS (Metal Oxicide Semiconductor) driver 13 and the output terminals + OUT, -OUT are short-circuited, and so on, so that an excessive current flowing in the field effect transistors PNM1, PPM1, PNM2, PPM2 is applied to the resistor R41. First overcurrent detection (OC) detected by detecting the voltage value ) The above-described excessive current flowing through the circuit 14 and the field effect transistors PNM1, PPM1, PNM2, and PPM2 is detected by detecting a voltage value applied to the resistor R46, and a speaker connected through an LC filter described later. When the other signal input terminal of the speaker is grounded while one signal input terminal of (load R) is connected to one of the output terminals + OUT and −OUT, the above-mentioned resistance The second overcurrent detection (OCP) circuit 15 detects the negative voltage applied to R46 by detecting the negative voltage.
[0013]
The driver 13 and the field effect transistors PNM1, PPM1, PNM2, and PPM2 constitute a BTL output circuit, and this BTL output circuit is operated by a single power supply VBB.
[0014]
The pulse width modulation output is supplied from the pulse width modulation unit 12 to the driver 13, and the driver 13 generates an inverted pulse obtained by inverting the pulse width modulation output, and outputs the pulse width modulation output and the inverted pulse.
[0015]
The first complementary circuit composed of the P-channel field effect transistor PPM1 and the N-channel field effect transistor PNM1 is driven by the pulse width modulation output output from the driver 13, and an inverted pulse of the pulse width modulation output output from the driver 13 Thus, the second complementary circuit composed of the P-channel field effect transistor PPM2 and the N-channel field effect transistor PNM2 is driven.
[0016]
As shown in FIG. 2, the outputs of the first and second complementary circuits are sent to a first low-pass filter composed of a coil L1 and a capacitor C1 and a second low-pass filter composed of a coil L2 and a capacitor C2. The high frequency component is removed by the first and second low pass filters, respectively, and the load (speaker) R is driven by the outputs of the first and second low pass filters.
[0017]
Since the first and second overcurrent detection circuits 14 and 15 are not essential to the present invention, description thereof is omitted.
[0018]
Further, since the Rch pulse width modulation amplification unit 2 is configured in the same manner as the Lch pulse width modulation amplification unit 1, its detailed configuration is not shown.
[0019]
FIG. 2 is a diagram illustrating an example of a configuration of a DC offset removal circuit that removes a DC offset included in the pulse width modulation output from the Lch pulse width modulation amplification unit 1. In FIG. The low-pass filter and load R are also shown.
[0020]
As shown in the figure, the DC offset removal circuit compares the positive (+) side pulse width modulation output output from the Lch pulse width modulation amplification unit 1 with the negative (−) side pulse width modulation output, A comparator CMP that outputs a voltage of a level according to the comparison result, and an integration circuit 4 comprising, for example, a low-pass filter (LPF) that integrates the output from the comparator CMP and extracts only the DC component contained in the output. The adder 5 adds the output signal from the integrating circuit 4 and the input signal IN0.
[0021]
The comparator CMP operates with a power supply voltage VDD (for example, 5 V) that is lower than the power supply voltage VBB of the pulse width modulation amplification unit 1. That is, the comparator CMP compares the pulse width modulation outputs on both sides to generate a pulse train having the same shape as that of the pulse width modulation output and having its signal level lowered, that is, a duty pulse.
[0022]
The integrating circuit 4 smoothes the duty pulse. Here, since the DC offset included in the pulse width modulation output appears as a duty error of the duty pulse, the integration circuit 4 smoothes the duty error. As a result, the integration circuit 4 outputs a signal having a level proportional to the DC offset. The adder 5 adds a signal having a level proportional to the DC offset and the input signal IN0 to obtain an input signal IN to the Lch pulse width modulation amplification unit 1.
[0023]
For example, if the pulse width modulation output includes a positive level DC offset, the integration circuit 4 outputs a negative level signal. As a result, the level of the input signal IN decreases, and the duty ratio of the pulse width modulation output on each side is corrected in the decreasing direction. On the other hand, when a negative level DC offset is included in the pulse width modulation output, the operation is the reverse of the above operation.
[0024]
FIG. 3 is a diagram illustrating an example of a voltage waveform applied to the predetermined terminal of FIG. 2 when the DC offset removal circuit is not operated. FIG. 4 is a diagram illustrating the DC offset in the state of FIG. FIG. 3 is a diagram illustrating a voltage waveform applied to a predetermined terminal in FIG. 2 when a removal circuit is operated.
[0025]
As can be seen by comparing FIG. 3 and FIG. 4, by operating the DC offset elimination circuit, the duty error of the pulse width modulation output is reduced ((c)), and the DC offset included in the pulse width modulation output is Is removed ((b)).
[0026]
In this embodiment, the pulse width modulation amplifier provided with the BTL output circuit has been described as an example. However, the present invention is not limited to this, and the same applies to a normal pulse width modulation amplifier. Can be applied to.
[0027]
FIG. 5 is a diagram showing an example of a DC offset removal circuit provided in a normal pulse width modulation amplifier. In this figure, the difference from FIG. 2 is that the level of the pulse width modulation output from the Lch pulse width modulation amplification unit 1 ′ is compared with the ground potential by the comparator CMP. As a result, the comparator CMP generates a pulse train having the same shape as the pulse width modulation output from the pulse width modulation amplification unit 1 ′, with its signal level lowered, that is, a duty pulse, as in FIG. is doing. Other configurations and operations are not different from those shown in FIG.
[0028]
As described above, in this embodiment, the pulse width modulation output is compared, the comparison result is integrated, and the integration result is added to the input signal, thereby removing the DC offset included in the pulse width modulation output. Therefore, the DC offset removal circuit can be configured with a small number of parts, and thereby the DC offset included in the pulse width modulation output can be removed while reducing the manufacturing cost.
[0029]
【The invention's effect】
As described above, according to the first or second aspect of the invention, the level of the pulse width modulation amplification signal is compared, the integration of the comparison result and the DC offset removal according to the integration result are eliminated. Since the DC offset included in the pulse width modulation amplification signal can be removed, the DC offset included in the pulse width modulation output can be removed while reducing the manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a pulse width modulation amplifier according to an embodiment of the present invention.
2 is a diagram illustrating an example of a configuration of a DC offset removal circuit that removes a DC offset included in a pulse width modulation output from an Lch pulse width modulation amplification unit in FIG. 1;
3 is a diagram illustrating an example of a voltage waveform applied to a predetermined terminal of FIG. 2 when the DC offset removal circuit of FIG. 2 is not operated.
4 is a diagram illustrating a voltage waveform applied to a predetermined terminal in FIG. 2 when the DC offset removal circuit in FIG. 2 is operated in the state of FIG. 3;
FIG. 5 is a diagram showing an example of a DC offset removal circuit provided in a normal pulse width modulation amplifier.
[Explanation of symbols]
1 Lch pulse width modulation amplification unit, 3 triangular wave generator, 4 integration circuit, 5 adder, 12 pulse modulation (PWM) unit, 13 MOS driver, PNM1, PPM1, PNM2, PPM2 field effect transistor, CMP comparator

Claims (2)

In a pulse width modulation amplifier that includes a BTL output circuit and outputs two pulse width modulation amplification signals from the BTL output circuit based on an input signal,
Comparing means for generating a duty pulse by comparing the level of each pulse width modulated amplified signal including a DC offset;
An integrating means for outputting a signal having a level proportional to the DC offset by integrating the duty pulse;
By combining the signals output by said integrating means to the input signal, possess a removing means for removing a DC offset included in the pulse width modulation amplifier signal,
2. The pulse width modulation amplifier according to claim 1, wherein the integrating means comprises a low pass filter . In a pulse width modulation amplifier that outputs a pulse width modulation amplification signal based on an input signal,
Comparing means for generating a duty pulse by comparing the level of the pulse width modulated amplified signal including a DC offset with a predetermined value;
An integrating means for outputting a signal having a level proportional to the DC offset by integrating the duty pulse;
By combining the signals output by said integrating means to the input signal, possess a removing means for removing a DC offset included in the pulse width modulation amplifier signal,
2. The pulse width modulation amplifier according to claim 1, wherein the integrating means comprises a low pass filter .

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