JPH01128603A - Current mirror circuit - Google Patents

Current mirror circuit

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Publication number
JPH01128603A
JPH01128603A JP62287122A JP28712287A JPH01128603A JP H01128603 A JPH01128603 A JP H01128603A JP 62287122 A JP62287122 A JP 62287122A JP 28712287 A JP28712287 A JP 28712287A JP H01128603 A JPH01128603 A JP H01128603A
Authority
JP
Japan
Prior art keywords
current
voltage
transistor
mirror circuit
equal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62287122A
Other languages
Japanese (ja)
Inventor
Yutaka Sada
佐田 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62287122A priority Critical patent/JPH01128603A/en
Publication of JPH01128603A publication Critical patent/JPH01128603A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enlarge the output impedance of a current mirror circuit by executing negative feedback control with using an error amplifier and causing the input terminal voltage of the current mirror circuit to be equal to an output terminal voltage. CONSTITUTION:An error amplifier 5 causes the voltage of an input terminal 3 to be equal to the voltage of an output terminal 4 by the negative feedback control. Accordingly, the voltages between the collectors of transistors 1 and 2 go to be equal. As the result, when the characteristics of the transistors 1 and 2 are equal, an emitter current, a current amplifying rate (hfe) and a collector current are made equal and accordingly, the input current of the input terminal 3 and the output current of the output terminal 4 go to be equal. Since the current of a constant current source 7 is constant regardless of the voltage of a voltage source 8, the current of the output terminal 4 goes to be constant in the same way. This shows that the output impedance of the current mirror circuit is infinite.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はカレントミラー回路に関し、特に集積回路化に
適したカレントミラー回路に間する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current mirror circuit, and particularly to a current mirror circuit suitable for integration into an integrated circuit.

[従来の技術] 従来のカレントミラー回路は、第7図に示すよ・うな構
成であり、1.2はカレントミラー構成用トランジスタ
、3は入力端子、4は出力端子、7は低電流源、6,8
は電圧源であり、入力端子3の電圧は、出力端子4の電
圧と関係なく一定であった。
[Prior Art] A conventional current mirror circuit has a configuration as shown in FIG. 6,8
is a voltage source, and the voltage at the input terminal 3 was constant regardless of the voltage at the output terminal 4.

[発明が解決しようとする問題点コ 上述した従来のカレントミラー回路は、トランジスタ2
のアーリー電圧が有限であるため、出力インピーダンス
が低いという欠点がある。これは出力端子4の電圧が変
化すると、トランジスタ2のコレクタ・エミッタ間電圧
が変化し、トランジスタ2の電流増幅率hfeが変化す
るので、トランジスタ2のコレクタ電流すなわち出力電
流が変化することによる。第7図のカレントミラー回路
において、トランジスタ2のアーリー電圧をVA。
[Problems to be solved by the invention] The conventional current mirror circuit described above has a transistor 2
Since the early voltage of is finite, it has the disadvantage of low output impedance. This is because when the voltage at the output terminal 4 changes, the collector-emitter voltage of the transistor 2 changes, and the current amplification factor hfe of the transistor 2 changes, so the collector current of the transistor 2, that is, the output current changes. In the current mirror circuit of FIG. 7, the early voltage of transistor 2 is VA.

コレクタ電流を■○UT、出力端子4の電圧をVOUT
、定電流源6の電圧をVCCとおくと、本カレントミラ
ー回路の出力インピーダンスZoは、ZO=VA+ (
VCC−VOUT)/l0UTとなる。例えば、VA=
6V、r OUT=1mA。
Collector current is ■○UT, voltage of output terminal 4 is VOUT
, the voltage of the constant current source 6 is set to VCC, the output impedance Zo of this current mirror circuit is ZO=VA+ (
VCC-VOUT)/l0UT. For example, VA=
6V, r OUT = 1mA.

VCC=5V、VOUT=2.5V(7)場合上式から
出力インピーダンスZ′0は8.5にΩになる。
When VCC=5V and VOUT=2.5V (7), the output impedance Z'0 becomes 8.5Ω from the above equation.

第3図のグラフはそのシミュレーション結果であり、従
来例は直線PAで示されているように出力インピーダン
スが低いことがわかる。
The graph in FIG. 3 is the simulation result, and it can be seen that the conventional example has a low output impedance, as shown by the straight line PA.

[発明の従来技術に対する相違点] 上述した従来のカレントミラー回路に対し、本発明はカ
レントミラー回路の入力端子電圧を出力端子電圧に等し
くなるように誤差増幅器を用いて負帰還制御するという
相違点を持っている。
[Differences between the present invention and the prior art] The present invention differs from the conventional current mirror circuit described above in that negative feedback control is performed using an error amplifier so that the input terminal voltage of the current mirror circuit becomes equal to the output terminal voltage. have.

[問題点を解決するための手段] 本発明のカレントミラー回路は、カレントミラー回路の
入力端子電圧を出力端子電圧に等しくなるよう負帰還制
御する誤差増幅器を有している。
[Means for Solving the Problems] The current mirror circuit of the present invention includes an error amplifier that performs negative feedback control to make the input terminal voltage of the current mirror circuit equal to the output terminal voltage.

すなわち、本発明の要旨は、コレクタが入力端子に接続
された第1のトランジスタと、コレクタが出力端子に接
続された第2のトランジスタとを有・し、第1のトラン
ジスタのベースと第2のトランジスタのベースとが接続
されたカレントミラー回路において、第1のトランジス
タのコレクタ電圧が第2のトランジスタのコレクタ電圧
に等しくなるよう負帰還制御する誤差増幅器を有するこ
とである。
That is, the gist of the present invention is to include a first transistor whose collector is connected to an input terminal, and a second transistor whose collector is connected to an output terminal, and a base of the first transistor and a second transistor. The current mirror circuit connected to the base of the transistor includes an error amplifier that performs negative feedback control so that the collector voltage of the first transistor becomes equal to the collector voltage of the second transistor.

[実施例コ 策1叉施ヨ 次に本発明について、図面を参照して説明する。[Example code] First plan Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図である。本
実施例は、コレクタが入力端子3に接続されベースが誤
差増幅器6の出力に接続されエミッタが定電圧ri、6
の一方の端子に接続されたトランジスタ1と、コレクタ
が出力端子4に接続されベースが誤差増幅器5の出力に
接続されエミッタが定電圧源6の一方の端子に接続され
たトランジスタ2と、正転入力がトランジスタ1のコレ
クタに反転入力がトランジスタ2のコレクタにそれぞれ
接続された誤差増幅器5とを含む。7は定電流傅、8は
電圧源である。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In this embodiment, the collector is connected to the input terminal 3, the base is connected to the output of the error amplifier 6, and the emitter is connected to the constant voltage ri, 6.
, a transistor 2 whose collector is connected to the output terminal 4, whose base is connected to the output of the error amplifier 5, and whose emitter is connected to one terminal of the constant voltage source 6; An error amplifier 5 whose input is connected to the collector of transistor 1 and whose inverting input is connected to the collector of transistor 2 is included. 7 is a constant current source, and 8 is a voltage source.

次に実施例の動作について説明する。誤差増幅器5は、
負帰還制御す2ことにより、入力端子3の電圧を出力端
子4の電圧に等しくしようとする。
Next, the operation of the embodiment will be explained. The error amplifier 5 is
Negative feedback control 2 attempts to make the voltage at input terminal 3 equal to the voltage at output terminal 4.

従って、トランジスタlと2のコレクタエミッタ間電圧
が等しくなる。その結果、トランジスタ1と2の特性が
等しければ、エミッタ電流、電流増幅率hfeおよびコ
レクタ電流も等しくなり、従って入力端子3の入力端子
と出力端子4の出力電流が等しくなる。定電流源7の電
流は電圧源8の電圧によらず一定なので、出力端子4の
電流も同じく一定になる。これは本発明のカレントミラ
ー回路の出力インピーダンスが無限大であることを示し
ている。半導体集積回路の特徴として、同一チップ上の
トランジスタ間の特性の違いは小さくできるので、トラ
ンジスタ1と2の特性が等しいという仮定は妥当である
Therefore, the collector-emitter voltages of transistors 1 and 2 become equal. As a result, if the characteristics of transistors 1 and 2 are equal, the emitter current, current amplification factor hfe, and collector current will also be equal, and therefore the output currents of the input terminal 3 and the output terminal 4 will be equal. Since the current of the constant current source 7 is constant regardless of the voltage of the voltage source 8, the current of the output terminal 4 is also constant. This shows that the output impedance of the current mirror circuit of the present invention is infinite. As a feature of semiconductor integrated circuits, differences in characteristics between transistors on the same chip can be made small, so it is reasonable to assume that transistors 1 and 2 have the same characteristics.

第2図は第1の実施例の誤差増幅器5を、トランジスタ
101,102,103,104,106.107,1
08及び109と定電流源105とで構成した回路図で
ある。第3図は第2図の回路の出力電圧出力電流の関係
を、計算機シミュレーションにより求めたも′のであり
、直線EMIて示されているように出力電流は出力電圧
によらず一定である。トランジスタ2のアーリー電圧V
A=6V、定電流源7の電流は1mA、定電圧源6の電
圧は5vとして計算した。
FIG. 2 shows the error amplifier 5 of the first embodiment with transistors 101, 102, 103, 104, 106, 107, 1
08 and 109 and a constant current source 105. FIG. FIG. 3 shows the relationship between the output voltage and the output current of the circuit shown in FIG. 2, obtained by computer simulation, and as shown by the straight line EMI, the output current is constant regardless of the output voltage. Early voltage V of transistor 2
The calculation was performed assuming that A=6V, the current of the constant current source 7 was 1 mA, and the voltage of the constant voltage source 6 was 5V.

第1図のトランジスタ1及び2のエミッタと定電圧源6
との間に抵抗を入れた第4図の変形例や、第1図及び第
4図のPNP)ランジスタをNPNトランジスタtこ置
き換えた回路も本発明の技術的範囲に含まれる。
Emitters of transistors 1 and 2 and constant voltage source 6 in FIG.
A modified example of FIG. 4 in which a resistor is inserted between the two, and a circuit in which the PNP transistor shown in FIGS. 1 and 4 are replaced with an NPN transistor are also included within the technical scope of the present invention.

策λ大施貝 第5図は本発明の第2実施例の回路図であり、本実施例
はコレクタが入力端子3に接続され、ベースが誤差増幅
器5の出力に接続されたトランジスタ1と、コレクタが
出力端子4に接続されベースが誤差増幅器5の出力に接
続されたトランジスタ2と、ベース及びコレクタがトラ
ンジスタ1のこミッタに接続され、エミッタが定電圧R
6の一方の端子に接続されたトランジスタ10と、コレ
クタがトランジスタ26エミツタに接続され、ベースが
トランジスタ1のエミッタに接続されたトランジスタ1
1と、正転入力がトランジスタ1のコレクタに接続され
、反転入力がトランジスタ2のコレクタに接続された誤
差増幅器5とを含む。
Figure 5 is a circuit diagram of a second embodiment of the present invention, which includes a transistor 1 whose collector is connected to the input terminal 3 and whose base is connected to the output of the error amplifier 5; A transistor 2 has a collector connected to an output terminal 4, a base connected to the output of an error amplifier 5, a base and a collector connected to the committer of the transistor 1, and an emitter connected to a constant voltage R.
transistor 10 connected to one terminal of transistor 6, and transistor 1 whose collector is connected to the emitter of transistor 26 and whose base is connected to the emitter of transistor 1.
1, and an error amplifier 5 whose non-inverting input is connected to the collector of transistor 1 and whose inverting input is connected to the collector of transistor 2.

次に実施例の動作を説明する。誤差増幅器5の負帰還制
御により、入力端子3の電圧が出力端子4の電圧に等し
くなる。従ってトランジスタ1と2のエミッタ・コレク
タ間電圧、トランジスタlOと11のエミッタ・コレク
タ間電圧が等しくなる。トランジスタ10と11の電流
増幅率をhfe、定電流源7の電流をIIN、 出力端
子の電流をI OUTとおくと、 I 0UT= I I NXh f e/h f e+
2となる。トランジスタ10と11のコレクタ・エミッ
タ間電圧は出力端子4の電圧に依らず一定なのでhfe
も一定になり、出力電流も一定になる。
Next, the operation of the embodiment will be explained. Due to the negative feedback control of the error amplifier 5, the voltage at the input terminal 3 becomes equal to the voltage at the output terminal 4. Therefore, the emitter-collector voltages of transistors 1 and 2 and the emitter-collector voltages of transistors 10 and 11 become equal. Assuming that the current amplification factor of transistors 10 and 11 is hfe, the current of constant current source 7 is IIN, and the current of the output terminal is IOUT, then I0UT=IINXhfe/hfe+
It becomes 2. Since the collector-emitter voltage of transistors 10 and 11 is constant regardless of the voltage at output terminal 4, hfe
becomes constant, and the output current also becomes constant.

従って本実施例のカレントミラー回路の出力インゼーダ
ンスは無限大になる。第5図の回路(EM2)と、第8
図の従来例(PA)とについて、トランジスタL  2
. 16,11の電流増幅率を30、アーリー電圧を6
V、定電圧源6の電圧を5V、定電流源7の電流を1m
Aとして計算機シミュレーションした結果を第6図に示
す。第6図かられかるように第2の実施例によりカレン
トミラー回路出力インピーダンスを大きくすることがで
きる。
Therefore, the output intensity of the current mirror circuit of this embodiment becomes infinite. The circuit in Figure 5 (EM2) and the circuit in Figure 8
Regarding the conventional example (PA) in the figure, transistor L 2
.. 16, 11 current amplification factor is 30, early voltage is 6
V, the voltage of constant voltage source 6 is 5V, and the current of constant current source 7 is 1m.
The results of computer simulation as A are shown in FIG. As can be seen from FIG. 6, the output impedance of the current mirror circuit can be increased by the second embodiment.

[発明の効果コ 以上説明したように本発明は、誤差増幅器を用いて負帰
還制御して、カレントミラー回路の入力端子電圧を出力
端子電圧に等しくすることにより、カレントミラー回路
の出力インピーダンスを大きくてきる効果がある。
[Effects of the Invention] As explained above, the present invention uses negative feedback control using an error amplifier to make the input terminal voltage of the current mirror circuit equal to the output terminal voltage, thereby increasing the output impedance of the current mirror circuit. It has a positive effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例の回路図、第2図は第1実
施例の誤差増幅器の回路図、第3図は第・1実施例の特
性を示すグラフ、第4図は第1実施例の変形例を示す回
路図、第5図は第2実施例を示す回路図、第6図はメ2
実施例の特性を示すグラフ、第7図と第8図とはそれぞ
れ従来例を示す回路図である。 1.2・・・カレントミラー回路のトランジスタ、3・
・・・カレントミラー回路の入力端子、4・・・・カレ
ントミラー回路の出力端子、5・・・・誤差増幅器。 特許出願人  日本電気株式会社 代理人 弁理士  桑 井 清 − 第1図 第2図 第5図 第4図 第5図 1.0203,04.0v VOIJT(鳴子4の電圧) 笛6因
Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2 is a circuit diagram of the error amplifier of the first embodiment, Fig. 3 is a graph showing the characteristics of the first embodiment, and Fig. 4 is a graph showing the characteristics of the first embodiment. FIG. 5 is a circuit diagram showing a modification of the first embodiment, FIG. 5 is a circuit diagram showing the second embodiment, and FIG. 6 is a circuit diagram showing a modification of the first embodiment.
Graphs showing the characteristics of the embodiment, and FIGS. 7 and 8 are circuit diagrams showing conventional examples, respectively. 1.2... Current mirror circuit transistor, 3.
...Input terminal of current mirror circuit, 4...Output terminal of current mirror circuit, 5...Error amplifier. Patent Applicant: NEC Corporation Representative, Patent Attorney Kiyoshi Kuwai - Figure 1 Figure 2 Figure 5 Figure 4 Figure 5 1.0203,04.0v VOIJT (Voltage of Naruko 4) Whistle 6 factors

Claims (1)

【特許請求の範囲】[Claims] コレクタが入力端子に接続された第1のトランジスタと
、コレクタが出力端子に接続された第2のトランジスタ
とを有し、第1のトランジスタのベースと第2のトラン
ジスタのベースとが接続されたカレントミラー回路にお
いて、第1のトランジスタのコレクタ電圧が第2のトラ
ンジスタのコレクタ電圧に等しくなるよう負帰還制御す
る誤差増幅器を有することを特徴とするカレントミラー
回路。
A current transistor having a first transistor whose collector is connected to an input terminal, a second transistor whose collector is connected to an output terminal, and a base of the first transistor and a base of the second transistor are connected. 1. A current mirror circuit comprising an error amplifier that performs negative feedback control so that the collector voltage of the first transistor becomes equal to the collector voltage of the second transistor.
JP62287122A 1987-11-12 1987-11-12 Current mirror circuit Pending JPH01128603A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62287122A JPH01128603A (en) 1987-11-12 1987-11-12 Current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62287122A JPH01128603A (en) 1987-11-12 1987-11-12 Current mirror circuit

Publications (1)

Publication Number Publication Date
JPH01128603A true JPH01128603A (en) 1989-05-22

Family

ID=17713354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62287122A Pending JPH01128603A (en) 1987-11-12 1987-11-12 Current mirror circuit

Country Status (1)

Country Link
JP (1) JPH01128603A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101099A (en) * 2009-11-04 2011-05-19 Ricoh Co Ltd Voltage current converter circuit
CN111682767A (en) * 2020-06-30 2020-09-18 连云港杰瑞电子有限公司 Boost circuit with fixed voltage difference

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112709A (en) * 1982-12-20 1984-06-29 Toshiba Corp Current mirror circuit
JPS6198006A (en) * 1984-10-18 1986-05-16 Victor Co Of Japan Ltd Current mirror circuit
JPS6218807A (en) * 1985-07-17 1987-01-27 Toshiba Corp Current mirror circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112709A (en) * 1982-12-20 1984-06-29 Toshiba Corp Current mirror circuit
JPS6198006A (en) * 1984-10-18 1986-05-16 Victor Co Of Japan Ltd Current mirror circuit
JPS6218807A (en) * 1985-07-17 1987-01-27 Toshiba Corp Current mirror circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101099A (en) * 2009-11-04 2011-05-19 Ricoh Co Ltd Voltage current converter circuit
CN111682767A (en) * 2020-06-30 2020-09-18 连云港杰瑞电子有限公司 Boost circuit with fixed voltage difference

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