JPH01128140A - Interruption request control circuit - Google Patents

Abstract

PURPOSE:To average the acceptance of requests to stabilize the overall working of a system and also to improve the throughput by excluding the already accepted ones out of plural interruption requests and selecting the unprocessed requests with preference. CONSTITUTION:An input register 31 receives an interruption sample signal from the host side and fetches plural interruption request signals 33 supplied from outside to hold them as the input interruption signals 34. An unaccepted request-priority output circuit 35 supplies the signals 34 and an accepted interruption request signal 36 received from an accepted request generating circuit 45 and delivers an unaccepted interruption request signal 37 to show that the interruption request is not accepted yet at the host side. A priority encoder 41 supplies the signal 37 to encode it according to the priority order set internally and delivers an unaccepted interruption request code 42. A decoder 43 decodes the code 42 and delivers an interruption request signal 44. An output register 52 supplies the signal 44 and receives an interruption strobe signal 53 from the host side to deliver it to the host side as an output interruption request signal 54.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control circuit used in a real-time processing system, and more particularly to an interrupt processing control circuit that preferentially selects unprocessed requests.

[Conventional technology]

One of the methods for making advanced use of computers is a real-time processing system that executes multiple independent processing requests in real time. In this real-time processing system, these independent processing requests are often detected by interrupt signals and executed as interrupt processing. Generally, these multiple processing requests occur asynchronously with each other, so it is possible that multiple processing requests occur simultaneously. Therefore, in this case, a means for determining which processing request to execute first is required.

Conventionally, there has been an interrupt control circuit that does this. In many of these interrupt control circuits, a fixed priority is given to each processing request, and the processing to be executed is determined according to this priority. In some cases, this priority order was changed at regular intervals during system operation.

FIG. 4 is a block diagram showing an example of a conventional interrupt control circuit when the number of interrupt channels is four.

First, each component in the figure will be briefly explained. The input register 11 is a 4-bit latch that receives the interrupt sampling signal 12 from the host system, receives four peripheral interrupt request signals 13 supplied from peripheral I10 devices, etc., and holds them as input interrupt request signals 14. It is a circuit. The priority encoder 15 is a 4-bit encoder that inputs the input interrupt request signal 14, encodes it according to an internally set priority order, and outputs an interrupt request code 16.

The decoder 17 is a 4-bit decoder that inputs the interrupt request code 16, decodes it, and outputs an interrupt request signal 18. The output register 19 is a 4-bit latch circuit that inputs the interrupt request signal 18 and receives an interrupt strobe signal 20 from the host system to output it as an output interrupt request signal 21 to the host system.

Next, the operation of the conventional interrupt control circuit will be explained based on this diagram. First, when the host system outputs the interrupt sampling signal 12, the input register 11 receives this and takes in the four peripheral interrupt request signals 13 supplied from peripheral ■/○ devices, etc. The output is held as 14. When the priority encoder 15 receives this input interrupt request signal 14, it encodes the input interrupt request signal 14 according to an internally set priority order and generates an interrupt request code 1.
Outputs 6. Subsequently, the decoder 17 receives the interrupt request code 16, decodes it, and outputs an interrupt request signal 18 indicating the channel number of the interrupt to be permitted.

FIG. 5 shows the relationship between several input interrupt request signals 13, interrupt request codes 16, and interrupt request signals 18 when the priorities of interrupt requests are increased in order of channel number in the priority encoder 15. It is expressed. In this figure, when two or more interrupt requests occur simultaneously for four channels, the request with the larger channel number always appears in the output result.

Next, when the output register 19 receives this interrupt request signal 18, the strobe signal 20 is supplied from the host system.
In response, an output interrupt request signal 21 is given to the host system. This allows interrupt requests to be distributed to host systems based on a fixed priority order.

[Problem that the invention seeks to solve]

By the way, in the conventional interrupt request control circuit described above, the priority order for individual processing requests is fixed, so high-level requests are accepted frequently, but low-level requests are accepted less frequently, and as a result, lower-level requests are accepted less frequently. Throughput for processing has decreased. Particularly when there are multiple processing requests with the same transfer speed, a disparity arises between requests that should be treated equally, and the operation of the entire system becomes unstable. In this way, when the throughput on the low-order side is greatly reduced, it causes fatal errors such as data loss in the peripheral devices controlled by these devices. Furthermore, even if the priorities are exchanged at regular cycles during system operation, the above-mentioned problem is not solved when looking at the cycle period (2), which is insufficient.

Therefore, an object of the present invention is to select an unprocessed request preferentially when deciding which processing request to execute from among a plurality of processing requests, instead of making this decision based on a fixed priority order for these processing requests. By doing so, it is an object of the present invention to provide an interrupt request control circuit that averages out the acceptance of requests as a whole.

[Means for solving problems]

In the interrupt request control circuit of the present invention, an interrupt accepted disk is provided to hold the interrupt processing signals that have already been accepted by the previous interrupt acceptance among the plurality of interrupt processing signals registered by the interrupt sampling signal. .

Then, from the plurality of registered interrupt processing signals, those that have been accepted and held in the disk are excluded, and one of the remaining interrupt processing signals to be newly executed is determined.

This allows the acceptance of interrupt requests to be averaged, making it possible to stabilize the operation of the entire system and at the same time increase its throughput.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

In this embodiment, in order to simplify the explanation, an interrupt request control circuit will be described when the number of interrupt channels is four. The basic operation is the same for multiple channels of four or more channels.

FIG. 1 is a block diagram showing an example of a four-channel interrupt request control circuit. First, each component in the figure will be briefly explained. The input register 31 receives an interrupt sampling signal 32 from the host system to
This is a 4-bit latch circuit that takes in four peripheral interrupt request signals 33 supplied from 10 devices and holds them as input interrupt request signals 34. The unaccepted request priority output circuit 35 outputs an input interrupt request signal 34 output from the input register 31 and a received interrupt request signal 36 indicating which of the input interrupt request signals 34 has already been accepted by the host system. This circuit outputs an unaccepted interrupt request signal 37 indicating that the host system has not accepted the input interrupt request signal 34 yet. This unaccepted request priority output circuit 35 is composed of a first AND circuit 38, a first OR circuit 39, and a first switch 40.

The priority encoder 41 receives the unaccepted interrupt request signal 3.
This is a 4-bit encoder that inputs a code 42, encodes it according to an internally set priority order, and outputs an unaccepted interrupt request code 42. The decoder 43 is a 4-bit decoder that inputs the unaccepted interrupt request code 42, decodes it, and outputs an interrupt request signal 44. The accepted request signal generation circuit 45 is a circuit that receives this interrupt request signal 44 and generates the received interrupt request signal 36 based on it.
Second AND circuit 46 and exclusive OR circuit 4
7, an inverter 48, a second OR circuit 49, a second switch 50, and a register 51. The output register 52 is a 4-bit latch circuit that receives an interrupt request signal 44 and receives an interrupt strobe signal 53 from the host system, and outputs this as an output interrupt request signal 54 to the host system.

The following will explain the case where '1001' (that is, there are interrupt requests on channels 4 and 1 and there are no interrupt requests on channels 3 and 2) is supplied as the peripheral interrupt request signal.

FIG. 2 is a diagram showing the relationship between each signal that changes as the internal operation of the interrupt request control circuit progresses at this time.

Therefore, the operation of the interrupt request control circuit will be explained based on FIGS. 1 and 2. First, in the interrupt request control circuit, when the power is turned on, the reset signal 61 becomes active, thereby resetting the register 51. At this time, register 51
is the received interrupt request signal 36 with its initial value "'111".
1" (step ■). Next, when the host system outputs the interrupt sampling signal 32, the input register 31 receives this and outputs four peripheral interrupt request signals 33 supplied from peripheral I10 devices, etc. is fetched and output and held as the input interrupt request signal 34. At this time, the value of the input interrupt request signal 34 is '1001' (step ■). The first AND circuit 38 receives this input interrupt request signal 3.
4 and the received interrupt request signal 36 are input, masking those that have already been accepted by the host system among the input interrupt request signals 34, and removing these signals as the unaccepted signal 62.
This is what is output as. At this time, the value of the unaccepted signal 62 is "1001" (step ■). The first OR circuit 39 inputs the unreceived signal 62 and outputs "1" as the first switching signal 63 if there is an unreceived signal among them, and otherwise outputs "0". Yes. In this case,
Since the unreceived signal 62 includes an unreceived signal, 1'' is output as the first switching signal 63.

The first switching device 40 inputs the first switching signal 63, and if this is 1'', the input interrupt request signal 34 and the unaccepted signal 62 are input.
Select the unaccepted signal 62 from among them, select the input interrupt request signal 34 if "o", and receive the strobe signal 53 from the host system to output this selection result as the unaccepted interrupt request signal 37. Output. At this time, the first switch 40 selects the unreceived signal 62. Subsequently, when the host system outputs the strobe signal 53, the first switch 40 outputs the unaccepted interrupt request signal 37.

At this time, the value of the unacknowledged interrupt request signal 37 is '1001'' (step ■).When the priority encoder 41 receives this unacknowledged interrupt request signal 37, it encodes it according to the priority set internally. The interrupt request code 42 is output. In this case, the priority encoder 41 increases the priority of the interrupt requests in descending order of channel number. Therefore, at this time, the interrupt request code 42 is output.
The value of is 4''' (channel 4) (step ■).

Subsequently, the decoder 43 receives and decodes the interrupt request code 42, and outputs an interrupt request signal 44 indicating the channel number of the interrupt to be permitted. At this time, the value of the interrupt request signal 44 is '1000' (step ■).Next, when the output register 52 receives this interrupt request signal 44, it receives the strobe signal 53 and outputs the output interrupt request signal 54. The output is output to the host system. At this time, the value of the output interrupt request signal 54 is '1000' (step ■). When the host system receives this, it will execute the corresponding interrupt processing.

On the other hand, the second AND circuit 45 inputs the interrupt request signal 44 and the accepted interrupt request signal 36 and calculates the logical sum thereof. At this time, the output of the second AND circuit 46 is '1000'
It is. Further, the exclusive OR circuit 47 inputs the output of the second AND circuit 46 and the accepted interrupt request signal 36, and calculates the exclusive OR of these. At this time, the output of the exclusive child circuit 47 is "0111".

The inverter 48 inputs the output of the exclusive OR circuit 47 and inverts the logic thereof. At this time, the output of the inverter 48 is '1000'.The second OR circuit 49 inputs the output of the exclusive OR circuit 47, calculates the logical sum of these, and outputs the second switching signal 64. At this time, the value of the second switching signal 64 is "1'".The second switching device 50 inputs the second switching signal 64, and if it is "o", the exclusive OR circuit 47 The output of the inverter 48 is selected from among the output of The selection result is output.At this time, the second switch 50 selects the output of the exclusive OR circuit 47, so the output is '0111'.

The register 51 inputs the output of the second switch 50, and upon receiving the strobe signal 53 from the host system, outputs it as an accepted interrupt request signal 36. At this time, the output of the accepted interrupt request signal 36 is "0111"
” (step ■). As a result, the interrupt request control circuit completes the cycle of accepting requests for channel 4, and
Then, a cycle of request reception for channel 1 is started.

In the cycle of request acceptance for channel 1, the value of the input interrupt request signal 34 is '1001'' (step ■).The first AND circuit 38 inputs this input interrupt request signal 34 and the accepted interrupt request signal 36. input and output “0001” as the unreceived signal 62 (step C)
. The first OR circuit 39 inputs the unreceived signal 62 and outputs the signal ``P1''' as the first switching signal 63.The first switch 40 inputs the first switching signal 63 and outputs the input interrupt request. The unaccepted signal 62 is selected from the signal 34 and the unaccepted signal 62. Then, when the host system outputs the strobe signal 53, the first switch 40 outputs '0001' as the unaccepted interrupt request signal 37. (Step ■). The priority encoder 41 receives this unaccepted interrupt request signal 37.
When received, the decoder 43 encodes this and outputs '1' (channel 1) as the interrupt request code 42 (step 0).Next, the decoder 43 receives this interrupt request code 42, decodes it, and issues an interrupt. '00 as request signal 44
01'" (step 0). Next, when the output register 52 receives this interrupt request signal 44, it receives the strobe signal 53 and outputs "OO0" as the output interrupt request signal 54.
1'' to the host system (step ■). Upon receiving this, the host system executes the corresponding interrupt process.

On the other hand, the AND circuit 46 of the second option inputs the interrupt request signal 44 and the received interrupt request signal 36, and performs the logical sum of these "OO0".
The register IJ logical OR circuit 47 inputs the output of the second AND circuit 46 and the received interrupt request signal 36, and performs an exclusive OR of these signals.
The inverter 48 inputs the output of the exclusive OR circuit 47 and outputs the logical inversion value of this.
The second OR circuit 49 inputs the output of the exclusive OR circuit 47, takes the logical sum, and outputs 1'' as the second switching signal 64.

The second switch 50 receives the second switching signal 64 and selects the output of the exclusive OR circuit 47 from among the output of the exclusive OR circuit 47 and the output of the impark 48 . Then the host system sends the strobe signal 53
, the second switch 50 outputs "01" as the selection value.
10" (step ■). The register 51 inputs the output of the second switch 50, and also receives the strobe signal 53 from the host system, and outputs 'Ol 10' as the received interrupt request signal 36. (Step ■). This causes the interrupt request control circuit to
The cycle of accepting requests for is completed.

In the example described above, since the peripheral interrupt request signal 33 included interrupt requests for channels 4 and 1, two cycles were required to accept all requests. Naturally, even if the peripheral interrupt request signal 33 is other than this, its basic operation is the same as that described above, except that the number of cycles for request acceptance is different.

FIG. 3 is an explanatory diagram showing the relationship between each signal when some signals other than '1001' used in the above explanation are used as the peripheral interrupt request signal 33. The respective results obtained can be easily derived by replacing the value of the peripheral interrupt request signal 33 in the above explanatory text with the corresponding value, so the explanation thereof will be omitted.

〔Effect of the invention〕

As explained above, in the interrupt request control circuit of the present invention, the accepted request signal generation circuit uses the accepted request signal generation circuit to detect which interrupt request signals have already been accepted by the previous interrupt reception among the plurality of interrupt request signals registered by the interrupt sampling signal. It is now possible to keep the same items. Then, from among the multiple interrupt request signals registered by the unaccepted request priority output circuit, those held in this accepted request signal generation circuit are eliminated, and one of the remaining interrupt processing signals to be newly executed is selected. I tried to decide.

This has the effect of averaging the acceptance of interrupt requests, stabilizing the operation of the entire system, and increasing its throughput.

[Brief explanation of the drawing]

1 and 2 are for explaining one embodiment of the present invention. Of these, FIG. 1 is a block diagram showing an example of an interrupt request control circuit, and FIG. 2 is a block diagram showing an example of an interrupt request control circuit. An explanatory diagram showing the relationship between each signal when there is an interrupt request on channel 4 and channel 1. FIG. 3 is an explanatory diagram showing the relationship between each signal for several peripheral interrupt request signals. , FIG. 4 and FIG. 5 are for explaining the conventional interrupt request control circuit, of which FIG. 4 is a block diagram showing an example of the conventional interrupt request control circuit, and FIG. 5 is a block diagram showing an example of the conventional interrupt request control circuit. FIG. 2 is an explanatory diagram showing the relationship between signals in a conventional interrupt request control circuit. 31...Input register, 34...Input interrupt request signal, 35...Unaccepted request priority output circuit, 36...
... Received interrupt request signal, 37 ... Unaccepted interrupt request signal, 38 ... First AND circuit, 39 ... First OR circuit, 40...First switch, 41...Priority encoder, 42...
...Unaccepted interrupt request code, 43...Decoder, 44...Interrupt request signal, 45...Accepted request generation circuit, 46...・
・Second AND circuit, 47...Exclusive OR circuit, 48.
... Inverter, 49 ... Second OR circuit, 50 ... Second switch, 51 ... Register, 52 ... Output Register, 54...Output interrupt request signal.

Claims (1)

[Scope of Claims] An input register that receives a plurality of interrupt request signals supplied from the outside by receiving an interrupt sampling signal, and holds the signals as input interrupt request signals; and the input register that is output from the input register. Inputs an interrupt request signal and an accepted interrupt request signal indicating which input interrupt request signals have already been accepted by the host system, and inputs an accepted interrupt request signal indicating which input interrupt request signals have not yet been accepted by the host system. an unaccepted request priority output circuit that outputs an unaccepted interrupt request signal indicating that the unaccepted interrupt request has occurred; an encoder that outputs the unacknowledged interrupt request code; a decoder that inputs the unacknowledged interrupt request code, decodes it, and outputs an interrupt request signal; and a decoder that inputs the interrupt request signal and generates the accepted interrupt request signal based on it; and an output register that inputs the interrupt request signal and receives an interrupt strobe signal to output the received request signal to the host system as an output interrupt request signal. interrupt request control circuit.