JPH01126742A - Logical simulation device - Google Patents

Abstract

PURPOSE:To simplify the constitution of an evaluating means and to simultaneously execute computation to obtain output data and the decision of a logical type by independently providing the evaluating means which corresponds to the logical type of a logical gate concerning the respective logical types. CONSTITUTION:An input impressing means 2 simultaneously impresses the input data 2-a of the logical gate which computes the output data to evaluating means 1-N. The evaluating means 1-N compute the output data according to the impressed input data and output the data. An output selecting means 3 decides an input 3-a which instructs the logical type of the logical gate from the output data of the evaluating means 1-N. The output data of said evaluating means are selected and outputted to a 3-b. In such a case, since the computation of the output data in the evaluating means 1-N and the decision of the logical type can be simultaneously executed, the computation can be executed at high speed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a logic simulation device.

A conventional technical logic simulation device is a device that performs a logic simulator 2 transformation that simulates what data appears at the output when certain input data is applied to a logic circuit. When performing this logic simulation, it is necessary to calculate the output data of each logic gate constituting the logic circuit from the data applied to its input.

This calculation is one of the most important processes in performing logical simulation, and requires high speed.

Conventionally, the process of calculating the output data of the logic gate described above uses an evaluation means capable of performing the above calculations for logic gates of multiple logic types, provides the logic type of the logic gate and input data, and then calculates the output data of the logic gate. The common method was to determine the logical type given, select the corresponding logical function, and calculate output data from input data.

Problems to be Solved by the Invention The conventional evaluation means described above has to handle multiple logical types, resulting in a complex configuration, and also requires time to determine the logical type, resulting in problems in terms of power and speed. But it was a disadvantage.

Means for Solving the Problems The present invention has been made in view of the problems of the conventional logic simulation three-page device described above, and the present invention has been made in view of the problems of the conventional logic simulation three-page device. a plurality of evaluation means that can operate simultaneously to calculate an output value of the logic gate from an input value; an input application stage that applies the input value of the logic gate to the plurality of evaluation means; and a calculation performed by the plurality of evaluation means. and an output selection means for selecting an output value calculated by the evaluation means corresponding to the logic type of the logic gate from among the output values calculated by the logic gate.

Function: As described above, the present invention is provided with evaluation means corresponding to the logic type of the logic gate independently for each logic type, and therefore the configuration of each evaluation means is easy.
By simultaneously applying input data to multiple evaluation means and selecting the necessary output data from the output data of these evaluation means, calculations to obtain output data and logical type determination can be performed at the same time, resulting in high-speed processing. Calculations become possible.

Embodiment FIG. 1 is a block diagram showing an evaluation section for calculating output data of a logic gate of a logic simulation apparatus according to the present invention. Here, 1-1 to 1-N are evaluation means 1, respectively.
~Evaluation means N, 2 is input application means, and 3 is output selection means.

Evaluation means 1 to evaluation means N are for obtaining output data of logic gates of different logic types, and are preferably provided for all logic types necessary for performing logic simulation. However, some of the evaluation means 1 to N may calculate the outputs of logic gates of a plurality of logic types.

The input applying means 2 simultaneously applies input data 2-a of the logic gate whose output data is to be calculated to the evaluation means 1 to evaluation means N.

Evaluation means 1 to N calculate output data according to the applied input data, but evaluation means that do not correspond to the logic type of the logic gate whose output data is to be calculated will output incorrect output data.

The six-vane output selection means 3 receives an input 3- which indicates the logic type of the logic gate from the output data of the evaluation means 1 to evaluation means N.
Determine a and select the output data of the applicable evaluation means 3
-Output to b.

Here, the calculation of output data in evaluation means 1 to evaluation means N and the determination of the logical type for selecting the output of the corresponding evaluation means by input 3-a indicating the logical type are as follows:
The logical type determination can be done at the same time or first.

Moreover, evaluation means 1 to evaluation means N are simply for calculating output data from input data, and can be configured extremely easily.

Effects of the Invention As described above, the present invention allows an evaluation section for determining output data of a logic gate to be configured to operate easily and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a logic simulation device according to the present invention. 1-1 to 1-N...Evaluation means, 1 to evaluation means N
, 6A-J2... Input application means, 3... Output selection means.

Claims (1)

[Claims] a plurality of evaluation means capable of simultaneous operation for calculating an output value of the logic gate from an input value of the logic gate corresponding to the logic type of the logic gate constituting the logic circuit; An input application stage for applying an input value, and an output selection means for selecting an output value calculated by the evaluation means corresponding to the logic type of the logic gate from among the output values calculated by the plurality of evaluation means. A logic simulation device characterized by: