SU993204A1 - Multi-variable function identifier - Google Patents

Description

one

The invention relates to technical cybernetics and, in particular, to devices for identifying and controlling complex dynamic objects.

A known identification system comprising a random trial step generator, actuators, and a unit for determining the quality increment sign of identification associated with a command unit whose outputs are connected to a random trial generator L1 J The disadvantage of this system is low accuracy.

The closest in technical essence to the present invention is an identifier containing random trial step generators, an increment sign determining unit associated with a command block, the output of which is connected to the reverse Z block.

The disadvantage of the identifier is low accuracy, since the generators of random test steps for each desired parameter work independently of each other and form random increments to each parameter of the approximating function if the previous step was successful, i.e. led to an improvement in the identification quality score. With convex smooth quality functionals, when the initial value of the vector of the sought parameters is located far from the optimum, an identifier is more effective in which the increment to the vector of parameters at the current step is preserved if the identification quality improves in the previous step.

The purpose of the invention is to improve the accuracy of the identifier.

Claims (1)

To achieve the goal, an identifier containing serially connected input blocks of variables of the identified function, block of co-controlled resistors, adder is a block of identification quality identification, a block of identification quality increment identification, the second input of which is connected to the input of the variable values input block of the identified function of the connected - eye output to the second input of the unit for evaluating the quality of identification, a block of reverse binary counters is entered, a ternary estimator is clock th generator number of test steps, an EXCLUSIVE OR element, series-connected block of EXCLUSIVE OR elements, first block of NAND elements and second block of elements sequentially connected inverter first element I. first and second delay elements, OR element, second AND element connected by the output to the second inputs of the first and second blocks of elements NAND. the third inputs of which are connected to the first outputs of the ternary counter, connected by second outputs to the first inputs of the block EXCLUSIVE IL, the second inputs of which are connected to the output of the EXCLUSIVE OR element connected to the first and second delays and the inverter whose input is connected with the output of the unit for determining the sign of the increment of identification quality and the first input of the counter of the number of test steps, the output of which is connected to the second input of the second element AND, and the second input to input the ternary counter and the output of the first delay element, the output of the so-called generator is connected to the second inputs of the first element AND, the OR element and to the inputs of the variable value input block of the identified function, the outputs, the first and second inputs of the reversible binary counter are connected respectively to the second inputs of the block code resistors to the first inputs and outputs of the second block of NAND elements. FIG. 1 shows a general identifier diagram block; in fig. 2 is a diagram of a ternary counter, in FIG. 3 and k are time diagrams of device operation. The identifier contains a block 1 for inputting the variables of the identified function, block 2 for code-controlled resistors, adder 3, block i for evaluating the quality of identification, block 5 for determining the sign of increment of identification qualities, block 6 for reversible binary counters, ternary counter 7, clock generator 8, counter 9 numbers of test steps, EXCLUSIVE OR 10 element, block 11 of elements EXCLUSIVE OR, first block 12 AND-NOT elements, second block 13 AND elements - NO, inverter 14, first element 15, first element 1b of delay, second element 17 of delay and, the element OR 18, the second element AND 19 signals 20-29. The source data for the identifier operation is a sequence of argument values, X and corresponding to them, and the values of the output variable of the identified function,,. , ,), given in the form of a table j 1 - 14 i X ... X nw U. U. -. -Yt l. The NUMBER of arguments to the function being identified; n is the number of measurements of variables on the basis of which identification is carried out; i is the number of current measurement. The task of identification is to determine such coefficient values, and approximations a function and -f.4 for which the deviation rate cf (a, a2, .., --IN-v (a, aa, -, a,) ll, (3) calculated for all variable measurements, takes the minimum value. The norm type (3) determines the specific implementation of the identification quality evaluation unit k. In the device the values of the arguments X-, x, ..., ... x are formed on the first input () loca 1 inputting the values of the variable identifiers function, the second output of which generates values of the output variable of the student of the desired coefficients a, a., arti are formed at the outputs of block 6 of reversible binary counters, is fed to the first inputs of block 2 of controlled resistors, where they are multiplied by the corresponding values of arguments, x ,, X2, ..., xj ,, -. At the output 5 of the adder 3, the inputs of the block 2 of resistors are connected, the values of y are formed. approximating function (2) and at the output of the block C of evaluation of the quality of identification, the values of the norm (3) are formed, which characterizes the accuracy of identification at the values of the coefficients a, a, a. . . . The device implements a search identification algorithm with a repetition of the UDZ step, in which the increment of the value of the coefficient vector Yes, contained in the triple counter 7, is saved and returned to the previous state in the event of an unsuccessful step. A variant of the t-bit ternary counter 7 circuit is shown in Fig. 2. Each of its bits contains two successively connected D-flip-flops, where, to exclude the C, O, and B1 state, the initial setup signal and the three-way counter 7 are fed to 5 - the input of the second trigger, whose inverse output is connected to the R input of the first trigger, which is assembled according to the trigger scheme with a counting input. Each j-th bit of the ternary counter 7 generates the following combinations of output signals: corresponds to the increment of the coefficient is a; П J 2) and 1, J С, which corresponds to the increment of the coefficient & aj, 3) U2 1, UT corresponds to the increment of the coefficient. Thus, the signal U is interpreted as a modulus of the increment of the coefficient, and the signal C toK of this increment. The block of 11 elements EXCLUSIVE OR and the blocks 12-13 of elements. AND-NOT consistently implement the expressions,) UaoU (2.6 4 (ar 4 (6)) At CB zfe, control signals at the corresponding outputs of blocks 12-13 of the NAND, element EXCLUSIVE OR 10 and the second element AND 19- Depending on the state of the ternary counter 7 and in accordance with Cta), (4b) a block of 11 elements EXCLUSIVE OR or blocks 12-13 of the elements AND-NOT produce the following combinations of control signals: which sub-codeodule 993204 1) Y., Z, r1 for storing the values of the coefficients in block 6 of the reverse binary counters Cove, 2), - for the arithmetic summing increments of the coefficients with corresponding values of the content block reverse binary counters 6, 3), I. - for arithmetic subtracting increments from the corresponding coefficients anacheny 6 reversible binary counter content block. The identifier works as follows. The identification step records the value of the vector of the desired coefficients 3 (, a,) of the function (.2). The values are sequentially fed to the first inputs of the block 2 of the code-controlled resistors and to the second input of the identification quality assessment unit 4. columns of the source data table (1 from block 1, i 1) A sequence of signals is formed at the output of adder 3. After supplying the values of the last n-column of the table (O block 4, identification quality assessment in accordance with (3) generates a signal characterizing the quality estimate identification at the K th stepO (ac). After this, the clock generator 8 generates a control signal 27 which terminates the cycle of issuing the values of the table (1) from block 1, sets its 8 initial state and starts the block 5 for determining the sign of the increment quality Identification Va. In this block, the signal characterizing the assessment of the quality of identification at the Kth step is compared with the similar signal obtained at the (K-1) th step with the value of the coefficient vector A. There can be two outcomes: (i) (f) (b.}, 5 (L) cf (aK) / cr (aKH) -5 (L The time diagram shown in Fig. 3 corresponds to the outcome (5a) when the identification quality is better. In this case, the increment sign unit 5 identification signal, a signal 28, equal to 1, which passes through the inverter 14, is converted into O, closes the first element 15 and arrives at the second input of the EXCLUSIVE OR element 10. At the same time, at its first input there is a signal O, so that at its output there appears a signal 25, equal to O, which enters the second inputs of the block 11 elements EXCLUSIVE IL At the same time the signal 27 from the output of the so-called generator 8, equal to 1, comes through the element OR 18, the open second element AND 19, and enters the second inputs of the blocks 12-13 of AND-NOT elements. The values of signals 25 and 2b thus generated form control signals for the algebraic summation of the contents of the corresponding bits of the tertiary counter 7 from the contained block 6 of reversible binary counters, i.e. to go to the new value of the coefficient vector vector (a., A, ... a) while maintaining the search direction defined in the previous step, the timing diagram shown in FIG. corresponds to the outcome (55) when the quality of identification is not improved. In this case, the block 5 for determining the quality mark of the identification quality generates a signal 28 equal to O, which, passing through inverter 1, is converted to 1, opens the first element 15 and enters the second input of the element EXCLUSIVE OR 10, causing a single signal at its output 25. Simultaneously, a single signal 27 from the output of the clock generator 8 passes through the element OR 18, the open second element AND 19 and enters the second inputs of the blocks 12 and 13 of the AND-NOT elements. The values of signals 25 and 2b thus formed form control signals for algebraically subtracting the contents of the corresponding bits of the ternary counter 7 from the contents of block 6 of reversible binary counters, i.e. to return to the value of the vector of coefficients, a, obtained in step K-1. After a time interval g, i.e. at time t t -Kt, the single signal 27 passes through the open first element 15 and the first delay element 1b enters the counting input 29 of the ternary counter 7, causing a change in its content, i.e. transition to a new direction of search coefficients. At the moment of time, a significant signal appears at the output of the second delay element 17 and enters the first input of the EXCLUSIVE OR 10 element, causing a single signal 25 at its output, as well as through the OR TV element and the open second And 13 element to the bus 26. Formed over the time interval (t, t), the values of signals 25 and 26 allow to perform algebraic summation of the new contents of the corresponding bits of the ternary counter 7 with the contents of block 6 of reversible binary counters, i.e. provide an opportunity to begin the search for the optimal values of the coefficients a, in a new direction. but, " . . If the resulting vector of coefficients a to again leads to an unsuccessful step, the ternary counter 7 again changes the direction of finding the minimum of the criterion (3 in the space of coefficients. If this criterion is not improved, after iterating through all possible directions, the count of the number of test steps is zeroed A zero signal is generated at the output, because each successful step at the first input of the counter 9 of the number of test steps receives a single signal 28 from the output of the increment sign determining unit 5, which causes the recording in counter 9, the number of trial steps of value 3 equal to the number of all possible directions of change of the coefficient vector (a, a,..., Luu,). For each unsuccessful ujare from the output of the second delay element 16, a single signal arrives at the second input of counter 9 of the sample steps, causing its contents to decrease by one. After the directions have been searched, the zero signal at the output of the counter 9 of the number of test steps locks the second element I 19. At output 2b, an O signal is generated, which puts the reversive binary counter block 6 into the storage mode . Moreover, their content corresponds to the optimal values of the desired coefficients a, a, ... a. For which the minimum criteria is reached (3) These values of the coefficients are the result of the identifier. Thus, an increase in the accuracy of the identifier is achieved by implementing the search mode for a minimum of the identification quality criterion 8 factor space, at which the well-chosen search pattern is maintained at each step until the identification quality criterion begins to deteriorate. Multi-variable function identifier containing sequentially connected input unit for variable values of identifiable function, block coding control resistors, adder identification quality evaluation unit, identification quality increment sign determination unit, the second input of which is connected to input variable input unit of the identified function connected by a second output to the second input of an identification quality assessment unit, characterized in that, in order to increase the accuracy the identifier, it contains a block of reversible binary counters, a ternary counter clock generator, a count of the number of test steps, an EXCLUSIVE IL element serially connected block EXCLUSIVE OR, the first block of AND-NOT elements and the second block of AND-NOT elements, sequentially connected inverter, AND , the first and second delay elements, the OR element, the second AND element connected by the output to the second inputs of the first and second blocks of the NAND elements, the third inputs of which are connected to the first outputs of the ternary counter, Connected by the second outputs to the first inputs of an EXCLUSIVE OR block, the second inputs of which are connected to the output of the EXCLUSIVE OR element connected by the first and second inputs respectively to the outputs of the second delay element and inverter, whose input is connected to the output of the identification quality mark increment and the first counter input the number of test steps, the output of which is connected to the second input of the second element I, and the second input to the ternary counter and the output of the first delay element, the output clock generator - connected to the second inputs of the first element AND, the OR element and to the input of the input block of variable values of the identified function, the outputs, the first and second inputs of the reversible binary counter block are connected respectively to the second inputs of the coding control resistors, to the first inputs and outputs of the second block of elements AND-NOT. Sources of information taken into account in the examination 1.US Patent W 3697957, cl. G 05 B 13/02, published 19b7. 2, USSR inventor's certificate 326550, cl. G 05 13/02, 1971 (prototype). .g 27 28 25 to tr 2 J / fug.