JPH01126730A - Stack memory device - Google Patents

Abstract

PURPOSE:To improve a processing speed by efficiently realize stack function with the small quantity of a hardware. CONSTITUTION:When push operation is executed, 1 is added to a stack top counter (ST)30. The value of the ST30 is given to one input of a coinciding circuit 70. To the other input of the coinciding circuit 70, the value of a stack base counter (SB)40 is inputted. When the coinciding circuit 70 detects coincidence, since this shows a condition that the entry of a high speed memory 10 is wholly used. Then, when the push operation is executed in such a condition, a save processing is executed to sweep out the contents of the high speed memory 10 to an external memory 20. At first, the contents of the SB40 are given to the high speed memory 10 as an address and the contents of the address are transferred to the external memory 20. After that, the value of the SB40 is added only by 1. The output of the most significant digit of the SB40 is given through a line 402 to a flip-flop 80. Then, when acarrying occurs, a setting is executed. This evacuating operation is continued until a flip-flop 70 is set.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention efficiently realizes the stack function in a computer with less hardware, thereby increasing processing speed and making it possible to use complex application programs in a wide range of applications. It is for.

(Prior Art) The stack function is a function that temporarily saves the state during computer operation and returns to the saved state when other related operations are completed, and has been frequently used since ancient times. This is a basic function. In general, a stack must be constructed so that it can hold a logically infinite number of entries by stacking multiple states one after another. However, in reality, it is difficult to realize all of this with hardware due to quantitative limitations of hardware. To solve this problem,
Conventionally, this has been achieved by combining a relatively expensive, small amount of high-speed memory with a relatively inexpensive, large-capacity, low-speed memory.

The operation of inputting and outputting data between these two layers of memory is complicated, and has conventionally been realized mainly by software and microprograms.

(Problems to be Solved by the Invention) Stack operations occur very frequently, and the efficiency with which they are realized greatly affects system efficiency. Efficiency is particularly important in the execution of languages such as LISP and PROLOG, which include stack operations as a basic mechanism of the programming language itself. In order to create a state in which an infinite number of logical states can be stored, software and firmware have conventionally been implemented as a basic function of a system, but this has had many problems in terms of efficiency and the limits of system resources. Therefore, many inventions have been made in the past, but when they are implemented using hardware support, the amount of hardware tends to increase in response to complex operations.

More specifically, detection of the timing for swapping between two memory hierarchies and the efficiency of the actual swapping operation are major problems.

An object of the present invention is to provide a stacked memory device that solves these problems.

(Means for Solving the Problems) The present invention includes a high-speed memory for storing power-of-2 entries used as a stack, an external memory for saving stack contents, a stack top counter, and a stack top counter. a base counter, a subtracter A that generates an output obtained by subtracting the contents of the two types of counters by 1, a subtracter B that generates an output obtained by subtracting the contents of the stack base counter by 1; It consists of a matching circuit that compares the contents of the counter and the outputs of the subtracter A and the subtracter B to detect a match, and a flip-flop that is set by a carry signal to the top of the stack base counter. When the coincidence circuit detects that all entries in the memory are filled in a push operation, the contents of the high-speed memory are saved in the external memory until the state of the flip-flop is changed; When the coincidence circuit detects that the contents of the memory are completely empty, the data group at the top of the stack is always stored in the memory by returning to the faster memory than the external memory until the state of the flip-flop is changed. This is a stack memory characterized by being held in high-speed memory.

(Function) The stack function retains the state at a certain point in time, then successively retains the state at subsequent points in time, and when accessed, outputs the most recently held state (Last In First Out).
This is realized using memory (LIFO memory). Here, the former is called a push operation, and the latter is called a pop operation. Logically, the button operation should be performed an infinite number of times, but there is a limit to the amount of hardware available. In order to efficiently perform stack operations, a small amount of fast but expensive memory is combined with a slow but cheap memory that can be increased in capacity.

In other words, since the most recently bushed state has the highest possibility of being accessed, it is desirable to store it in the fastest possible memory. Here, the push operation to the fast memory continues, and when the fast memory is overflowed, the oldest state is flushed to the slow memory,
High speed memory must be cleared for subsequent bush operations. The timing of this content replacement and speeding up of the replacement process are important.

The stack memory of the present invention realizes the stack operation by a stack base counter pointing to the base of the high speed memory and a stack top counter pointing to the address of the memory for push button operation, and also checks whether the high speed memory overflows. This is to detect the content using hardware and realize high-speed content replacement operation.

(Example) Hereinafter, an example of the stack memory of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 10 is a high-speed memory that stores entries of powers of 2 used as a stack, 20 is an external memory, and 30
is a stack top counter (abbreviated as ST), 40 is a stack base counter (abbreviated as SB), 50 is a subtracter A160, subtracter B170 is a matching circuit, 80 is a flip-flop, 11, 51, 71.72 is a selector. It is.

For simplicity, an example will be described in which the number of entries (addresses) in the high-speed memory 10 is four. In the initial state, 5T30 and 5B40 are both set to 00'' and flip-flop 80 is reset.

(Bush operation) When a push button operation is performed, each selector is set to the following state. That is, the input of selector 11 is line 3
01, the line 301 is selected as the input to the selector 71, and the line 601 is selected as the input to the selector 72. The button operation in the initial state is such that the contents of 5T30 are addressed via line 301, selector 11, and line 111, and the contents of 5T30 are addressed to “00” of high-speed memory 10.
This is achieved by writing the contents of a data register (not shown) to address 5T30, and 1 is added to 5T30 after this writing is completed. That is, the output of 5T30 becomes "01" at the end of writing, and preparations are made for the next bushing operation. This value is line 301, selector 71, line 7
11 as one input of the matching circuit 70. The other input of the -number circuit 70 is the value obtained by subtracting 1 from 5B40, that is, 11°.The -number circuit does not detect a match at this point, so no further processing is performed.

Does not cause the above behavior.

When the bushing operation is subsequently performed, the same operation as described above is executed until the coincidence circuit 70 detects a coincidence.

(Saving process) 5T30 and 5B4 when the matching circuit 70 detects a match
Both values of 0 are 'oo', indicating that all entries in the high-speed memory 10 are used.If a push operation is performed in this state, the contents of the high-speed memory 10 are flushed to the external memory 20. Processing is required, and the states of each selector at this time are as follows: Input to selector 11 is line 401, input to selector 51 is line 301, input to selector 71 is line 501, selector 7 is input to line 401.
For input No. 2, line 401 is selected. High speed memory 10
A saving process to the external memory 20 is performed. First, 8B
The contents of 40 are given to the high speed memory 10 as an address, and after the contents of address "00'" are transferred to the external memory 20, the value of 5B40 is incremented by 1. The most significant digit output of 5B40 is provided to flip-flop 80 via line 402 and is set when a carry occurs. The above operation is performed until this flip-flop 80 is set. In other words, half the amount of high-speed memory 10 is saved. 5B at the time the final entry has been saved
The content of 40 is "10". Therefore, the subsequent stack base becomes the top position of the second half of the high speed memory 10. When the high-speed memory 10 becomes full again due to further push operation from this state, the flip-flop 80
is set, the second half of the high-speed memory 10 is saved and the stack base is updated to address 110011 again. The end of the subsequent return process is when the flip-flop 80 is reset by the most significant carry of 5B40. Also, from the high-speed memory 10 to the external memory 20
The fact that the evacuation has been performed is stored by an external device (not shown).

(Pop operation) The state of each selector when a pop operation is performed is as follows. That is, the input of the selector 11 is the line 50
1. The line 301 is selected as the input to the selector 51, the line 501 is selected as the input to the selector 71, and the line 401 is selected as the input to the -selector 72. Since 5T30 indicates the address of the high speed memory 10 to be bushed next, the subtracter 50 reads the previous address by 1 in the pop operation. When this reading is completed, 8T30 is subtracted by 1. - 5 for number circuit 70
The value of B40 and the value obtained by subtracting 1 from the value of 5T30 are input. The pop operation is realized by repeating the above operations until the matching circuit 70 detects a match.

(Return Process) The states of each selector when the return process is performed are as follows. That is, the input of the selector 11 is the line 501
, the line 401 is selected as the input to the selector 51, the line 301 is selected as the input to the selector 71, and the line 601 is selected as the input to the selector 72. During the pop operation, the matching circuit 70 detects a match when the content of 5B30 is "01" and the content of 8B40 is "
'oo'. Immediately after this, 8T30 is 'oo'.
"", and if a pop operation is performed at this point, the address space 11" is accessed. Here, if a save process was previously performed, a restore process must be performed. The return is performed to address 1111+1, which is obtained by subtracting 1 from 5B40, and when reading is completed, the value of 5B40 is subtracted by 1. This operation is 5B
Flip-flop 80 by the most significant digit of 40
repeats until reset. This operation restores half the contents of high speed memory 10 to high speed memory 10. Note that the recovery process is performed by an external device using the high-speed memory 10.
Needless to say, this is performed only when it is known that the contents of are saved in the external memory 2o.

The contents of the embodiment have all been explained through the explanation of the four types of operations described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 10 is a high-speed memory that stores entries of powers of 2 used as a stack, 20 is an external memory,
30 is a stack top counter, 40 is a stack base counter, 50.60 is a subtracter, 7o is a matching circuit, 80
is a flip-flop, and 11, 51, 71, and 72 are selectors. Juzo Iizuka, Director of the Agency of Industrial Science and Technology

Claims (1)

[Claims] A high-speed memory for storing power-of-2 entries used as a stack, an external memory for saving the stack contents, a stack top counter, a stack base counter, and the contents of the two types of counters are subtracted by 1. a subtracter A that generates an output that is obtained by subtracting the contents of the stack base counter by 1; a subtracter B that generates an output that is obtained by subtracting the contents of the stack base counter by 1; and the contents of the two types of counters and the outputs of the subtracter A and the subtracter B. and a flip-flop that is set by a carry signal to the top of the stack base counter, and in a stack push operation, all the entries in the memory are filled by the matching circuit. the contents of the high-speed memory are evacuated to the external memory until the state of the flip-flop is changed when a stack pop operation is detected, and the contents of the memory are all emptied by the match circuit in a stack pop operation. A stack memory device characterized in that when a problem is detected, the data group at the top of the stack is always held in the high-speed memory by returning to the high-speed memory from the external memory until the state of the flip-flop is changed. .