JPH04262436A - Address conversion buffer circuit - Google Patents

Abstract

PURPOSE:To reduce delay of address conversion action by carrying out the compare/coincidence action of signal groups sequentially in order of earlier determined timing. CONSTITUTION:The address conversion buffer circuit is equipped with the second latch circuit 102 that is divided into a process identification number corresponding tag section 101 constituted by an associative memory circuit for carrying out the compare/coincidence processing of a compare input signals outputted from a process identification number register 106, and into an effective address corresponding tag section 103 constituted by an associative memory circuit for carrying out the compare/coincidence processing of effective addresses in accordance with a compare input signal output from an effective address register 107 and the content of the second latch circuit 102, and that latches a result of the compare/coincidence processing by the process identification number corresponding tag section 101 and that gives a latched result to the effective address corresponding tag section 103. Accordingly, the load capacity of the compare/coincidence output from a CAM circuit corresponding to the signal group whose input is determined latest can be maintained to the minmum.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applied to digital computers. The present invention relates to an address translation buffer circuit that can reduce delays in comparison operations in virtual memory computers.

0002

[Prior Art] Conventionally, an associative memory circuit (hereinafter referred to as CAM)
An address conversion buffer circuit using a tag section (called "tent Addressable Memory") as a tag section is
The input signal input to the tag section is compared with the signal comparison circuit means constituted by one CAM, and the comparison result is sent to the storage circuit (RAM) which constitutes the physical address data section via a comparison match output line. RandomAccess Me
Mory) was used to select a word.

FIG. 3 is a block diagram showing the configuration of a conventional address translation buffer circuit. The operation of the conventional example will be explained with reference to FIG.

[0004] Logical address information consists of a process identification number that identifies each space in the multiple virtual storage space and an effective address to be accessed, and these two signals are stored in a process identification number register 106 and an effective address register 107, respectively. A comparison operation is performed in the logical address tag sections 101' and 103' formed by CAM circuits, and the word corresponding to the entry that matches the tag is stored in the physical address data section 10 formed by RAM circuits.
5 is selected and output as a physical address.

FIG. 4 shows a logical address tag section 101',
The CAM circuit used as 103' is composed of transistors, and the circuit for one entry is shown. Compare match line 126 is precharged according to timing signal 122. When the timing signal 122 is inverted, the contents of the process identification number and effective address stored in the process identification number register 106 and effective address register 107 and the logical address tag section (CAM
If the contents registered in the circuits 101' and 103' are different, the comparison match line 126 is discharged through the discharge line 129. Comparison match line 126 of only entries with matching contents is '1'
is held in the latch circuit 104, and at the next timing, the physical address data section (RAM circuit) 105
A word is selected and its contents are stored in the physical address register 111.

[0006]

[Problems to be Solved by the Invention] In the conventional address conversion buffer circuit described above, since the logical address information of the input signal is compared with a single CAM circuit, the number of bits of the input signal, that is, the bits to be compared, is When the number becomes large,
There is a problem in that the load on the comparison match line becomes heavy and the delay in the comparison operation increases.

When both a process identification number and an effective address are used as comparison inputs, as in the address translation buffer circuit in multiplexed virtual memory described above, the timing of determining the process identification number is generally earlier than the timing of determining the effective address. Although it is early, the comparison matching operation of the CAM circuit starts from the time when the effective address is determined, and the CAM circuit corresponding to the process identification number effective address
The cell will drive a heavily loaded comparison match line connected to it. Therefore, there is a problem in that the delay in the address translation operation becomes large.

[0008] The present invention is intended to solve such problems, and an object of the present invention is to provide a circuit that can reduce delays in address translation operations.

[0009]

[Means for Solving the Problems] The present invention is constituted by an associative memory circuit, and receives a comparison input signal of a process identification number stored in a process identification number register and an effective address stored in an effective address register, and compares and matches. A logical address tag section that performs processing, a first latch circuit that holds the contents of comparison match processing, a physical address data section that includes a RAM circuit that receives a comparison match signal from this latch circuit and selects a word; In an address conversion buffer circuit comprising a physical address register that stores contents selected by the physical address data section, the logical address tag section is an associative memory that performs comparison matching processing of comparison input signals from the process identification number register. an effective address configured by a process identification number corresponding tag section configured by a circuit, and an associative memory circuit that performs a comparison match process of effective addresses according to a comparison input signal from the effective address register and the contents of the second latch circuit; The present invention is characterized by comprising a second latch circuit that is divided into a corresponding tag section and a second latch circuit that latches the comparison matching processing result of the process identification number corresponding tag section and supplies it to the effective address corresponding tag section.

It is preferable to include a base address latch and a displacement latch, and an effective address adder for adding the base address and displacement from the latch to form an effective address and storing the result in the effective address register.

[0011]

[Operation] A CAM circuit is used to configure an address tag section that is divided into logical address designation information that is an input signal for each signal whose confirmation timing is different, and the comparison match output of the CAM circuit corresponding to a group of signals whose confirmation timing is early is as follows. is applied to the input of the comparison match line of the CAM circuit corresponding to the signal group to be finally determined, and the match output line of the CAM circuit corresponding to the signal group to be finally determined is connected to the word selection signal of the RAM circuit that stores the physical address information. do.

[0012] The process identification number is rewritten when a process is switched, and its contents are fixed at the time when address addition is performed. Therefore, it is possible to perform process identification number comparison and matching processing in parallel with address addition, and add the result when performing effective address comparison and matching processing at the next timing.

As a result, the load capacitance of the comparison match output line of the CAM circuit corresponding to the signal group whose input is determined the latest can be kept to a minimum, and after the input signal group having the latest determination timing is determined. The delay until a logical address comparison match output is obtained can be reduced.

[0014]

Embodiments Next, embodiments of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention has a process identification number corresponding tag unit 101 constituted by an associative memory circuit that performs comparison matching processing of a comparison input signal from a process identification number register 106, and a comparison input signal from an effective address register 107. and an effective address corresponding tag section 103 formed of an associative memory circuit that performs effective address comparison matching processing according to the contents of the second latch circuit 102, and the effective address corresponding tag section 103 which performs comparison matching processing results of the process identification number corresponding tag section 101. Latching effective address compatible tag section 10
A second latch circuit 102 is provided.

Furthermore, an effective address corresponding tag section 103
A latch circuit 104 that holds the contents of comparison matching processing by
, a physical address data section 105 constituted by a RAM circuit that receives a comparison match signal from the latch circuit 104 and selects a word; and this physical address data section 1
05, and a base address latch 108.
and a displacement latch 109,
An effective address adder 110 is provided for adding the base address and displacement from this latch to form an effective address and storing the result in an effective address register 107.

The process identification number corresponding tag section 101 and the effective address corresponding tag section 103 are constructed of transistor circuits.

In this embodiment, when the tag part of the address translation circuit is divided into two by the effective address and process identification number that are the result of adding two inputs of logical address input information (for example, the base and displacement of address specification). shows. The process identification number register 106 stores a process identification number, and the effective address register 107 stores an effective address. Effective address register 1
The effective address stored in 07 is the base address latch 108 and the displacement latch 109.
The effective address adder 110 adds the base address and displacement stored in .

Generally, the process identification number is rewritten when a process is switched, and its contents are fixed by the time address addition is performed. Therefore, it is possible to perform process identification number comparison and matching processing in parallel with address addition, and add the result when performing effective address comparison and matching processing at the next timing.

FIG. 2 shows a process identification number corresponding tag section (CAM circuit) 101 and an effective address corresponding tag section (CAM circuit) 103 at the transistor level according to the embodiment of the present invention. Process identification number comparison and matching processing is performed according to the timing signal 121, and the result is held in the latch circuit 102. This value is '0' for entries whose process identification numbers match, and '1' for entries that do not match.

Effective address register 1 at the next timing
07 and the contents of the latch circuit 102, effective address comparison matching processing is performed. At this time, the latch circuit 10
2 holds '1', that is, when the process identification numbers do not match, the transistor 125 is turned on by the comparison match output line 124, and the comparison match line 126 is turned on.
is discharged and the final comparison match output line 127
is '0', indicating that this entry does not match.

When the process identification numbers match, the transistor 125 is off, and when the effective addresses also match, the comparison match output line 127 is held at '1' and the comparison match output line 127 is turned on. Then, the physical address data section (RAM circuit) 105 is accessed and the contents are stored in the physical address register 111.

[0023]

[Effects of the Invention] As explained above, according to the present invention, in an address conversion circuit using a CAM circuit in the tag section, tags corresponding to signal groups having different determination timings are divided among input logical address information. By constructing a CAM circuit and sequentially performing a comparison match operation starting from a group of signals with the earliest confirmation timing, it is possible to keep the load capacitance of the comparison match output line of the CAM circuit corresponding to the signal group whose input is the latest to be confirmed to a minimum. This has the effect of reducing the delay from when the input signal group with the latest determination timing is determined to when a logical address comparison match output is obtained, compared to when the tag section is configured with a single CAM circuit. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a transistor configuration of a CAM circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a conventional example.

FIG. 4 is a diagram showing a conventional CAM circuit with a transistor configuration.

[Explanation of symbols]

101 Process identification number corresponding tag section 101'
, 103' logical address tag section 102, 1
04 Latch circuit 103 Effective address corresponding tag section 105 Physical address data section
(RAM circuit) 106 Process identification number register 107 Effective address register 108
Base address latch 109 Displacement latch 110 Effective address adder 111 Physical address registers 121, 12
2 Timing signals 123, 126
Comparison match lines 124, 127 Comparison match output line 125 Transistor

Claims (2)

[Claims] 1. A logical address tag section configured of an associative memory circuit, which receives a comparison input signal of a process identification number stored in a process identification number register and an effective address stored in an effective address register, and performs a comparison matching process. , a first latch circuit that holds the contents of the comparison match processing, a physical address data section composed of a RAM circuit that receives a comparison match signal from this latch circuit and selects a word, and a word selected by the physical address data section. In an address conversion buffer circuit comprising a physical address register for storing contents, the logical address tag section includes a process identification number configured by an associative memory circuit that performs comparison matching processing of comparison input signals from the process identification number register. divided into a corresponding tag section and an effective address corresponding tag section constituted by an associative memory circuit that performs effective address comparison matching processing according to a comparison input signal from the effective address register and contents of the second latch circuit; An address conversion buffer circuit comprising: a second latch circuit that latches a comparison match processing result of the tag section corresponding to the process identification number and supplies it to the tag section corresponding to the effective address. 2. An effective address adder comprising a base address latch and a displacement latch, and an effective address adder for adding the base address and displacement from the latch to form an effective address and storing the result in the effective address register. Address translation buffer circuit.