JPH01125830A - Grinding of semiconductor wafer - Google Patents
Grinding of semiconductor waferInfo
- Publication number
- JPH01125830A JPH01125830A JP62284867A JP28486787A JPH01125830A JP H01125830 A JPH01125830 A JP H01125830A JP 62284867 A JP62284867 A JP 62284867A JP 28486787 A JP28486787 A JP 28486787A JP H01125830 A JPH01125830 A JP H01125830A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- oxide film
- polishing
- wafer
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005498 polishing Methods 0.000 claims description 27
- 239000004744 fabric Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000010453 quartz Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000007517 polishing process Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体ウェーハの一面側を保持具に嵌合装着
して該半導体ウェーハの他面側を研磨する研磨方法の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a polishing method in which one side of a semiconductor wafer is fitted into a holder and the other side of the semiconductor wafer is polished.
（従来の技術とその問題点）
一般に、半導体ウェーハの研磨方法の一例二゛シて保持
具のプレートに半導体ウェーハの−・面側（非研磨面側
ンを嵌合装着し、その半導体つｆ −ハの他面側（研磨
面側）を研磨装置の定盤表面の研磨布に圧接させて研磨
する研磨方法が知られている。その研磨方法による鏡面
加工は、第３図に示す如く、保持具を構成するプレート
９にフィルム状のクツション材１０を張り合わせ、更に
そのクツション材１０の下面にウェーハ１１の外径より
梢々大径な窓孔１２′を開穿した支持板１２を固着し、
窓孔１２′にウェーハを嵌合装着して研磨加工を行うも
のである。(Prior art and its problems) In general, an example of a method for polishing a semiconductor wafer is to fit and attach the - side (non-polished side) of the semiconductor wafer to the plate of a holder, and then polish the semiconductor wafer. - A polishing method is known in which the other side (polishing surface side) of C is brought into pressure contact with a polishing cloth on the surface plate of a polishing device.Mirror finishing by this polishing method is as shown in Fig. 3. A film-like cushioning material 10 is laminated onto the plate 9 constituting the holder, and a supporting plate 12 having window holes 12' each having a diameter larger than the outer diameter of the wafer 11 is fixed to the lower surface of the cushioning material 10. ,
A wafer is fitted into the window hole 12' and polished.
ところで、研磨加工されるウェーハの非研磨面に傷が付
くのを防止するためプレートにウェーハよりも軟らかい
クツション材が貼着されるが、そのクツション材は両面
粘着テープ等で貼り合せられる時両者間に空気が入るな
どしてクツション材表面の平坦度を出すのが困難となり
、その結果保持されるウェーハに傾きが生じ、それによ
って研磨されたウェーハの厚みが不均一になるといった
不具合を有する。尚、ウェーハを平坦に保持する手段と
しては、硬質体で形成されたプレートそのままの表面に
半導体ウェーハを当接させることが考えられるが、この
場合は硬質体にウェーハが直接当たるため非研磨面に傷
及び研磨材による汚れ等が付き易く、又、プレートへの
脱着の際に当てるなどしてウェーハが破損するなどの問
題点を有する。尚、半導体つ１−ハの非研磨面を保護す
る手段として特開昭６２−５１２２６号公報に記載の発
明が提案されているが、その保護膜は合成樹脂製の保護
材であるため、上述した従来方法のクツション材と保護
膜は類似し、半導体ウェーハに比較して硬度が軟らかい
ため、該ウェーハの平坦度を向上させることが困難であ
るという難点がある。By the way, in order to prevent scratches on the non-polished surface of the wafer being polished, a cushioning material that is softer than the wafer is attached to the plate, but the cushioning material is attached with double-sided adhesive tape or the like for a long time. Air enters the cushioning material, making it difficult to achieve flatness on the surface of the cushioning material.As a result, the wafer held is tilted, which causes problems such as uneven thickness of the polished wafer. Note that one possible way to hold the wafer flat is to bring the semiconductor wafer into contact with the surface of a plate made of a hard material, but in this case, the wafer hits the hard material directly, so the surface is not polished. The wafer is easily scratched and contaminated by abrasive materials, and the wafer can be damaged by contact with the wafer when it is attached to and removed from the plate. Incidentally, as a means for protecting the non-polished surface of the semiconductor layer 1-c, an invention described in JP-A-62-51226 has been proposed, but since the protective film is a protective material made of synthetic resin, the above-mentioned The cushioning material and protective film of the conventional method are similar and have softer hardness than a semiconductor wafer, so it is difficult to improve the flatness of the wafer.
（発明の目的）
この発明は上述した如き従来の事情に鑑み、研磨作業中
に、半導体ウェーハの非研磨面側が傷付いたり汚損する
のを防止すると共に、半導体つ１−ハの平坦度を再現し
て均一な厚さに研磨することが出来る研磨方法を提供す
ることにある。(Object of the Invention) In view of the conventional circumstances as described above, the present invention prevents the non-polished side of a semiconductor wafer from being damaged or contaminated during polishing work, and reproduces the flatness of a semiconductor wafer. An object of the present invention is to provide a polishing method that can polish to a uniform thickness.
（発明の構成）
上記目的を達成Ｊるために本発明が講じた技術的手段は
、半導体ウェーハの非研磨面側を予め酸化膜で被覆し、
研磨加工終了後、前記酸化膜を除去する方法とする。(Structure of the Invention) The technical means taken by the present invention to achieve the above object is to coat the non-polished side of the semiconductor wafer with an oxide film in advance,
After the polishing process is completed, the oxide film is removed.
上記の酸化膜を形成する方法としては、半導体ウェーハ
の基材がシリコン（Ｓｉ）である場合は酸化炉法、Ｃ−
Ｖ−Ｄ法が採用出来、半導体ウェーハの基材がシリコン
以外のＧＧＧ、石英板等である場合はＣ−Ｖ−Ｏ法が採
用される。When the base material of the semiconductor wafer is silicon (Si), the method for forming the above-mentioned oxide film is an oxidation furnace method, a C-
The V-D method can be adopted, and when the base material of the semiconductor wafer is GGG, quartz plate, etc. other than silicon, the C-V-O method is adopted.
（作 用）
上記方法によれば、保持具のプレートに半導体ウェーハ
の非研磨面に施した酸化膜が当接して研磨されるため、
非研磨面は被覆保護されると共に、酸化膜は均一な膜厚
で硬いため半導体ウェーハの平坦度をそのまま再現し、
研磨を可能とする。(Function) According to the above method, the oxide film applied to the unpolished surface of the semiconductor wafer comes into contact with the plate of the holder and is polished.
The unpolished surface is coated and protected, and the oxide film is hard and uniform in thickness, so it reproduces the flatness of a semiconductor wafer.
Allows polishing.
（実施例）
以下、本発明の実施例を図面に基づいて説明すると、第
１図は保持具に固定する前の半導体ウェーハを示し、半
導体ウェーハ１の非研磨面１ａ側に酸化膜２を形成づる
。(Example) Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 shows a semiconductor wafer before being fixed to a holder, and an oxide film 2 is formed on the non-polished surface 1a of the semiconductor wafer 1. Zuru.
上記酸化ＷＡ２は半導体ウェーハ１の基材にＣ−Ｖ−Ｄ
法により非研磨面１ａに酸化膜２を形成すると共に、そ
の膜厚は５００〜２０，０００人で全面を均一な厚さと
する。The above oxidized WA2 is C-V-D on the base material of the semiconductor wafer 1.
An oxide film 2 is formed on the non-polished surface 1a by a method, and its thickness is made uniform over the entire surface by 500 to 20,000 coats.
以上の如くして非研磨面１ａに酸化膜２を形成した半導
体つｌ−ハ１はウェーハ保持具Ａに嵌合装着して研磨作
業が行われる。The semiconductor substrate 1 with the oxide film 2 formed on the non-polished surface 1a as described above is fitted into the wafer holder A and a polishing operation is performed.
上記ウェーハ保持具Ａはプレート３と、そのプレート３
を保持する加圧ヘッド４と、半導体つ工−ハ１が嵌入す
る窓孔６を開穿した支持板５とで構成されている。The wafer holder A includes a plate 3 and a plate 3.
The support plate 5 has a window hole 6 into which the semiconductor tool 1 is inserted.
従って、半導体ウェーハ１の非研磨面１ａ側を被覆する
酸化膜２をプレート３と対向させた状態で支持板５の窓
孔６内のプレート３上に載置し、この半導体ウェーハ１
の酸化膜２とプレート３との間に介在させた水の表面張
力によって半導体ウェーハ１を保持具Ａに保持固定する
。以上の状態で半導体ウェーハ１の研磨面１ｂ側を定盤
７表面の研磨布８に圧接させ、加圧ヘッド４及び研磨機
の定盤７を夫々回転さゼて半導体ウェーハ１の研磨布１
ｂを研磨加工する。上記の研磨加工において、半導体ウ
ェーハ１の非研磨面１ａ側は硬度膜である酸化膜を介し
てプレート３に保持されるため、非研磨面１ａ側に傷が
付くのを確実に防止できると共に、硬質材のプレート３
に、硬度膜で均一な厚さの酸化膜２が当接するため、プ
レート表面の平ｌ！ｌ疾はそのまま再現され、その結果
、定盤７上の研磨布８に対する半導体ウェーハ１の加圧
も全面均一に行われて均一な厚さに研磨加工が行われる
。研磨完了模における酸化膜２の洗浄除去は、フッ酸等
によって行う。Therefore, the oxide film 2 covering the non-polished surface 1a side of the semiconductor wafer 1 is placed on the plate 3 in the window hole 6 of the support plate 5 with the oxide film 2 facing the plate 3, and the semiconductor wafer 1
The semiconductor wafer 1 is held and fixed to the holder A by the surface tension of the water interposed between the oxide film 2 and the plate 3. In the above state, the polishing surface 1b side of the semiconductor wafer 1 is brought into pressure contact with the polishing cloth 8 on the surface of the surface plate 7, and the pressure head 4 and the surface plate 7 of the polishing machine are rotated, respectively, and the polishing cloth 1 of the semiconductor wafer 1 is
Polish b. In the above polishing process, since the non-polished surface 1a side of the semiconductor wafer 1 is held on the plate 3 via the oxide film, which is a hard film, it is possible to reliably prevent scratches on the non-polished surface 1a side, and Hard material plate 3
Since the oxide film 2, which is a hard film and has a uniform thickness, comes into contact with the surface of the plate, the plate surface is evenly flat! The damage is reproduced as is, and as a result, the semiconductor wafer 1 is evenly pressed against the polishing cloth 8 on the surface plate 7 over the entire surface, and the polishing process is performed to a uniform thickness. The oxide film 2 is removed by cleaning after polishing is completed using hydrofluoric acid or the like.
（発明の効果）
本発明の研磨方法は以上詳述した如く、半導体ウェーハ
の非研磨面側を予め酸化膜で被覆し、研磨加工終了後、
前記酸化膜を除去するようにしたものであるから、保持
具におけるプレートとの当接面にクツション材などを介
在せずども非研磨面に傷が付くのを確実に防止し得ると
共に、酸化膜は硬度膜で均一な厚さに形成できるため、
プレート表面の平坦度をそのまま再現することができる
。(Effects of the Invention) As detailed above, in the polishing method of the present invention, the non-polished side of the semiconductor wafer is coated with an oxide film in advance, and after the polishing process is completed,
Since the oxide film is removed, it is possible to reliably prevent scratches on the non-polished surface without intervening a cushion material or the like on the contact surface with the plate of the holder, and to remove the oxide film. is a hard film that can be formed to a uniform thickness.
The flatness of the plate surface can be reproduced as is.
従って、半導体ウェーハの加圧は全面均一に行わ゛れ、
研磨終了後のウェーハは均一な厚さに仕上げることがで
きる。Therefore, the pressure on the semiconductor wafer is uniformly applied over the entire surface.
After polishing, the wafer can be finished to have a uniform thickness.
依って、高品質の研磨を行うことができる研磨方法を提
供できる。Therefore, it is possible to provide a polishing method that can perform high-quality polishing.
図面は本発明の実施例を示し、第１図は酸化膜を施した
半導体ウェーハの一部切欠斜視図、第２図は研磨状態の
断面図、第３図は保持具の従来構造を示す断面図である
。
図中、
１：半導体ウェーハ
１ａ：半導体ウェーハの非研磨面
２：Ｍ化膜The drawings show an embodiment of the present invention; FIG. 1 is a partially cutaway perspective view of a semiconductor wafer coated with an oxide film, FIG. 2 is a sectional view of a polished state, and FIG. 3 is a sectional view of a conventional structure of a holder. It is a diagram. In the figure, 1: Semiconductor wafer 1a: Non-polished surface of semiconductor wafer 2: M film
Claims (1)
状態で該ウェーハの研磨面側を研磨装置の定盤表面の研
磨布に圧接させて研磨する研磨方法において、前記半導
体ウェーハの非研磨面側を予め酸化膜で被覆し、研磨加
工終了後、前記酸化膜を除去することを特徴とする研磨
方法。In a polishing method, the non-polished surface of the semiconductor wafer is polished by pressing the polishing surface of the wafer into contact with a polishing cloth on the surface of a surface plate of a polishing device while the non-polished surface of the semiconductor wafer is fitted and attached to a holder. A polishing method characterized in that the side is coated with an oxide film in advance, and the oxide film is removed after polishing is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62284867A JPH01125830A (en) | 1987-11-10 | 1987-11-10 | Grinding of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62284867A JPH01125830A (en) | 1987-11-10 | 1987-11-10 | Grinding of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125830A true JPH01125830A (en) | 1989-05-18 |
Family
ID=17684058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62284867A Pending JPH01125830A (en) | 1987-11-10 | 1987-11-10 | Grinding of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125830A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104153A (en) * | 1992-03-16 | 1994-04-15 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5655052A (en) * | 1979-10-11 | 1981-05-15 | Nippon Telegr & Teleph Corp <Ntt> | Mechanical and chemical polishing |
| JPS5927529A (en) * | 1982-08-03 | 1984-02-14 | Clarion Co Ltd | Fabrication of semiconductor device wafer |
| JPS6251226A (en) * | 1985-08-30 | 1987-03-05 | Toshiba Corp | Polishing method |
-
1987
- 1987-11-10 JP JP62284867A patent/JPH01125830A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5655052A (en) * | 1979-10-11 | 1981-05-15 | Nippon Telegr & Teleph Corp <Ntt> | Mechanical and chemical polishing |
| JPS5927529A (en) * | 1982-08-03 | 1984-02-14 | Clarion Co Ltd | Fabrication of semiconductor device wafer |
| JPS6251226A (en) * | 1985-08-30 | 1987-03-05 | Toshiba Corp | Polishing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104153A (en) * | 1992-03-16 | 1994-04-15 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor integrated circuit |
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