JPH01125818A - Heterointerface formation - Google Patents

Heterointerface formation

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Publication number
JPH01125818A
JPH01125818A JP28221587A JP28221587A JPH01125818A JP H01125818 A JPH01125818 A JP H01125818A JP 28221587 A JP28221587 A JP 28221587A JP 28221587 A JP28221587 A JP 28221587A JP H01125818 A JPH01125818 A JP H01125818A
Authority
JP
Japan
Prior art keywords
semiconductor
mixed crystal
crystal
interface
molecular layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28221587A
Other languages
Japanese (ja)
Other versions
JPH0727865B2 (en
Inventor
Yuichi Ide
雄一 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
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Priority to JP28221587A priority Critical patent/JPH0727865B2/en
Publication of JPH01125818A publication Critical patent/JPH01125818A/en
Publication of JPH0727865B2 publication Critical patent/JPH0727865B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make it possible to form a heterointerface of high quality by a method wherein the surface of a N-component mixed crystal of first semiconductor is flattened so that the stepping on the surface becomes a single molecular layer, the mixed crystal is grown one molecular layer only, and a M- component mixed crystal second semiconductor is epitaxially grown. CONSTITUTION:A N-component mixed crystal of first semiconductor is epitaxially grown, the surface of the first semiconductor is flattened so that it has the stepping of single molecular layer. Then, a Q-component crystal of third semiconductor, consisting of positive ionized element and a negative ionized element which are common to a N-component mixed crystal of first semiconductor and a M-component crystal or mixed crystal of second semiconductor (Q indicates the natural number of 2<=Q<=N) is grown in one-molecular layer only. The second semiconductor M-initial crystal is epitaxially grown. As a result, an interface is formed by a flat island in the height of one- molecular layer, and the undesirable mixed crystal layer of extremely steep, scattered carrier and disordering energy potential are not generated.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ヘテロ界面の形成方法に関し、特に分子線エ
ピタキシ法によって化合物半導体の高品質ヘテロ界面を
形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a heterointerface, and particularly to a method for forming a high quality heterointerface of a compound semiconductor by molecular beam epitaxy.

[従来の技術] 2次元電子ガストランジスタや量子井戸レーザのような
化合物半導体のデバイスは、その多くが異種の半導体結
晶を接合したベテロ接合を利用するものである。ペテロ
接合界面(以下、ヘテロ界面と称する)の性質はキャリ
アの散乱や、発光、吸収等に影響し、デバイス特性を大
きく左右する。
[Prior Art] Most compound semiconductor devices such as two-dimensional electron gas transistors and quantum well lasers utilize betero junctions in which different types of semiconductor crystals are joined. The properties of the heterojunction interface (hereinafter referred to as heterointerface) affect carrier scattering, light emission, absorption, etc., and greatly influence device characteristics.

従って、平坦かつ急峻で、不純物や欠陥のない高品質の
界面を形成することが重要である。このような急峻なヘ
テロ界面を形成する手段として分子線エピタキシ(Mo
lecular Beam Epitaxy、以下MB
Eと称する)法が広く行われている。
Therefore, it is important to form a high-quality interface that is flat, steep, and free of impurities and defects. Molecular beam epitaxy (Mo.
Regular Beam Epitaxy, hereinafter MB
(referred to as E) is widely practiced.

第2図は、このMBE法を行うために一般的に用いられ
るMBE装置の概略断面図を示したもので、イオンポン
プ等の真空ポンプ9によって超高真空に保たれた成長室
1中に、所望の結晶を構成する元素を含む原料を加熱し
、分子線状に各元素を噴出させる分子線源20,21,
22.23と、この分子線源20.21.22.23と
は独立に温度制御可能に基板4を加熱・保持する基板ホ
ルダ3とを設け、各分子線源20,21,22.23か
ら基板4に向けて原料元素の分子線を噴出させてエピタ
キシャル成長を行うものである。MBE法では、各分子
線源の前方に配設されたシャッタ5a〜5dの開閉によ
り個々の分子線の断続を行うと共に、各原料の蒸発源の
温度設定により分子線強度の変調制御を行うことができ
る。
FIG. 2 shows a schematic cross-sectional view of an MBE apparatus commonly used to perform this MBE method. Molecular beam sources 20, 21, which heat a raw material containing elements constituting a desired crystal and eject each element in the form of molecular beams;
22.23 and a substrate holder 3 that heats and holds the substrate 4 in a temperature controllable manner independently of the molecular beam sources 20, 21, 22.23. Epitaxial growth is performed by ejecting molecular beams of raw material elements toward the substrate 4. In the MBE method, individual molecular beams are interrupted by opening and closing shutters 5a to 5d disposed in front of each molecular beam source, and the molecular beam intensity is modulated and controlled by setting the temperature of the evaporation source of each raw material. Can be done.

従来、MBE法において原子のオーダーで平坦かつ急峻
なペテロ界面を形成する方法としては、各分子線源20
〜23のシャッタ58〜5dを閉じることで成長を界面
で中断し、数十秒ないし数分間待機することにより、界
面の平坦性を増す方法がGaAs/ #GaASヘテロ
系について報告されている(ジャパニーズ・ジャーナル
・オブ・アプライド・フィジックス(Jpn、J、Ap
pl、Phys、 )、24. (1985)。
Conventionally, in the MBE method, each molecular beam source 20
A method of increasing the flatness of the interface by closing the shutters 58 to 5d of ~23 to interrupt the growth at the interface and waiting for several tens of seconds to several minutes has been reported for the GaAs/#GaAS hetero system (Japanese).・Journal of Applied Physics (Jpn, J, Ap
pl, Phys, ), 24. (1985).

シ417頁)。ここではこの方法を、界面待IXIMB
E法と呼ぶ。
(page 417). Here we will use this method,
It is called the E method.

第3図は従来の界面待BIMBE法によるペテロ界面形
成方法を工程順に模式的に説明した説明図である。ここ
ではAxCl−xD3元混晶上にA、B1.D3元混晶
を界面待機MBE法により積層゛する場合を説明する。
FIG. 3 is an explanatory view schematically explaining a method for forming a Peter interface using the conventional interfacial BIMBE method in the order of steps. Here, A, B1. A case in which D ternary mixed crystals are laminated by the interface standby MBE method will be described.

なお、A、B、Cは陽イオン性、Dは陰イオン性元素を
表す。また図中、D元素については省略した。
In addition, A, B, and C represent a cationic element, and D represents an anionic element. Further, in the figure, element D is omitted.

第2図において、分子線源20.21.22および23
にそれぞれA、C,BおよびDの各元素の原料を入れ、
分子線源20.21および23の前方のシャッタ5a。
In Figure 2, molecular beam sources 20, 21, 22 and 23
Put the raw materials of each element A, C, B and D into the
Shutter 5a in front of molecular beam sources 20.21 and 23.

5bおよび5dを開き、下地のAxCl−xDの成長を
行った後、AおよびC元素の分子線源20および21の
前方のシャッタ5aおよび5bを閉じてD元素のみを照
射する状態とする。中断した瞬間には、第3図(a)に
示すように表面に高さ2分子層におよぶ凹凸が存在して
いる。しかし、そのまま90〜180秒待期を続けると
表面上のAおよびC原子あるいは分子が表面を拡散し、
表面のステップやキンクに捉えられて第3図(b)に示
すように高さが1分子層の平坦な島を形成する。次に、
AおよびB元素の分子線源20および22の前方のシャ
ッタ5aおよび5Cを開いて、平坦化された表面の上に
A、B1.D3元混晶を成長させれば、第3図(C)に
示すように所望のヘテロ界面が得られる。
5b and 5d are opened to grow the underlying AxCl-xD, the shutters 5a and 5b in front of the molecular beam sources 20 and 21 for the A and C elements are closed to irradiate only the D element. At the moment of interruption, as shown in FIG. 3(a), there are irregularities on the surface with a height of two molecular layers. However, if we continue to wait for 90 to 180 seconds, the A and C atoms or molecules on the surface will diffuse across the surface.
It is captured by steps and kinks on the surface, forming flat islands with a height of one molecular layer, as shown in FIG. 3(b). next,
The shutters 5a and 5C in front of the molecular beam sources 20 and 22 for elements A and B are opened, and A, B1 . By growing the D ternary mixed crystal, a desired heterointerface can be obtained as shown in FIG. 3(C).

こうして得られた界面の遷移領域の幅は、1分子層分で
あり、極めて急峻かつ平坦なものである。
The width of the transition region of the interface thus obtained is one molecular layer, and is extremely steep and flat.

[発明が解決しようとする問題点] しかしながら、この1分子層分の遷移領域を詳細に検討
すると、この部分は陽イオン性元素としてA、B、03
種類の元素が共存した4元混晶になっている。このこと
は次のような不利益をもたらす。即ち、4元混晶は3元
混晶よりもキャリアを散乱させやすい。また界面に望ま
しくないエネルギーポテンシャルの乱れが生じ、界面に
沿う方向へのキャリアの輸送を妨げる。この問題は、遷
移領域の4元混晶組成が界面に平行な面内で均一でない
ので、ことに重大である。界面にあけるポテンシャルの
乱れは、このような界面を持つ吊子井戸からの励起子発
光のスペクトル幅を拡げる動きをする。従って量子井戸
を光素子に応用する際には大きな問題である。
[Problems to be Solved by the Invention] However, when the transition region for one molecular layer is examined in detail, this part is composed of A, B, and 03 as cationic elements.
It is a quaternary mixed crystal in which different types of elements coexist. This brings about the following disadvantages. That is, the quaternary mixed crystal scatters carriers more easily than the ternary mixed crystal. Additionally, undesirable energy potential disturbances occur at the interface, which impedes carrier transport in the direction along the interface. This problem is particularly serious because the quaternary mixed crystal composition of the transition region is not uniform in the plane parallel to the interface. Disturbances in the potential created at the interface act to widen the spectral width of exciton emission from a hanger well with such an interface. Therefore, this is a big problem when applying quantum wells to optical devices.

本発明の目的は、以上述べたような従来の問題点を解決
するためになされたもので、界面での望ましくない混晶
の形成を防止して高品質のヘテロ界面を形成する方法を
提供することにある。
An object of the present invention was to solve the conventional problems as described above, and to provide a method for forming a high-quality heterointerface by preventing the formation of undesirable mixed crystals at the interface. There is a particular thing.

[問題点を解決するための手段] 本発明は、第1.の半導体N元混晶(Nは3以上の自然
数を表す)の上に該第1の半導体N元混晶と共通の陽イ
オン性元素と陰イオン性元素を少なくとも1個ずつ含む
第2の半導体M元混晶(Mは3以上の自然数を表す)を
積層してなる半導体ヘテロ界面の形成方法において、第
1の半導体N元混晶をエピタキシャル成長させる第1の
成長工程と、成長した第1の半導体N元混晶表面の段差
が1分子層となるように平坦化する表面平坦化工程と、
前記第1の半導体N元混晶と第2の半導体M元混晶に共
通の陽イオン性元素および陰イオン性元素からなる第3
の半導体0元結晶または混晶(Qは2≦Q≦Nの自然数
を表す)を1分子層だけ成長させる第2の成長工程と、
前記第2の半導体M元混晶をエピタキシャル成長させる
第3の成長工程とを有してなることを特徴とするヘテロ
界面形成方法である。
[Means for solving the problems] The present invention has the following features: 1. a second semiconductor containing at least one cationic element and one anionic element common to the first semiconductor N-element mixed crystal on a semiconductor N-element mixed crystal (N represents a natural number of 3 or more); In a method for forming a semiconductor hetero-interface formed by laminating M-element mixed crystals (M represents a natural number of 3 or more), a first growth step of epitaxially growing a first semiconductor N-element mixed crystal; a surface flattening step of flattening the surface of the semiconductor N-element mixed crystal so that the step becomes one molecular layer;
A third semiconductor composed of a cationic element and an anionic element common to the first N-element semiconductor mixed crystal and the second semiconductor M-element mixed crystal.
a second growth step of growing only one molecular layer of a semiconductor zero-element crystal or mixed crystal (Q represents a natural number of 2≦Q≦N);
A method for forming a heterointerface, comprising a third growth step of epitaxially growing the second semiconductor M-element mixed crystal.

[作用] 第1図は本発明によるヘテロ界面形成方法を工程順に模
式的に説明した説明図である。ここではAxCl−xD
3元混晶上にA、B1−VD3元混晶を積層する場合を
説明する。なお、A、B、Cは陽イオン性、Dは陰イオ
ン性元素を表す。また図中、D元素については省略した
[Operation] FIG. 1 is an explanatory diagram schematically explaining the method for forming a heterointerface according to the present invention in the order of steps. Here, AxCl-xD
A case will be described in which A, B1-VD ternary mixed crystals are laminated on a ternary mixed crystal. In addition, A, B, and C represent a cationic element, and D represents an anionic element. Further, in the figure, element D is omitted.

第1図(a)は下地のAxCl−xDの成長を行った後
、成長を中断した時の下地の半導体3元混晶の表面を示
したものである。次に、平坦化を行って、第1図(b)
に示すような表面状態とした後、第1および第2の半導
体混晶に共通の元素からなる結晶を1分子層分成長させ
ると第1図(C)に示す如くなり、界面の遷移領域には
、高々N元の混晶しか形成されない。次いで第1図(d
)に示すように、第2の半導体混晶であるA、B1.D
を積層してヘテロ構造を形成する。この方法によれば、
従来の方法のように下地の混晶より次数の高い、即ちキ
ャリアを散乱しゃすい混晶が形成されることがなく、キ
ャリアの輸送効率の高い界面が得られる。
FIG. 1(a) shows the surface of the underlying semiconductor ternary mixed crystal when the growth of the underlying AxCl-xD was interrupted. Next, flattening is performed, as shown in Fig. 1(b).
After forming the surface state as shown in Figure 1(C), if a single molecular layer of crystal consisting of the element common to the first and second semiconductor mixed crystals is grown, it will become as shown in Figure 1(C), and a transition region at the interface will be formed. In this case, only a mixed crystal of at most N elements is formed. Next, Figure 1 (d
), the second semiconductor mixed crystals A, B1. D
are stacked to form a heterostructure. According to this method,
Unlike conventional methods, a mixed crystal having a higher order than the underlying mixed crystal, that is, a mixed crystal that easily scatters carriers, is not formed, and an interface with high carrier transport efficiency can be obtained.

[実施例] 以下、図面を参照しながら本発明の一実施例を説明する
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

本発明の方法に用いられるMBE装置としては例えば前
記の第2図に示すような装置を用いることができる。以
下、例として第1図の説明図におけるAをIn、 3を
Ga、 C@All、 DをASとし、InP(001
)基板上に第1の半導体N元混晶として、In、 M、
−xAs (x=0.52)を、第2のM元竿導体混晶
としてIn、 Ga1−、 AS (V=0.53)を
積層してヘテロ構造を形成する場合について述べる。
As the MBE apparatus used in the method of the present invention, for example, an apparatus as shown in FIG. 2 described above can be used. Hereinafter, as an example, in the explanatory diagram of FIG. 1, A is In, 3 is Ga, C@All, and D is AS, and InP (001
) As the first semiconductor N-element mixed crystal on the substrate, In, M,
A case will be described in which a heterostructure is formed by stacking In, Ga1-, and AS (V=0.53) using -xAs (x=0.52) as a second M-element conductor mixed crystal.

第2図に示すMBE装置の各分子線源は、それぞれ20
にIn、 21にGa、 22にM、23にAsが原料
として充填されている。
Each molecular beam source of the MBE apparatus shown in FIG.
In is filled in 21, Ga is filled in 22, M is filled in 22, and As is filled in 23 as raw materials.

まず、通常の方法によりInP(001)基板4を有機
洗浄し、化学的にエツチングして清浄化した復、io”
 Torr台の超高真空に排気された成長室1中。
First, the InP (001) substrate 4 was organically cleaned using a conventional method, and then chemically etched and cleaned.
Inside growth chamber 1, which is evacuated to an ultra-high vacuum on a Torr stand.

の基板ホルダ3に装着する。Attach it to the board holder 3 of.

成長開始に先立ち、In、 Ga、 #の各分子線源2
0゜21.22は所望の組成、即らInxAJ!1−x
As (x=0.52>とIn、 Ga1−vAS (
V=0.53)が得られるように温度制御される。また
、As分子線源23も、InP基板4表面において2 
X 10−”Torrの強度が得られるように温度を制
御する。As分子線源23の前方のシャッタ5dを開け
、As分子線をInP基板4に照射しつつ、基板ホルダ
3に取付けられた抵抗ヒータの温度を上げ、As圧下で
InP基板4の表面を熱クリーニングする。通常、54
0℃で表面の酸化膜や汚れが脱離し、表面が清浄となる
。次に基板温度を550℃に安定させ、InとMの分子
線源20.22の前方のシャッタ5a、 5cを開けて
、In0.52M0.48ASを0.5pm成長さげる
(第1の成長工程)。典型的な成長。
Prior to the start of growth, each molecular beam source 2 of In, Ga, and
0°21.22 is the desired composition, ie InxAJ! 1-x
As (x=0.52> and In, Ga1-vAS (
The temperature is controlled so that V=0.53) is obtained. Further, the As molecular beam source 23 also has 2
The temperature is controlled so that an intensity of The temperature of the heater is raised and the surface of the InP substrate 4 is thermally cleaned under As pressure.
At 0°C, the oxide film and dirt on the surface are removed and the surface becomes clean. Next, the substrate temperature is stabilized at 550°C, the shutters 5a and 5c in front of the In and M molecular beam sources 20.22 are opened, and In0.52M0.48AS is grown by 0.5 pm (first growth step). . typical growth.

速度は0.81Jfn/hでil>ッた。The speed was 0.81 Jfn/h.

次に、InとNの分子線源20.22のシャッタ5a。Next, the shutter 5a of the In and N molecular beam source 20.22.

5Cを閉じて成長を中断する。ここで成長の中断の瞬間
は前記の第1図(a)に対応する。
Closing 5C interrupts growth. Here, the moment of interruption of growth corresponds to the above-mentioned FIG. 1(a).

次いで、そのままASを照射しながら120秒待機を行
って平坦化を行う(平坦化工程)。この状態は前記の第
1図(b)に対応する。
Next, flattening is performed by waiting for 120 seconds while irradiating AS (flattening step). This state corresponds to the above-mentioned FIG. 1(b).

次に、Inの分子線源20の前方のシャッタ5aを1分
子層の厚さ、即ち、約2.93人に相当する2、5秒だ
け開ける。この第2の成長工程により表面がInAsに
より覆われる(第1図(C)に対応)。
Next, the shutter 5a in front of the In molecular beam source 20 is opened for 2.5 seconds corresponding to the thickness of one molecular layer, that is, about 2.93 people. This second growth step covers the surface with InAs (corresponding to FIG. 1(C)).

続いて、Gaの分子線源21の前方のシャッタ5bを開
け、In(、53Ga0.47ASを成長させ、第3の
成長工程を行う。
Subsequently, the shutter 5b in front of the Ga molecular beam source 21 is opened, In(,53Ga0.47AS) is grown, and a third growth step is performed.

以上の工程により前記第1図(d)に対応するヘテロ界
面が形成される。このヘテロ界面では、界面に平行な方
向には4元混晶は存在せず、界面は3元混晶であるIn
x、#1−x、AsからIny、Ga1−y、ASへ急
峻に切替っている。従って、従来の界面待BIMBE法
では避けられない、4元混晶よりなる界面遷移領域が生
じず、高品質な界面が得られる。界面にできるIn、 
・M 1−、 tAsとIny・Ga1−y−Asは、
必ずしもInP基板4に格子整合しないが、1分子層し
かないのでその影響はほとんど無視できる。
Through the above steps, a hetero interface corresponding to that shown in FIG. 1(d) is formed. At this hetero interface, there is no quaternary mixed crystal in the direction parallel to the interface, and the interface is a ternary mixed crystal of In
There is a sharp switch from x, #1-x, As to Iny, Ga1-y, AS. Therefore, an interfacial transition region consisting of a quaternary mixed crystal, which is inevitable in the conventional interfacial BIMBE method, does not occur, and a high-quality interface can be obtained. In formed at the interface,
・M 1-, tAs and Iny・Ga1-y-As are,
Although it is not necessarily lattice matched to the InP substrate 4, since there is only one molecular layer, its influence can be almost ignored.

[発明の効果] 以上述べたように、本発明のヘテロ界面形成方法によれ
ば、界面が1分子層の高ざの平坦な島から形成され、極
めて急峻であるだけでなく、キャリアを散乱したり、エ
ネルギーポテンシャルを乱す望ましくない混晶層を生じ
ない。この結果、ペテロ界面に沿ったキャリアの輸送現
象を利用した電子デバイスの作製や、界面での混晶(合
金)散乱が発光スペクトル幅に影響する量子井戸を用い
た光素子の作製に適する。
[Effects of the Invention] As described above, according to the method for forming a heterointerface of the present invention, the interface is formed from a flat island with a height of one molecular layer, and is not only extremely steep but also scatters carriers. or create undesirable mixed crystal layers that disturb the energy potential. As a result, it is suitable for fabricating electronic devices that utilize carrier transport phenomena along the Peter interface, and for fabricating optical devices using quantum wells in which mixed crystal (alloy) scattering at the interface affects the emission spectrum width.

【図面の簡単な説明】 第1図は本発明のヘテロ界面形成方法を模式的に説明し
た工程図、第2図は本発明の方法に用いられるMBE装
置の一例を示す概略断面図、第3図は従来の界面時IM
BE法によるペテロ界面の形成方法を模式的に説明した
工程図である。 1・・・成長室     3・・・基板ホルダ4・・・
基板      5a〜5d・・・シャッタ9・・・真
空ポンプ   20〜23・・・分子線源A、B、C・
・・陽イオン性元素 D・・・陰イオン性元素
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a process diagram schematically explaining the method for forming a heterointerface of the present invention, FIG. 2 is a schematic cross-sectional view showing an example of an MBE apparatus used in the method of the present invention, and FIG. The figure shows the conventional interface IM
FIG. 3 is a process diagram schematically explaining a method for forming a Peter interface using the BE method. 1... Growth chamber 3... Substrate holder 4...
Substrate 5a to 5d...Shutter 9...Vacuum pump 20 to 23...Molecular beam sources A, B, C.
...Cationic element D...Anionic element

Claims (1)

【特許請求の範囲】[Claims] (1)第1の半導体N元混晶(Nは3以上の自然数を表
す)の上に該第1の半導体N元混晶と共通の陽イオン性
元素と陰イオン性元素を少なくとも1個ずつ含む第2の
半導体M元混晶(Mは3以上の自然数を表す)を積層し
てなる半導体ヘテロ界面の形成方法において、第1の半
導体N元混晶をエピタキシャル成長させる第1の成長工
程と、成長した第1の半導体N元混晶表面の段差が1分
子層となるように平坦化する表面平坦化工程と、前記第
1の半導体N元混晶と第2の半導体M元混晶に共通の陽
イオン性元素および陰イオン性元素からなる第3の半導
体Q元結晶または混晶(Qは2≦Q≦Nの自然数を表す
)を1分子層だけ成長させる第2の成長工程と、前記第
2の半導体M元混晶をエピタキシャル成長させる第3の
成長工程とを有してなることを特徴とするヘテロ界面形
成方法。
(1) At least one cationic element and one anionic element common to the first semiconductor N-element mixed crystal (N represents a natural number of 3 or more) on the first semiconductor N-element mixed crystal In the method for forming a semiconductor hetero-interface formed by stacking a second semiconductor M-element mixed crystal (M represents a natural number of 3 or more) including a first semiconductor M-element mixed crystal, a first growth step of epitaxially growing a first semiconductor N-element mixed crystal; A surface flattening step of flattening the surface of the grown first semiconductor N-element mixed crystal so that it becomes one molecular layer, and common to the first semiconductor N-element mixed crystal and the second semiconductor M-element mixed crystal. a second growth step of growing one molecular layer of a third semiconductor Q element crystal or mixed crystal (Q represents a natural number of 2≦Q≦N) consisting of a cationic element and an anionic element; and a third growth step of epitaxially growing a second semiconductor M-element mixed crystal.
JP28221587A 1987-11-10 1987-11-10 Hetero interface formation method Expired - Fee Related JPH0727865B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28221587A JPH0727865B2 (en) 1987-11-10 1987-11-10 Hetero interface formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28221587A JPH0727865B2 (en) 1987-11-10 1987-11-10 Hetero interface formation method

Publications (2)

Publication Number Publication Date
JPH01125818A true JPH01125818A (en) 1989-05-18
JPH0727865B2 JPH0727865B2 (en) 1995-03-29

Family

ID=17649557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28221587A Expired - Fee Related JPH0727865B2 (en) 1987-11-10 1987-11-10 Hetero interface formation method

Country Status (1)

Country Link
JP (1) JPH0727865B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH041427A (en) * 1990-04-13 1992-01-06 Yanmar Diesel Engine Co Ltd Soundproofing type working device
JP2002240790A (en) * 2001-02-14 2002-08-28 Honda Motor Co Ltd Cooling passage structure for outboard motor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH041427A (en) * 1990-04-13 1992-01-06 Yanmar Diesel Engine Co Ltd Soundproofing type working device
JP2002240790A (en) * 2001-02-14 2002-08-28 Honda Motor Co Ltd Cooling passage structure for outboard motor

Also Published As

Publication number Publication date
JPH0727865B2 (en) 1995-03-29

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