JPH01125139A - Synchronization switching device - Google Patents

Abstract

PURPOSE:To prevent the range of a change in irregular phase fluctuation of an output data string when a frame synchronization is unlocked even with a wide dynamic range from being widened by decreasing number of stages of buffer memories when the frame synchronization required to form a write clock of the buffer memories is unlocked. CONSTITUTION:When the frame synchronization required to form a write clock of buffer memories 5, 6 is unlocked, the number of stages of the buffer memories 5, 6 is decreased to reduce the storage period of each stage. Since the range in the change of irregular fluctuation of the phase of an output data occurred in this way is made narrow, the occurrence of an error for a long time from the unlocked clock synchronization in a demodulator of a succeeding radio line till the recovery of the clock synchronization is prevented. Since the possibility of unlocked clock synchronization in the succeeding demodulation is precluded, the number of stages of buffer memories is increased to widen the dynamic range of synchronization switching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous switching device, and more particularly to a synchronous switching device used for switching data signals in a digital wireless communication system.

[Conventional technology]

The data signal being transmitted on the working radio line is transmitted in parallel on the backup radio line, and at the receiving end, the data signal is switched from the data signal via the working radio line to the data signal via the backup radio line, and the data signal is transferred between the working radio line and the backup radio line. When switching lines, if the propagation delay difference between the working radio line and the backup radio line fluctuates over time and exceeds one time slot of the data signal, bit errors will occur if the two data signals are simply switched. do. In order to avoid the occurrence of this bit error, a synchronous switching device is used that performs bit synchronization of both data signals before switching.

Such a synchronous switching device is also used to switch data signals output by two receivers for diversity reception.

FIG. 4 is a block diagram showing an example of such a conventional synchronous switching device.

DI and D2 are data strings to be switched, and are the same data strings except that their timings do not necessarily match. CLI and CL2 are clocks for data strings DI and D2. S3 is a switching control signal that instructs which of the data strings DI and D2 is selected and output.

Reference numerals 18 and 19 designate buffer memories in which data columns DI and D2 are sequentially written and sequentially read, and are composed of (for example) four stages of memory cells.

Reference numeral 16.17 is a frequency division counter that generates four clocks for writing to the buffer memory 18.19. frequency division counter 16,
17 is a clock CLI (corresponding to the buffer memories 18 and 19 having four stages);

CL2 is counted and frequency-divided by 4, and four frequency-divided outputs whose phases are sequentially shifted are output respectively. These four divided outputs are clocked at CL7. Let's call it CL8. Clock CL7. Data string Di, using CL8 as a write clock,
D2 is a buffer memo! The data is sequentially written to each stage of 718 and 19.

Since the frequency division output of frequency division by 4 can have four different phases, if the initial phases of the frequency division counters 16 and 17 are uncertain, the data written to, for example, the first stage of the buffer memory 18 by the clock CL7 and the clock The data does not necessarily match the data written to the first stage of the buffer memory 19 by CL8.

The frame synchronization circuits 14.15 detect frame synchronization bits from the data strings DI and D2, and frame pulses PI and
Generates P2. By resetting the frequency division counters 16 and 17 with the frame pulses PL and P2 in accordance with the timing deviation between the data strings Di and D2 and determining their initial phases, the data written to each stage of the buffer memory 18 can be adjusted. It is possible to match the data written to each stage of the buffer memory 19.

7 is data string D read from buffer memory 18.19
6. This is a switch that selects and outputs either one of D7, and the upstream conductor is instructed by the switching control signal S3.

Clock CL9, which is a common read clock for buffer memories 18 and 19, is created as described below.

Reference numeral 9 denotes a switch controlled by the switching control signal S3, and when the switch 7 selects the data string D6, it selects and outputs one of the four switches CL7, and the switch 7 selects the data string D7. When the clock is running, one of the clocks CL8 is output. 2
0 is a frequency division counter that counts the output of vcolo and divides the frequency by four in the same way as frequency division counters 16 and 17, and outputs four frequency division outputs whose phases are sequentially shifted as clock CL9.

vcoto configured by returning one of the clocks CL9 to the phase comparator 12, a frequency division counter 20, a phase comparator 12. A phase-locked loop (hereinafter referred to as PLL) consisting of a low-pass filter 13 operates to
Phase synchronize OIO to clock -CLI or CL2.

When vCOLO is constantly phase-synchronized with clock CL, clock OL9 connects each stage of buffer memory 18 to
The delay time of the clock CL9 from the frequency dividing counter 20 to the buffer memory 18 is set so that it is read out sequentially at the center of each stage's holding period (four cycles of clocks c, , t+1). Also, vc6t.

When the clock OL9 is constantly phase-synchronized with the clock CL2, the clock OL9 reads out each stage of the buffer memory 19 from the frequency division counter 20 to the buffer memory 19 in the same manner as described above.
Set the delay time until.

As a result of this setting, if the timing difference between the data strings DI and D2 is within two cycles of the clocks CLI and CL2, V
COIO Garityri CLl.

No matter which one of the data strings D6.CL2 is phase-locked, the data string D6.
D7 matches including the timing, and no bit error occurs due to switching of the switch 7. The clock 0LIO which is the output of vcoto is the clock of the data string D8 which is the output of the switch 7.

As the switching device 7 switches, the timing at which VCOIO is synchronized also changes, so after switching, the output phase of vcoto is PL
With a response speed of L, the data string DI.

It changes by an amount corresponding to the timing shift of D2, and the phase of data string D8 also changes by the same amount.

By the way, if the data string D1 becomes abnormal and the frame synchronization circuit 14 goes out of synchronization while the switch 7 is selecting (for example) the data string D6, the frame synchronization circuit 14
tries to recover synchronization and changes the phase of the frame pulse P1 greatly and rapidly.As a result, the frequency division counter 16 cannot output CL7 normally and the buffer memory 1
8 becomes abnormal, and as a result, the phase of data string D, 8 fluctuates irregularly over the entire retention period of each stage of the buffer memory 18. This fluctuation is caused by the frame synchronization circuit 1
The process continues until the frame synchronization of the frame synchronization circuit 15 is restored or the frame synchronization of the frame synchronization circuit 15 is lost and the switches 7 and 9 are switched.

An example of the structure of the frequency division counters 16 and 17 and the buffer memories 18 and 19 is detailed in Japanese Patent Publication No. 32535/1983, so please refer to it if necessary.

The embodiment shown in FIG. 4 has been described above.

By increasing the number of stages of the buffer memories 18 and 19 and the frequency division ratio of the frequency division counters 16 and 17.20, the data string D
The range (dynamic range) of timing deviation in which synchronization can be switched between I and D2 is also wide and negative. Furthermore, if the dynamic range is widened in this way, the range of irregular phase fluctuations in the output data string when frame synchronization is lost is also widened.

Now, if there is a lower-level wireless line that further transmits the data string outputted by such a synchronous switching device, the phase of the output data string changes as described above when the synchronous switching device performs switching, so the lower-level hot wire line It is necessary to increase the response speed of the PLL for clock synchronization of the demodulator to prevent clock synchronization. However, if the response speed of this PLL is increased, the C/N of
Therefore, the response speed should be set as slow as possible without losing clock synchronization when switching the synchronous switching device.

Therefore, if irregular wide range phase fluctuations occur in the output data string due to frame synchronization loss in the conventional synchronization switching device described above, clock synchronization loss may occur in the demodulator of the lower-order wireless link, and the demodulation When a device loses clock synchronization, it takes a long time to recover, and errors occur during that time.

[Problem that the invention seeks to solve]

As explained above, in conventional synchronous switching devices, if the frame synchronization required to create the write clock of the buffer memory is lost, the phase of the output data string fluctuates irregularly over a wide range, so the demodulation of the subsequent wireless line The drawback is that the clock synchronization may be lost in the device, causing an error that takes a long time to recover.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization switching device that can prevent the change range of irregular phase fluctuations of an output data string from becoming wide when frame synchronization is lost even if the dynamic range is widened.

[Means for solving problems]

The synchronization switching device of the present invention synchronizes the transmission data string including frame synchronization bits with the first and second data strings, which are the received data strings transmitted through two wireless transmission paths, respectively. Outputs a frame pulse of
first and second frame synchronization circuits that output first and second out-of-synchronization signals while the frame is out of synchronization;
The first data string is reset by the first frame pulse or its frequency divided pulse, and when the first desynchronization signal is not input, the first data string is reset at a predetermined first frequency division ratio that is an integer of 2 or more. When the first out-of-synchronization signal is input, the first data is divided by a predetermined second frequency division ratio that is a positive integer less than the first frequency division ratio. a first frequency division counter that divides a column clock and outputs a first frequency division output whose phase is sequentially shifted by a number equal to the first or second frequency division ratio; and the second frame pulse. or is reset by the frequency division pulse, and when the second desynchronization signal is not input, divides the clock of the second data string by the first frequency division ratio, and divides the clock of the second data string by the first frequency division ratio,
When an out-of-synchronization signal is input, the clock of the second data stream is divided by the second frequency division ratio, and the phase is sequentially shifted by a number equal to the first or second frequency division ratio. a second frequency division counter that outputs a second frequency division output; the number of stages is equal to the division ratio of the first frequency division counter; a first buffer memory in which a first data string is sequentially written to each stage;
a second buffer memory whose number of stages is equal to the frequency division ratio of the second frequency division counter, and in which the second data string is sequentially written into each stage using each of the second frequency division outputs as a write clock; a first switch that selects and outputs one of the third and fourth data strings read from the first and second buffer memories using a common read clock; a second switch that selects and outputs one of the out-of-synchronization signals in correspondence with the selection of the first switch; and the third or fourth data string selected by the first switch. a phase-locked oscillator synchronized in double phase with the clock of the fourth or second data string corresponding to the second data string; When neither input is input, the frequency is divided by the first frequency division ratio, and the frequency is divided by the second frequency division ratio.
When the first or second desynchronization signal is input from the switch, the frequency is divided by the second frequency division ratio, and the phase is sequentially shifted by a number equal to the first or second frequency division ratio. and a third frequency division counter that outputs the third frequency division output as the read clock.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a synchronous switching device of the present invention.

The embodiment shown in FIG.
2 and a frame synchronization circuit 1.2 that outputs clock CL.
I, CL2, frame pulses PL, P2 and out-of-synchronization signals Sl, 82 are input, and clocks C., L3.
Frequency division counters 3 and 4 that output CL4 and data string DI
.

D2 as well as out-of-sync signals 81.82 and clock CL3. CL4 and clock CL5 are input, and data string D3. Buffer memories 5, 6 that output data D4, and data strings D3. A switch 7 which inputs D4 and a switching control signal S3 and outputs a data string D5, and an out-of-synchronization signal 81.8.
2 and the switching control signal S3, a switching device 9 that receives one of the clocks CL3 and one of the clocks CL4 and the switching control signal S3, and the clock C
A VCOIO that outputs L6, a frequency division counter 11 that inputs the output of the switch 8 and the clock CL6, and outputs the clock CL5, a phase comparator 12 that inputs one of the clocks CL5 and the output of the switch 9, It is configured to include a low-pass filter 13 connected between the output terminal of the comparator 12 and the control input terminal of the VCOIO.

The embodiment shown in FIG. 1 has a switching device 8 in addition to the conventional example shown in FIG.
are added, frame synchronization circuits 14.15, frequency division counters 16, 17, buffer memories 18.19 and frequency division counter 20 are connected to frame synchronization circuits 1, 2, frequency division counters 3.4tt and buffer memory 5,
6 and a frequency division counter 11. In addition, data strings Di and D2 are respective received data strings obtained by transmitting a transmission data string including a frame synchronization bit through two wireless transmission paths, clocks CLI and CL2 are clocks of data strings Di and D2, and a switching control signal S3 is a data string. Column D
These are signals for instructing which of I and D2 to select and output, and are the same as those in FIG. 4, respectively.

The frame synchronization circuits 1 and 2 send synchronization loss signals 81 . This circuit is the same as the frame synchronization circuits 14 and 15 in FIG. 4, except that it outputs S2.

Frequency division counters 3 and 4 are frequency division counter 1 in FIG.
Frame pulse PI similar to 6 and 17.

It is reset by P2 and counts the clocks CLI and CL2, and if the out-of-synchronization signal 81.82 is not input, the frequency is divided by a frequency division ratio of 4, and if it is input, the frequency is divided by a frequency division ratio of 2. It is a lap counter. Therefore, the out-of-sync signal 81.
If 82 is not input, a, riCL3. CL4 is the clock CL7. in FIG. It is the same as CL8, and the out-of-synchronization signals 81 and 82 are input.

3 and CL4 are two divided outputs, respectively.

The switch 8 is controlled by the switch control signal S3, and the switch 7
When the switch 7 selects the data string D3, it selectively outputs the out-of-synchronization signal Sl, and when the switch 7 selects the data string D4, it selects and outputs the out-of-synchronization signal S2.

The frequency division counter 11 is the frequency division counter 20 in FIG.
Similarly, the output of VCOIO is counted, and if neither of the out-of-synchronization signals 81 and 82 is input through the switch 8, the division ratio is 4, and if either one is input, the division ratio is 2. This is a frequency division counter that divides the frequency. Therefore, clock CL
5 becomes the same as the clock CL9 in FIG. 4 when the frequency division ratio is 4, and becomes two divided outputs when the frequency division ratio is 2.

Buffer memory5. -6, data string DI, D2 is clock CL3. The data string D3 . This is a buffer memory with a variable number of stages from which D4 is sequentially read. The number of stages is 4 if the out-of-synchronization signal 31 or 32 is not input, and 2 if it is input.

If the frame synchronization of the frame synchronization circuits 1 and 2 is normal and neither of the out-of-synchronization signals 31 and 82 is output, the embodiment shown in FIG. 1 is exactly the same as the conventional example shown in FIG. The data string DI is operated under the control of the switching control signal S3.

Selectively output one of D2 as a data string D5,
The timing difference between the data strings DI and D2 is the clock CL.
If it is within two cycles of I and CL2, no bit error will occur due to switching of the switch 7 that makes this selection.The clock CL6, which is the output of VCOIO, is the data string D.
The clock is set to 5.

If the switch 7 selects the data string D3 and the data string Dl becomes abnormal and the frame synchronization circuit 1 generates an out-of-synchronization signal, the phase of the frame pulse P1 changes drastically and the frequency is divided. Counter 3 is correctly clocked CL3
cannot be output, and writing to the buffer memory 5 becomes abnormal, and as a result, the phase of the data string D5 fluctuates irregularly throughout the retention period of each stage of the buffer memory 5. Shigashi,
In this case, the out-of-synchronization signal sl is output, the frequency division ratio of the frequency division counters 3 and 11 becomes 2, the number of 50 stages of the buffer memory becomes 2 stages, and the holding period of each stage of the buffer memory 5 becomes 2 cycles of the clock CLI. Therefore, the change range of the irregular phase fluctuation of the data string D5 is two cycles of the clock CLI. When the switch 7 selects the data string D4 and the frame synchronization circuit 2 generates an out-of-synchronization signal, the range of irregular phase fluctuation of the data string D5 is also the period of the clock CL202. In the conventional example shown in FIG. 4, these change ranges are four cycles, CLI and CL2, whereas in the embodiment shown in FIG. 1, they are narrowed by half, to two cycles.

Note that the clocks CLI and CL2 are also input to the switch 9,
The clock CLI or CL2 selected and outputted by the switch 9 and the clock CL6 (output of vColo) are connected to the phase comparator 1.
2 can also be input to control VCOIO.

In the above explanation, it is assumed that the number of clocks in one frame of the data strings Di and D2 is divisible by the frequency division ratios (4 and 2) of the frequency division counters 3, 4, and 11, but if it is not divisible, the frame pulse PL .

It is necessary to use the N-divided pulse of P2 instead of the frame pulses PL and P2 so that the number of N-frame clocks of the data strings Di and D2 is divisible by the division ratio of the frequency division counters 3 and 4.11. . Regarding this matter, the above-mentioned
It is detailed in Japanese Patent No. 7-32535, so please refer to it if necessary.

The configuration and operation of the embodiment shown in FIG. 1 have been described above.

Next, an application of the embodiment shown in FIG. 1 will be explained.

FIG. 2 is a block diagram showing the first application example.

21 is a transmitting end wireless terminal station, 22 is a receiving end wireless terminal station, and the transmitting end wireless terminal station 21 and the receiving end wireless terminal station 22 are connected by a working wireless line and one backup wireless line. has been done. These active and backup radio circuits are normally relayed by a plurality of intermediate relay stations, but are omitted in FIG. 2. Further, a lower-order wireless line (not shown) is connected to the receiving end wireless terminal station 22.

In the transmitting end wireless terminal station 21, 30 is a test pattern generator, and 40 to 4 are test pattern generators for converting the speed of the test pattern generated by the test pattern generator 30 or the data string input from the transmitting end carrier terminal station (not shown). Transmission signal processing device for inserting frame synchronization bits and other additional bits, 51 to 5
50 is a transmission distribution device that branches the data string outputted by the transmission signal processing devices 41 to 4k into two, and 50 is a transmission signal processing device 40.
A transmission switching device inputs the data string outputted by the transmission switching device 50 and one of the branch outputs of the transmission distribution devices 51 to 5 and selectively outputs one of them, and 60 is a backup radio line into which the data string outputted by the transmission switching device 50 is inputted. The transmitting devices 61 to 6 are transmitting devices for the working wireless lines which input the other branch outputs to the transmission distribution devices 51 to 5. In the receiving end wireless terminal station 22, 70 is a receiving device for the backup wireless line, 71 to 7 are receiving devices for the working wireless line, and 80 is a receiving device that branches the data string demodulated and output by the receiving device 70 and its clock. The distribution devices 81 to 8 receive the data strings demodulated and outputted by the receivers 71 to 7k, their clocks, and the branch output of the reception distribution device 80, and are synchronized to selectively output one of the data strings and the clock. The switching devices 90 to 9 include a received signal processing device that inputs the data string outputted by the receiving distribution device 80 or the synchronous switching devices 81 to 8k and its clock, extracts additional bits from the input data string, converts the speed, and outputs the same. 100 is a test pattern detector into which the data string outputted by the received signal processing device 90 is input. The data strings output by the received signal processing devices 91 to 9k are respectively input to lower-order wireless lines. The embodiment shown in FIG. 1 is used as the synchronous switching devices 81-8.

When the backup wireless line is on standby, the transmission switching device 50 selectively outputs the data string output by the transmission signal processing device 40, and the test pattern generated by the test pattern generator 30 is detected via the backup wireless line. The signal is input to the device 100 and used for monitoring the quality of the backup wireless line.

When the working wireless line from the transmitting device 61 to the receiving device 71 is normal, the synchronization switching device 81 selectively outputs the data string output by the receiving device 71, and the transmitted signal processing device 4
The data string input to 1 is transmitted via the working wireless line and output from the received signal processing device 91.

When switching this working radio line to a backup radio line, a line switching control device (not shown) first controls the transmission line switching device 50 to selectively output the branch output of the transmission distribution device 51. As a result, the data string output from the transmission signal processing device 41 is input to the synchronous switching device 81 via the backup wireless line. Assuming that the data string via this backup wireless line is data string D1 in FIG. 1 and the data string via the working wireless line is data string D2, the switch 7 in FIG. 1 selects data string D4 before this line switching. This means that it is being output.

Since the transmission signal processing devices 40 and 41 insert the additional bits asynchronously with each other, when the transmission switching device 50 is switched, the frame synchronization bit of the data string D1 is changed from that inserted by the transmission signal processing device 40 to the transmission signal. Processing device 41
In place of the inserted frame, the synchronization of the frame synchronization circuit 1 is temporarily lost, and frame synchronization is established again after a while. After re-establishing the synchronization of the frame synchronization circuit 1, the line switching control device controls the switching control signal S3 to cause the switching device 7 to selectively output the data string D3, thereby completing the switching from the working radio line to the backup radio line. do. Transmission signal processing device 41
Since the fixed component of the propagation delay difference between the route via the working radio line and the route via the backup radio line from For example, the above line switching does not cause any bit errors.

Now, if the working wireless line is disconnected before line switching due to equipment failure etc., and the frame synchronization circuit 2 becomes out of synchronization,
As already mentioned, the phase of the data string D5 output by the synchronous switching device 81 fluctuates irregularly until the line switching to the backup wireless line is completed.

However, since the change range of this phase fluctuation is narrow, ie, two clock periods, the demodulator will not become out of clock synchronization in the radio line following the received signal processing device 91 in this case as well.

FIG. 3 is a block diagram showing a second application example of the embodiment shown in FIG. 1.

21 is the same transmitting end radio terminal station as in FIG. 2, and 23 is an intermediate relay station immediately below the transmitting end radio terminal station 21.

At intermediate relay station 23, 200 to 20k.

210 to 21 are receiving devices for diversity reception, 30
0 to 30 are synchronous switching devices, and 400 to 40 are transmitting devices. The embodiment shown in FIG.
Used as 0.

The receiving devices 200 and 210 are both receiving devices for a backup wireless line, receive and demodulate the radio waves sent out by the transmitting device 60 of the sending end wireless terminal station 21, and output a data string and its clock. Synchronous switching device 300 is controlled by a diversity control device (not shown) to select and output a data string output by either receiving device 200 or 210.

The transmitting device 400 is a transmitting device of a backup wireless line that inputs the data string selectively outputted by the synchronous switching device 300.

The diversity control device monitors the received S/N of the receiving device 200° 210 or the error rate of the demodulated data string, and monitors the error rate of the data string selectively output by the synchronization switching device 300 or the received S/N corresponding to this data string. /N deteriorates below a certain threshold, and if the error rate of the other data stream or the received S/N corresponding to that data stream is better than the above threshold, the switching control signal S3 in FIG. The synchronous switching device 300 is controlled to switch the data string to be selectively output.

If the fluctuation component of the propagation delay difference between the two propagation paths from the transmitter 60 to the receivers 200 and 210 is within two clock cycles, no bit error will occur due to this switching. In the synchronization switching device 300, when the frame synchronization of the data string being selectively output is lost, the phase of the output data string fluctuates irregularly.

However, since the change range of this phase fluctuation is narrow, ie, two clock cycles, the demodulator in the receiving device of the backup radio channel at the lower intermediate relay station and the receiving end radio terminal station (none of which are shown) detects clock synchronization. However, when the transmission switching device 50 is switched at the sending end wireless terminal station 21 to switch from the working line to the protection line, the second
As already mentioned in the explanation of the application example shown in the figure, since the frame synchronization bit of the data string transmitted on the backup radio line changes, both of the two frame synchronization circuits in the synchronization switching device 300 temporarily become out of synchronization.

In this case as well, the demodulator in the lower receiving device does not lose clock synchronization, as in the case of diversity switching described above.

The receiving devices 200, 210, the synchronous switching device 300, and the transmitting device 400 relay the backup wireless line as described above.

The receiving devices 201 and 211, the synchronization switching device 301, and the transmitting device 401 similarly relay the working wireless line starting from the transmitting device 61 of the transmitting end wireless terminal station 21. The same applies below. Similarly to the above, even if the frame synchronization is lost in the synchronization switching device 301.30k, the demodulator does not become out of synchronization in the receiving device of the working wireless line following the transmitting device 401.40k.

〔Effect of the invention〕

As explained above, the synchronization switching device of the present invention reduces the number of stages of the buffer memory and shortens the retention period of each stage when the frame synchronization required to generate the write clock of the buffer memory is lost. It is possible to narrow the change range of irregular fluctuations in the phase of the output data that occur when the demodulator S clock of the subsequent wireless line is out of synchronization, and to prevent errors from occurring over a long period of time until the clock synchronization is restored. Furthermore, since there is no risk of clock synchronization being lost in the subsequent demodulator, there is an effect that the number of stages of buffer memory can be increased and the dynamic range of synchronization switching can be widened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronous switching device of the present invention, FIG. 2 is a block diagram showing a first application example of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of a conventional synchronous switching device. 1.2... Frame synchronization circuit, 3, 4, 11.
...Divide counter, 5, 6...Buffer memory, 7.8, 9...Switcher, 10...
...VCo, 12... Phase comparator, 13...
...Low pass filter. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] The first and second data strings are transmitted in frame synchronization with the first and second data strings, which are respective received data strings, in which a transmission data string including a frame synchronization bit is transmitted over two wireless transmission paths. a first outputting a frame pulse and outputting first and second out-of-sync signals while out of frame alignment;
and a second frame synchronization circuit, a predetermined first fraction that is reset by the first frame pulse or its frequency divided pulse and is an integer of 2 or more when the first desynchronization signal is not input. The clock of the first data stream is divided by a frequency ratio, and when the first out-of-synchronization signal is input, a predetermined second fraction is divided by a positive integer less than the first frequency division ratio. The clock of the first data string is divided by the frequency ratio, and the clock of the first or second data string is divided by the frequency ratio.
a first frequency division counter that outputs first frequency division outputs whose phases are sequentially shifted by a number equal to the frequency division ratio; and a first frequency division counter that is reset by the second frame pulse or its frequency division pulse;
When the out-of-cycle signal is not input, the clock of the second data string is divided by the first frequency division ratio, and when the second out-of-sync signal is input, the clock of the second data string is divided by the second frequency division ratio. a second frequency division counter that divides the clock of the second data string by a ratio and outputs a second frequency division output whose phase is sequentially shifted by a number equal to the first or second frequency division ratio; , a first buffer memory whose number of stages is equal to the frequency division ratio of the first frequency division counter, and in which the first data string is sequentially written to each stage using each of the first frequency division outputs as a write clock; , a second buffer memory whose number of stages is equal to the frequency division ratio of the second frequency division counter, and in which the second data string is sequentially written to each stage using each of the second frequency division outputs as a write clock; , a first switch that selects and outputs one of the third and fourth data strings read from the first and second buffer memories using a common read clock; a second switch that selects and outputs one of the out-of-synchronization signals in correspondence with the selection of the first switch; and the third or fourth data string selected by the first switch. a phase-locked oscillator whose phase is synchronized with the clock of the first or second data string corresponding to the first or second data string; When neither is input, the frequency is divided by the first frequency division ratio, and when the first or second desynchronization signal is input from the second switch, the frequency is divided by the second frequency division ratio. a third frequency division counter that divides the frequency and outputs a third frequency division output whose phase is sequentially shifted by a number equal to the first or second frequency division ratio as the read clock; Synchronous switching device.