JPH01125062A - Frequency-voltage converting circuit - Google Patents

Abstract

PURPOSE:To eliminate the influence of noise occurring by calculating the frequencies of an inputted vertical and horizontal synchronizing signals by means of a microcomputer, D-A-converting their results to output a voltage signal, sorting the calculation results of the frequencies of the both synchronizing signals, and making the new calculation results new ones in case their frequencies of occurrence are high. CONSTITUTION:In the microcomputer 11, the frequencies of a vertical synchronizing signal and a horizontal synchronizing signal are calculated respectively. Upon compression of the calculation of horizontal synchronizing signal frequency, the result is stored as a counting COUNT 2. Thereafter, the both signals are compared with each other; in case the current counting COUNT 2 is different from the last counting COUNT 1, a counter CT1 corresponding to this value is incremented by one each time. When the value reaches a threshold S, all the counters CT1, CT2-CTn, CTX are cleared, then the data corresponding to the counting COUNT 2 at this very point of time is supplied from the microcomputer 11 to a latch circuit 12 and the data is therein latched. Accordingly, since no time constant circuit is necessary, the operation is stable even under temperature variation, and noise can be eliminated.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a frequency-voltage conversion circuit, and more specifically, to frequency separation of a synchronizing signal of a video display device that automatically follows the frequency of an input signal. The present invention relates to a frequency-voltage conversion circuit used in applications such as applications.

(Prior art) In video display devices such as television receivers, both vertical and horizontal synchronization signals are detected by frequency separation, and image display is performed using this as a reference. Therefore, the frequency of the input synchronization signal is tracked. In a type of device that performs a display operation using a so-called free-running oscillator, a frequency-voltage conversion circuit is used that converts the frequency of an input synchronizing signal into a voltage using a so-called free-running oscillator.

FIG. 4 is a circuit diagram showing the configuration of such a conventional frequency-voltage conversion circuit (hereinafter referred to as an F-V conversion circuit).

In the figure, 1 is a one-shot multi-by-break, a synchronizing signal is input to its signal input terminal IN, and a pulse signal is output from its signal output terminal OUT.

The period of the output pulse signal of the one-shot multivibrator 1 is determined by an oscillation time constant circuit composed of a resistor 2 and a capacitor 3.

The output pulse signal of the one-shot multivibrator l is divided by a voltage dividing resistor 4.5 and then sent to an output transistor 6.
is given on the basis of

A predetermined voltage is applied to the collector of the output transistor 6 via a load resistor 7. Further, this collector is connected to the frequency separation output terminal vO via an integral time constant resistor 8, and is also grounded via an integral time constant capacitor 9.

Further, the emitter of the output transistor 6 is directly grounded.

The operation of the conventional F-V conversion circuit having such a configuration is as follows.

Synchronous signal input terminal F! When a synchronizing signal is input to the signal input terminal IN of the one-shot multivibrator 1 from
A rectangular pulse signal with a pulse width determined by the resistor 2 and capacitor 3 is output from the signal output terminal 0υ of the one-shot multivibrator l. This rectangular pulse signal is voltage-divided by voltage-dividing resistors 4 and 5 and then applied to the base of an output transistor 6.

Since a predetermined voltage is applied to the collector of the output transistor 6 via the load resistor 7, when the output transistor 6 is in a conductive state, that is, the rectangular pulse output from the one-shot multivibrator 1 is at a high level. In this section, the voltage applied to the collector of the output transistor 6 is discharged to the ground terminal via the output transistor 6.

In other words, in the low level section of the rectangular pulse output from the one-shot multivibrator 1, the predetermined voltage applied to the collector of the output transistor 6 is integrated by the integration time constant resistor 8 and the integration time constant capacitor 9.

Now, the pulse width (width of the high level section) of the rectangular pulse output from the one-shot multivibrator l is constant due to the action of the resistor 2 and capacitor 3, and the number of nottles corresponds to the frequency of the input synchronizing signal. Therefore, the deity in each cycle of this pulse signal changes. This allows the integral time constant condenser +
Since the ratio between the charging time and the discharging time of 9 changes, as a result, the signal input terminal I of the one-shot multivibrator 1
The frequency of the synchronizing signal input to N is detected as a change in the voltage across the integral time constant capacitor 9 at the frequency separation output terminal vO.

[Problem to be Solved by the Invention 3] In the conventional F-V conversion circuit as described above, the horizontal synchronization signal is not input during the period of the vertical synchronization signal (its duration is longer than the horizontal synchronization signal). In this case, the output is dominated by the vertical synchronization signal, causing an abnormality in the F-V conversion output of horizontal synchronization decoding. Further, in order to eliminate the influence of noise, it is necessary to set a large integration time constant, but in this case, a problem arises in that the responsiveness deteriorates.

The present invention was made in view of these circumstances, and
To provide a frequency-voltage conversion circuit that can quickly respond to frequency changes in an input signal and can sufficiently eliminate noise by devising software for pulse counting in a micro combinator. With the goal.

[Means for Solving the Problems] The frequency-voltage conversion circuit of the present invention counts the frequencies of input vertical and horizontal synchronizing signals using a microcomputer, converts the results into D/A, and outputs a voltage signal. At the same time, the frequency counting results of both synchronizing signals are classified, and if each classification result has a high frequency, it is used as a new frequency counting result to eliminate the influence of noise generation.

[Effect]

In the frequency-voltage conversion circuit of the present invention, the frequency counts of the input vertical and knee synchronization signals are D/A converted and a voltage signal is output, and if noise occurs, the count results are is excluded.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.

FIG. 1 shows a frequency-voltage conversion circuit (hereinafter referred to as F-V) of the present invention.
1 is a circuit diagram showing the configuration of a converter circuit (referred to as a conversion circuit), in which a CPU,
Microcomputer 11 including ROM, RAM, etc.
, latch circuit 12.13 and 0/A converter 14.1
It is composed of 5 etc.

The microcomputer 11 has two input terminals ■h■2
A horizontal synchronizing signal is input to the first input terminal (2), a vertical synchronizing signal is input to the second input terminal (2), and the frequency of these resynchronization signals is counted. In addition to operating as a counting means, it also has the function of eliminating noise mixed in during frequency counting, as will be described later.

Data for F-V conversion is output from output terminals Q, -Qn of this microcomputer 11, and trigger pulses for launch circuits 12 and 13 are output from Tl+T2, respectively.

The output terminals Q, -Qn of the microcomputer 11 are connected to the input terminals 01 - On of the launch circuit 12.13, respectively, and the output terminals T, T2 of the microcomputer 11 are connected to the trigger terminal T, respectively. has been done. Output terminals O1 to Qn of both latch circuits 12 and 13
The F-■ conversion data inputted to the respective input terminals D1xDn and launched is outputted from the input terminals D1xDn.

Each input terminal of both/A converters 14 and 15, ~Dn
Output terminals Q, -Qn of both circuits 12.

FIG. 2 is a schematic diagram showing a method of counting vertical synchronization signals and horizontal synchronization signals by the microcomputer 11. Specifically,
A vertical synchronizing signal shown in FIG. 2(a) is input to the input terminal (2) of the microcomputer 11, and a horizontal synchronizing signal shown in FIG.

Inside the microcomputer 11, the frequencies of the vertical synchronization signal and the horizontal synchronization signal are counted, respectively, using the internal pulses shown in FIG. 2(b) that depend on the system clock serving as its operating reference. That is, microcomputer 1
The frequency of the vertical synchronizing signal is counted by counting the number of internal pulses of the microcomputer 11 within one period of the vertical synchronizing signal inputted to the input terminal I2 of 1, and the frequency of the vertical synchronizing signal is counted for a certain period in one period of the vertical synchronizing signal. P is specified by an internal pulse of the microcomputer 11, and the frequency of the horizontal synchronizing signal is counted by counting the number of pulses of the horizontal synchronizing signal input to the input terminal 11 during that period.

FIG. 3 is a flowchart showing a processing procedure for D/A converting the frequencies of the vertical synchronization signal and horizontal synchronization signal counted as described above while eliminating noise.

Hereinafter, the procedure for processing the counting results will be explained with reference to the flowchart shown in FIG. Note that the flowchart in FIG. 3 shows the processing procedure regarding the horizontal synchronization signal,
The vertical synchronization signal processing procedure is also similar.

The counting of horizontal synchronization signals and the processing of the results are performed in synchronization with the vertical synchronization signals. Then, when the counting of the horizontal synchronizing signal frequency is completed, the counting result is the counted value C0UN.
Stored as T2. Note that the count value C0UNTI is the previous count value.

Next, the count value C0IJNT2 is the previous count value C0UNT
If the result is the same, the loop passage counter CTO is incremented by one. After this, the loop passage counter CTO is compared with a constant A (A>S). As a result, if it is determined that CTO≧A, each counter CTI, CT2 . ...After CTn and CTX are cleared, if it is determined that CTO<A again, the process returns to the process of directly storing the count result of the horizontal synchronization signal in the count value C0UNT2. As a result, the vertical synchronization signal becomes A+1
Each time an input is made to the microcomputer 11, each counter CTI, CT2 .・=CTn, CTX are cleared.

The above processing is performed when the current count value COυNT2 is equal to the previous count value C0UNTI, that is, when the frequency of the input horizontal synchronizing signal is constant and does not change.

In this case, from the microcomputer 11 to the latch circuit 1
Data output and lunch output to 2 are not performed.

That is, the data that was applied to the latch circuit 12 from the microcomputer 11 and latched at the time of counting the previous count value C0UNTI or before is still valid, and the voltage signal output from the D/A converter 14 remains constant. maintained.

On the other hand, if both count values C0IINTI and count value COυNT2 are different, the current count value C01lNT2 is sequentially changed to the value C
0IjNT1-1°C0UNT1+1. C0UNT1+
1. . . . The counters CTI, CT2 . ...C
The current count value C011NT2 is classified by incrementing Tn by 1, and if neither is the case, incrementing the counter CTX by 1.

Next, one of the counters CTI, CT2 . ...CTn, CTX are compared with a predetermined threshold S, and if the value of the counter is larger than the threshold S, all counters CTI, CT2
゜...After clearing CTn and CTX, the current count value C0UNT2 is stored as the previous count value C0tlNT1.

Then, the above-mentioned count value C0IINTI is decoded and D/
Data for A conversion is created and given to the latch circuit 12 to be latched. The data latched by the launch circuit 12 is converted into an analog signal, ie, a voltage signal, by the D/A converter 14 and output from the output terminal O.

That is, as mentioned above, if the current count value C0UNT2 is different from the previous count value C0UNTI, the counter CTI (or C10, . . . = CTn, CTX) corresponding to that value is incremented by 1, and the value becomes When the threshold S is reached, all counters C1. CT2. ...CTn,
After CTX is cleared, the current count value C01lN
Data corresponding to T2 is applied from the micro combinator 11 to the latch circuit 12 and latched, and the analog-converted voltage signal is output from the D/A converter 14.

Also, counter CTI (or C70, -CTn, CT
If the value of X) is less than or equal to the threshold S, the loop passing p counter CTO is incremented by 1, and the same processing as in the case where the count value COυNT2 and the count value COυNTI are equal is performed.

By the way, in the case of noise generation, the current count value C0UN
Of course, T2 and the previous count value CO[lNT1 are included. In this case, since the count value C0UNT2 generally changes randomly each time, the counter CT to be incremented
1. C70,=CTn,CTX are different each time. In other words, since the increments of each counter due to noise generation are distributed, any particular counter C↑1
, C70,...The probability that the values of CTn, CTX increase significantly during ^+1 processing is very low, but it is not due to noise, but due to the frequency of the input signal. If the frequency actually changes, the value of one of the counters corresponding to the frequency after the change will reach the maximum A.
Significant increase during +1 treatment. As a result, since the value of the counter exceeds the threshold value S, it is possible to determine that it is not noise.

That is, counter CT1. C70,...CTn, CTX
By preparing a sufficiently large number of , it becomes possible to eliminate noise.

Furthermore, since the data for the analog output of the D/A converter 14 is latched in the latch circuit 12, the horizontal synchronization signal from the D/A converter 14 can be output even during the period in which there is no horizontal synchronization signal during the output period of the vertical synchronization signal. The output of the voltage signal corresponding to the signal is maintained.

Note that the procedure for counting the frequency of the vertical synchronizing signal is to count the frequency of the microcomputer 11 during one period of the vertical synchronizing signal instead of counting the horizontal synchronizing signal when counting the frequency of the horizontal synchronizing signal shown in FIG. If internal pulses are counted, the same processing procedure will be used.

〔Effect of the invention〕

As described in detail above, the F-V conversion circuit of the present invention does not require a time constant circuit composed of resistors, capacitors, etc., so it is stable against temperature changes, and also reduces noise. Since a process that can eliminate noise is adopted, a +F-V conversion circuit that is stable against noise can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the p-v conversion circuit according to the present invention, and FIG. 2 is a timing diagram showing the relationship between the vertical synchronization signal and horizontal synchronization signal to be processed and the pulses used for counting. FIG. 3 is a flowchart showing the processing procedure performed by the apparatus of the present invention, and FIG. 4 is a circuit diagram showing the configuration of a conventional p-v conversion circuit. 11...Microcomputer 12.13...Latch circuit 14.15...D/A converter
The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. In a frequency-voltage conversion circuit of a video display device that converts and outputs voltage signals corresponding to the frequencies of input vertical and horizontal synchronizing signals, a reference pulse generation circuit; a first frequency counting means for counting the number of reference pulses during one cycle; a means for obtaining frequency-voltage conversion data for a vertical synchronizing signal corresponding to the counting result; a second frequency counting means for counting the number of pulses of the horizontal synchronizing signal based on the reference pulse in a predetermined period; means for obtaining frequency-voltage conversion data for the horizontal synchronizing signal corresponding to the counting result; means for classifying and counting the counting results of the first and second frequency counting means, and when the count values of these counting means exceed a predetermined value, the frequency counting means corresponding to the counting means Based on the count value, the frequency -
A microcomputer that corrects voltage conversion data, a latch circuit that latches the frequency-voltage conversion output of the microcomputer, and a D/A converter that converts the data latched in the latch circuit into a voltage signal and outputs it. A frequency-voltage conversion circuit comprising: