JPH01123330A - Data processor - Google Patents

Abstract

PURPOSE:To shorten execution cycles for all the tasks by increasing states in the machine cycle of a computing element for 1 state and executing a writing after a reading when both input and output of the computing element generate for the same register. CONSTITUTION:A multi-port register file 17 is provided by connecting respective 3 transistors for each of a flip flop and its cross-connecting point, and a gate line and a word line are provided independently for 3 ports so that a computing element 12 can simultaneously access three different registers from the multi-port register file 17. At the same time, the title device is composed so that the access becomes possible by adding the necessary minimum states with a timing control circuit 18 even when the register for the reading is the same as that for the writing. Thus, the machine cycle of instructing execution can be reduced, a task switching can be executed for every machine cycle when a multi-task is processed with a time division, and the processing of all the tasks can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processor equipped with a multi-vote register file that executes multi-task processing at high speed.

[Conventional technology]

FIG. 6 is a block diagram of a conventional data processor, in which 10 is a storage device for storing programs;
1 is an arithmetic unit, and 14 is a register file in which arithmetic data is stored. Reference numeral 16 denotes a control unit which controls the arithmetic unit 12 and the register file 14 according to the contents of the program read from the storage device 10 to execute arithmetic operations.

FIG. 7 is a configuration diagram of a conventional register file 14.
This shows normal static RAM. In the same figure, 20
is the address line used to specify the reno star,
22 is a data line to which write and read data for the register is added. 24 is a register file select terminal used for discrimination from other data storage devices%
26 is a write terminal, and 28 is an output enable terminal used as a read terminal for the register file.

30 is an address buffer, and an address decoder 32
The signal amplification operation is performed so that the signal can be sufficiently driven. Reference numeral 34 indicates a word line used to select the memory section 40, and 36 and 38 indicate data lines, which are logically inverted to each other, and the memory contents differentially amplified by the sense angle 42 are taken out.

44 is an output data buffer that drives the data line 22, and 46 is an input data buffer that completely controls sending of write data to the data line.

FIG. 8 representatively shows a part of a conventional memory section 40, in which the first to fourth transistors 50, 52, 54, 56 are 0.
The 5th and 6th transistors 58 and 60 of the MO8 flip-flop are connected to the word line 34 and to the data line 36.38 at the cross-connection point 62 and 64 of the flip-flop to select the cell. , used for reading and writing.

Next, the operation will be explained. FIG. 9 is a diagram showing the operation of a conventional data processor when a calculation result using the stored contents of Resota X and Resota Y is stored in Resota Z. In the machine cycle 70, an instruction is read from the storage device [10, and the control unit 16, in the case of this embodiment,
It is decoded to store the calculation result of the memory contents of Resostar Ru. That is, the control unit 16 gives the address of register X in the register file 14 through the address line 20, passes through the address buffer 30, and decodes it by the address decoder 32. Then, one word line 34 is selected and the darts of the 5th and 6th transistors 58 and 60 are set to 1H'' level.The 5th and 6th transistors 58 and 60 are conductive, and the free lag flop is turned on. , the memory contents of the resistor X, which is in the OFF state, are transmitted to the data line 36. , is input to the computing unit 12. In the next machine cycle 74, the memory contents of the Resota Y are read out in the same way as in the Resota X, and input to the computing unit 12. In the next machine cycle 76, the contents of the memory of the Resota An arithmetic operation using the memory contents is executed by the arithmetic unit 12,
In the next machine cycle 78, the result of the operation is entered into the register zK$ of the register file 14 as follows. The calculation result is converted into binary values of positive and negative logic by the calculation unit 12 via the data line 22 and the input data path sofa 46, and is applied to the data lines 36 and 38.

In part, the address of the resistor 2 is applied to the address line 20 via the control unit 16, passed through the address buffer 30, and decoded by the address decoder 32 to select one word line 34. .6
0 is made conductive and electrically connected to the cross connection points 64 and 62 of the data 1 lines 36 and 38e flip-flops, and the logic of the 7 flip-flops is set by the signal level of the data lines 36 and 38. In this way, writing of the calculation results to the reloader 2 is completed.

[Problem that the invention seeks to solve]

Conventional data processors are configured as described above, so in order to time-share multiple tasks that require real-time processing, the method of switching tasks every machine cycle as shown in FIG. It is impossible to execute because simultaneous write processing is not possible, and the first
As shown in FIG. 1, it is necessary to perform time-sharing processing for each instruction or to switch tasks for each series of programs, resulting in problems such as an increase in the execution cycle of all tasks.

The present invention was made in order to solve the above problems, and it provides a data processor that shortens the execution cycle of all tasks by processing multi-task tasks in each machine cycle. The purpose is to obtain.

[Failure to solve the problem]

In the data processor according to the present invention, each memory cell of the renostar file is configured with a flip-flop and three pairs of transistors connected to a pair of cross-connections thereof, and two transistors are normally connected to the arithmetic unit. When reading from a Reso star and writing to one Reso star at the same time, and when the input and output of an arithmetic unit occur to the same Reso star, the state within that machine cycle is increased by l state, and the timing for writing after reading is performed. It is equipped with a control circuit.

[Effect]

The data processor of the present invention has a renostar file that can be accessed through multiple ports, so even when data processing is performed in a pipeline, the renostar file can be used simultaneously, and machine cycles are required to execute multitasking. This enables time-sharing calculations for each time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the overall configuration of a data processor according to the present invention, and parts with the same symbols as in FIG. 6 are the same as those in the conventional example.
Or the corresponding part will be shown and the explanation thereof will be omitted. In this embodiment, instead of the renosta file 14, a multi-hode renosta file 17, which will be described later, stores calculation data, and a timing control circuit 18 for timing the input and output of the multi-hode renosta file 17 is provided. 80 is the first address line of the first port, 82 is the first data line of the first port, 84 is the second address line of the second port, and 86 is the second data line of the second port. line 88 is the third address line of the third port, and 90 is the third data line of the third port. 1st to 3rd
The address lines 80, 84, 88 and the first to third data lines 82, 8'6, 90 are connected between the multiport data file 17 and the timing control circuit 18. Further, the arithmetic unit 12 and the timing control circuit 18 have three buses for two inputs and one output, that is, the first to third buses.
The control unit 16 is connected to the arithmetic unit 12 and the timing control circuit 18 by control signal lines.

FIG. 2 is a diagram showing the internal structure of the multiport data file 17. In Figure 2, the number, for example 80
The symbols (a)...(n) appended to the lines indicate each address line of the first address line 80, and the symbols AOA...AnA paired with the symbols (a)...(n) indicate the respective addresses transmitted by the first address line. This shows the signal that will be sent. Thus, for example, the first address line 80 is the address line 8
Consisting of 0(a)...80(n), AOA, AI
A...AnA is an address signal transmitted on each line. Since the other parts are the same, the details will be omitted below. Also, the parts with the same symbols as in FIG. 1 are the same parts, and the explanation thereof will be omitted entirely. Reference numerals 92, 94, and 96 are renosta file selection lines that transmit the inverted signals of the renosta file selection signals for the first to third ports. 98 is a write signal line that transmits an inverted signal WRA of the write signal of the first port; 10
0\i Write timing signal TAt - Write timing line for transmission. 102 is a timing gate that multiplies the input dehood line and the write timing line 100, and 104 is a multi-memory unit whose details are shown in FIG.

First, the connection of the first port will be explained.

The first address line 80 is connected to the first address buffer 3
It is connected to the input terminal of the first address decoder 32a via 0a'i. The lead line from the output terminal of the first address decoder 32a is connected to the timing line lOO by AND dart at timing r-) 102, and is connected from the timing gate 102 to the first word line 106 in the multi-memory section 104. There is. The V soster file selection line 92 is connected to the first address buffer 30a and the address decoder 32a via an inverter, and receives a renostar file selection signal C8A for selecting them.
to transmit. Further, the timing dart 102 opens the y-t only when there is a timing signal TA. The first data line 82 is connected via the input data buffer 46 to a pair of first data lines 108 and 110 that transmit mutually inverted signals in the multi-memory section 104. In addition, the output select file line 92 and the write signal line 98 connected through an inverter are connected to a negative input type ANDf-
It is connected to the input data puffer 46 via a port.

As a result, the input data path sofa 46 becomes active only when the renostar file selection signal C8A and the write signal WRA are generated simultaneously.

Next, the connection of the second port will be explained. The second address line 84 is connected to the input terminal of the second address decoder 32b via the second address buffer 30bt. A lead line from the output terminal of the second address decoder 32b is connected to a second word line 112 in the multi-memory section 104. Furthermore, a pair of second data lines 114 and 116 that transmit mutually inverted signals in the multi-memory section 104 are connected to the input terminal of the second port sense angle 42b. Sense amplifier 4 for 2nd port
The output terminal 2b is led out by a second data line 86 via the second boat output buffer 44b. Furthermore, the Renostar file selection line 94 is connected via an inverter to the second address buffer 30b, the second address decoder 32b, the second port sense amplifier 42b, and the second port output buffer 44b, and receives the Renostar file selection signal. Select them only when C3B occurs.

Next, the connection of the third port will be explained, but since it is similar to the connection of the second port, only the outline will be described.

30cij a third address buffer; 32C a third address decoder; 118 a third word line in the multi-memory section 104; 120 and 122 a third data line pair; 42c a third boat sense amplifier. , 44c is an output buffer for the third port.The first port is for reading, and the second and third ports are for reading.

FIG. 3 is a partial configuration diagram representatively showing the multi-memory section 104. In the same figure, the multi-memory section 10
The structure of three arbitrary memory cells using a data line in common among three arbitrary renosters in a plurality of renosters in four is shown.

106x, 106y, 106z are 106a・-
Three first word lines (for first port) of EE in 106n, 112x, 112y, 112zl
d any three second words of 112a-...112n? f@(for 2nd port), 118x, 118y,
118z is any three third word lines (for the third word line, t?-to) among 118a . . . 118n. Three pairs of first to third data lines 108, 110°114.11
Reference numerals 6, 120, and 122 indicate each pair of the first S-third data lines, d j A , and 1 .

Transmit data at djB, djB, djC, and punishment (where, j is any value from 0 to n). 57 is 1st-4th
0M composed of transistors 50, 52, 54.56
Flip-flops of O8 structure, 62, 64 are cross-connection point pairs (input/output terminal pairs) of flip-flop 57, 130 and 132, l 34 and 136 degrees, 138 and 140 are three pairs of transistors (first - third transistor pair), each one end of which is connected to the cross-connection pair 62,64 of the flip-flop 57, and each other end connected to the three pairs of data lines 10.
8 and 110 degrees, 114 and 116, 120 and 122 are connected. 3 pairs of transistors 130, 132, 134
Six pairs of darts 136, 138 and 140 are commonly connected to three word lines 106x, 112X and 118x, respectively. One memory cell is configured with this configuration. The structures of the remaining two memory cells are the same, so they are indicated by broken lines and are not shown. If arbitrary three renosters among a large number of renosters in the multi-memory unit 104 are designated as registers X, Y, and 2, then one memory cell of each of them is shown, for example, in order from the top.

FIG. 4 is a diagram for explaining the operation of the data grosser according to the present invention, and shows a case where tasks 1 to 4 are sequentially processed in a time-sharing manner. 160, 162°164.16
61d machine cycle, and in machine cycle 166, the instruction fetch of task 4, reading the contents of task 3's renostar executed simultaneously under control.

FIG. 5 is a timing chart showing the operation of the timing control circuit 18. In the figure, F0 is an inverted signal of the file selection and readout signal of the second port, which is applied to the Renostafail selection line 94, and 172 is an inverted signal of the file selection and readout signal of the third port. , applied to registerf write signal line 98, 1
76 is a write timing signal TA of the first port, which is applied to the write timing line lOO.

Next, the main parts of the operation will be explained. To read the contents of register X, the designation address of register
The second word line 112x is then decoded to select the second word line 112x. As a result, the transistors 134 and 136 of the second transistor pair become conductive, and the second data dl14, 1
The stored contents are read out at 16, amplified by the sense amplifier 42b for the WJ21 port, and guided to the timing control circuit 8 via the second data line 86 via the output buffer 44b for the second port. Similarly, reading the contents of register Y is performed using a third If-to. In this case, the designated address of register Y is sent to the third address line 88 of the third port, and the third address buffer 30c and the 317th address decoder 32cf
The third word line 1.183r is decoded through i-, and the stored contents of the register Y are read out to the third data line 120.122. The data read from these registers X and Y are transmitted to the arithmetic unit 12 through the timing control circuit 18. In addition, in the same manner as above, the operation of writing the results of calculations by the calculation unit 12 to the register Z of all the multiport register files 17 by using the stored data already transmitted from the multiport data file 17 is performed by first register designation. address signal is the first
address line 80, is decoded via the first address buffer 30a and the first address decoder 32a, and is guided to the timing dart lO2. If the address of register 2 is different from the address of register X or register Y, simultaneous parallel processing of reading and writing is possible, so as shown in FIG. At the L'' level, that is, at the H'' level of the file selection and read signal, the write timing signal 176a is set to the write timing line 10.
0 is applied, and the designation address of the register 2 is transmitted to the first word 1106zif by the timing dart 102, and is also transmitted by the first data line 82 from the arithmetic unit 12 via the timing control circuit 18. The data resulting from the calculation are converted into a pair of inverted states via the input data path sofa 46 by the write signal 174a of the write signal line 98, and then sent to the multi-memory unit 10.
4 data line 108. ll0K is applied and stored in the flip-flop and stored in register 2. In this case, Renometa X. Reading and writing of Y and Y can be executed at the same time. Also, even if the addresses of registers X and Y are the same, for example, the second word line 112X
and the third word line 118x are simultaneously selected. Third
transistor pair transistor resistors 134, 136.13
8°140 is made conductive to transfer the memory contents of the flip-flop to the second and third data lines 114, 116, 120°12.
This enables simultaneous reading of the same Nostar. In the above case, reading the storage contents from registers X and Y and writing data to register 2 can be executed at the same time.

If the address of register Z of multi-horde register file 17 is the same as the address of either renostar is automatically generated by the register X and applied to the write timing line 100 as the write timing signal 170b.
Immediately after the stored contents of Y are retrieved, writing of the calculation result to the register 2 is completed. In this case as well, the timing f-t 10 is provided after the first address decoder 32a.
2 is provided, the operating time of the first address decoder 32a for write access to the multi-port renosta file 17 can be taken during the read state of the memory contents from the renostars X and Y. can be finished early. As described above, traps and calculations are performed by the arithmetic unit 12, for example, in machine cycle 166 in Figure 84.
The reading of instruction fetch is performed by the storage device ft1o and the control unit 1.
Since the machine cycle is performed in 6 intervals, the machine cycles from Task 1 to Task 4 can be performed at the same time.

〔Effect of the invention〕

As described above, according to the present invention, a multi-port renostaf aisle is connected to each of the prep frogs and their cross-connection points with three transistors to connect the gate line and the word line f.
: 3 ports are provided independently, allowing simultaneous access to three different renostas from the arithmetic unit multi-port renosta file, and even when the read and write renostars are the same, the timing control circuit allows for the minimum required state. Since it is configured so that it can be accessed by adding it, it is possible to reduce the machine cycles for executing instructions, and when processing multi-tasks in a time-sharing manner, it is possible to switch tasks in each machine cycle, so that all tasks can be processed. This has the effect of producing something that can be done at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processor equipped with a multi-t gate renostar file according to an embodiment of the present invention;
3 is a partial configuration diagram of an embodiment of the multi-memory section, FIG. 4 is an explanatory diagram of the operation of a data processor according to an embodiment of the present invention, and FIG. FIG. 5 is an explanatory diagram of the operation of a timing control circuit according to an embodiment of the present invention, FIG. 6 is a configuration diagram of a conventional data processor, and FIG. 7 is a configuration diagram of a conventional renostar file.
FIG. 8 is a partial configuration diagram of a conventional memory section, FIG. 9 is an explanatory diagram of the operation of a conventional data processor, FIG. 1O is an explanatory diagram of time-division multitasking processing per machine cycle, and FIG. It is an explanatory diagram of task processing. In the figure, 10...Storage device, 12...Arithmetic unit, 16...
... ttttll1 part, 17... Multiport Renostafail, 18... Timing control circuit, 30...
・Address buffer, 32...Address decoder, 4
2...Sense angle, 44...Output data buffer, 46...Input data puffer, 50, 52, 54.
56... First to fourth transformer, 57... Prep frog, 62.64... Cross connection point, 80, 84
．． 90...first to third address lines, 82, 86
．． 88...first to third data lines, 104...
Multi-memory section, 106, 112, 118...first to
Third word line, 108, 110, 114, 116, 1
20°122...first to third data lines, 130,1
32゜134.136,138,140...Transosta. In addition, the same symbols in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] In a data processor that uses flip-flops as static random access memory and has a register file that stores data for calculations and an arithmetic unit that performs calculations using data transferred from the register file, the register file is stored in each of the flip-flops. three pairs of transistors each having one end connected to a pair of cross-connections which are input/output terminals of the transistors, three pairs of data lines connected to the other ends of the transistors, and three words to which the gates of the transistor pairs are connected. The line is made into a multi-port with a memory cell structure, and the arithmetic unit uses two of the three pairs of data lines for input and the remaining one pair for output, and reads data from the register file and sends it to the register file. A data processor comprising: a timing control circuit for executing a data write after reading data from the register file when executing an instruction in which the data write refers to the same register in the register file.