JPH01120994A - Method and equipment for monitoring sensor output - Google Patents

Abstract

PURPOSE:To improve a sensor output fetch speed to a CDU and to reduce the number of wires by arranging a peripheral processing unit LDU to each of plural sensors and connecting the LDUs in series in a ring form via the central processing unit CDU corresponding to a controller. CONSTITUTION:An identification code ID to specify its own LDU is assigned to a CDU 30 in LDUs 41-4n. Then in the LDUs 41-4n, if a sensor 22 is turned off to on for example, the output of the sensor 22 is fetched in a first-in first-out(FIFO) buffer 403 immediately together with the ID code assigned to the LDU 42. A transmission circuit 406 applies required processing such as modulation to the inputted signal and transfers the result to the LDU 43 of the next stage via a communication medium 50. The CDU 30 decomposes the fetched signal into an ID code and a sensor output and gives the converted address and the sensor output to a machine controller 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a system for centrally monitoring sensor outputs of various sensors used in various industrial machines, NC machines, automatic guided vehicles, robots, etc. using a controller. The present invention relates to a method and apparatus for monitoring sensor output suitable for the purpose of monitoring sensor output.

rPrior art] In order to centrally monitor the sensor outputs as described above, conventionally, the above-mentioned controller (often a programmable sequencer is used) is provided with input terminals corresponding to the number of sensors, and these terminals are connected to each other. Each sensor was connected directly. As a result, the number of wires increases significantly, which inevitably leads to difficulties in wiring work and maintenance, as well as inconvenience in handling.

Therefore, recently, peripheral processing devices have been installed to indirectly manage each of the plurality of sensors, and a central processing device has been installed to correspond to the control controller. Attempts have also been made to connect these peripheral processing devices in series in a ring via an IIL processing device to reduce the amount of wiring. FIG. 7 does not show the overall configuration of such a sensor output monitoring device.

That is, in this FIG. 7, 10 is a machine controller that centrally controls the target Ia machine as the control controller, 21 to 2n are the above sensors arranged in each part of the machine, and 30 is a machine controller. The above-mentioned central processing unit (hereinafter referred to as CDU), which is arranged in 10 and centrally monitors the sensor outputs of these sensors 21 to 2n;
4n is the peripheral section 1! which is arranged corresponding to each of the plurality of sensors 21 to 2n and relays the output of each sensor to and from the CDU 3O. I! As described above, in this sensor output monitor %fPl, the two CDUs 3O and LDUs 41 to 4n are connected in series in a ring shape as shown in FIG. 7. Note that 50 is a communication medium interposed between these CDU3O and LDU41 to 4n, and 50 is a communication medium interposed between these CDU3O and LDU4n.
When the communication between 1 and 4n is carried out by optical communication via an optical link, an optical fiber cable is used as the communication medium, and when the communication is carried out by telecommunication, the communication medium is Metal cables (twisted pair cables, coaxial cables, etc.) are used as such.

[Problem that the invention seeks to solve]

By adopting the configuration shown in Fig. 7,
The connection between the CDU and each sensor (more precisely, each DU) is achieved through only two signal lines (substantially one each due to the above-mentioned circular connection), each consisting of an input line and an output line. However, these devices typically
Since the sensor output of each sensor is sequentially captured while circulating U at a constant cycle, a new problem arises in that the sensor output capture cycle becomes longer in proportion to the number of sensors per loop. That is, a problem remains in terms of signal transmission speed.

For example, when ng LDUs are connected in series in a ring as shown in the g position shown in FIG. Let tk be the time it takes for tk to be transmitted, and let tk be the sampling period (circulation period), then the time it takes for the sensor output from the sensor corresponding to k to be taken into the CDU is tk. ≦τ≦T+tk ... (1).In other words, if the sensor output timing of the above sensor happens to match during the signal circulation, it is possible that the signal will be captured at the shortest time tk, but normally it will take some time from now. There will be some delay until T, and in the worst case, a delay of time T will occur.As mentioned above, this period time becomes longer in proportion to the number of sensors per loop, and When the number of signals is large, this time delay (transmission delay) cannot be ignored.

This invention can reduce the number of wires described above by arranging an LDU corresponding to each of a plurality of sensors, and connecting these LDUs in series in a ring through one CDU arranged corresponding to a controller. Based on this configuration, it is an object of the present invention to provide a sensor output monitoring method and apparatus that can further improve the signal transmission speed, that is, the sensor output acquisition speed to the controller (CDU).

[Means for solving problems]

In this invention, when there is a -H sensor output from any sensor, it must be taken into the controller (CDLI) as soon as possible in an electrical sense.
Most of the devices (used in machines, automated guided vehicles, robots, etc.) are linked to the movement of the machine or are activated when an abnormality occurs, and their states change electrically at high speed (for example, when the device is turned on). - It is not something that repeats (off),
In other words, focusing on the fact that it is not necessary to constantly monitor the outputs of these sensors, an identification code for identifying each LDU is assigned to each LDU, and only when a sensor output is generated from one of the sensors, the corresponding one is detected. The identification code of the LDLJ and the sensor output are asynchronously transferred to the CDU.

[Effect]

The probability that a plurality of sensors as described above change their states at the same time is extremely low. Further, even if it appears to be mechanically simultaneous, electrically there is variation in milliseconds (1IIS). Moreover, as mentioned above, it is highly unlikely that the same sensor would repeatedly change state on a millisecond basis. Therefore, by transferring sensor output to the CDU only when a sensor output is generated from one of the sensors as described above, it is possible to centrally monitor these sensor outputs. It becomes clear from which sensor the transferred sensor output is generated by checking the identification code transferred together with the identification code.

According to such a monitoring method, there is no transmission delay in sensor output due to the periodic time as described above, and in most cases, the sensor output is transmitted between the CDU and the corresponding L.
C in the shortest time determined by the series connection distance with DU
It will be incorporated into DU. Furthermore, regarding the sensor outputs generated during the transfer of such sensor outputs to the CDU, these sensor outputs can be further ranked in a predetermined manner within the corresponding LDU and transferred to the next stage. Collisions are also avoided.

〔Example〕

FIG. 1 shows an embodiment of a sensor output monitoring device according to the present invention.

However, Fig. 1 shows the sensor output monitoring device shown in
Assuming the configuration shown in the figure, each LDU 41
This shows an example of the internal configuration of ~4n. Of course, all of these LDUs 41 to 4n have basically the same configuration.

Further, in this embodiment, as the sensors 21 to 2n,
A so-called on-off sensor such as a limit switch, a proximity switch, a push button switch, a pressure switch, a bimetal switch, etc. that outputs a 1-bit signal as a logical value 111 I+ or "0" is assumed.

Now, as shown in FIG. 1, these IDUs 41 to 4n
are each an identification code (hereinafter referred to as an I
The condition is that there is a sensor output from the ID code generation circuit 401 (each LDU 41 to 4n differs only in the content of the 10 codes that will be generated from now on) and the corresponding sensor, that is, that the state has changed. A first gate buffer 402 opens to add this sensor output (a 1-bit signal of +12 "1" or 'O') to the generated ID code and outputs it in parallel.
, a FIFO buffer 1403 that temporarily stores the parallel signal of the sensor output and ID code that has been output, on a first-in, first-out basis;
/S (parallel/serial) conversion circuit 404, an OR circuit (OR gate) 405 that ORs the converted serial signal and a received demodulated serial signal (described later), and modulates the output serial signal as required. Transmission circuit 4 that sends this to the next stage LDU or CDLI 30
06, and a receiving circuit 4 that receives a signal when it is transmitted from the preceding DU and demodulates it into a required serial signal.
07, when this receiving circuit 407 receives a signal transmission from the previous LDU, if there is no signal stored in the FIFO buffer 403, the received demodulated serial signal is sent to the output path R1.
and if there is a signal stored in the FIFO buffer 403, the received demodulated serial signal is switched to the output path R2, and the output path R of this switching circuit 408 is connected.
2, and an S/P (serial/parallel) conversion circuit 409 that converts an H demodulated serial signal into a parallel signal, and a and a second gate buffer 410 that outputs the converted received demodulated parallel signal to the FIFO buffer 403 in parallel.

Here, in the case where signal transmission and reception between each LDLI is performed by optical communication via an optical fiber, the transmission circuit 406 includes a modulation circuit (Manchester modulation circuit or CMI modulation circuit, etc.), an electrical-to-optical converter, etc. If the same signal transmission and reception is performed by electrical communication via a metal cable, the configuration will include a modulation circuit, a driver circuit, etc.

On the other hand, the receiving circuit 407 also includes an optical-to-electrical converter and a demodulating circuit (Manchester demodulating circuit or CM
In the case of the above-mentioned telecommunications, the configuration includes an impedance matching circuit, a receiving amplifier, a demodulation circuit, etc.

In these LDtJ41-4n, for example,
Assuming that the sensor 22 changes state from off to on (or from on to off), the first gate buffer 402 of the LDU 40 is opened and the output of this sensor 22 is transferred to the LDU.
42 with the ID code attached to vj immediately.
The data is taken into the IFO buffer 1403.

The signal A (ID
The parallel signal of the code and the sensor output) is converted into a serial signal by the P/S conversion circuit 404 along with this output, and is input to the transmission circuit 406 via the OR circuit 405.

In the transmitting circuit 406, the input signal (serial signal of ID code and sensor output) is subjected to necessary 51 modulation, etc.
! LL! [! The processed data is transferred to the next stage LDU 43 via a communication medium (optical fiber cable or metal cable) 50.

When a signal is transmitted from LDU42 in this way, LDU4
3, the transmission signal is received by the receiving circuit 407 and subjected to necessary processing such as demodulation, and the received demodulated signal (a serial signal of the 10 codes of the LDU 42 and the output of the sensor 22) is transferred to the switching circuit 408. send to

In the switching circuit 40B (Ll)IJ43), the switching circuit 40B (Ll)IJ43)
If there is no signal stored in the FIFO buffer 1403 of 43, the received demodulated signal sent above is output to the output path R1. As a result, the received demodulated signal is directly sent to the OR circuit 405.
The signal is input to the transmitting circuit 406 via.

In the transmitting circuit 406, as described above, this input A is sent as the number (
After performing necessary processing such as modulation on the serial signal of the ID code of the LDU 42 and the output of the sensor 22, it is further transferred to the next stage LDU (LDU 44) via the communication medium 50.

Also, during the signal transfer from the LDU 42 to the LDU 43, the state of the sensor 23 changes and the sensor output is transferred to the FIF of the LDU 43 along with the ID code of the LDU 43.
When stored in the O buffer 403, the switching circuit 408 (LDU43) outputs the sent received demodulated signal (a serial signal of the 10 codes of the LDU 42 and the output of the sensor 22) to the output path R2. . In this case, the received demodulated signal is converted into a parallel signal through the S/P conversion circuit 409 and then taken into the i'FIFo buffer 403 (LDU 43) via the second gate buffer 410.

Therefore, in this case, the parallel signal of the ID code of the LDU 43 stored in the FIFO buffer 403 of the LDU 43 and the output of the sensor 23 is first
The OR circuit 40 converts the signal into a serial signal with the same content.
5 and the transmission circuit 406 to the next stage LDU (LD
Transferred to U44), and then continued to the same F I 'F
ID of LDU 42 stored next in O buffer 403
The parallel signal of the code and the output of the sensor 22 is similarly P/S converted and sent as a serial signal with the same content to the next stage LDU via the OR circuit 405 and the transmission circuit 406.
(LDU44).

The same process as described above is repeated in the LDUs after the LDU 44, and the signals (signal string) sequentially transferred in this way are finally taken into the CDU 3O.

The CDU3O decomposes each of these captured signals into 10 codes and a sensor output, converts the ID code into a contact address assigned in advance to the machine controller 10, and then converts this converted address and the sensor output. It is handed over to the machine controller 10.

Now, when considering the sensor output monitoring method and monitoring device according to these embodiments, as mentioned above, the sensors 21 to 2n targeted here are few.

o1jJ Even though the state changes of multiple sensors appear to be mechanically simultaneous, electrically there are variations in millisecond (ms) units.

O The same sensor rarely changes state repeatedly in milliseconds.

Due to the current situation, both LDUs
However, in reality, there are 2 in the FIFO buffer 403.
It is rare that more than two signals (parallel signals of ID code and sensor output) are stored temporarily. Therefore, by the time the output-transferred signal from a certain LDU reaches CDU3O, it has passed through the F of any L D or U on the way.
The probability that it will be temporarily stored in the IFO buffer 403 is extremely low, and even if it happens once, the time it takes for it to be taken into the CDLI 30 is tk≦τ×2tk (2) However,
tk: is the signal transmission time from the th LDU to the CDU 3O.

Incidentally, in the conventional sensor output monitoring method having the relationship expressed by equation (1) above, the above time τ varies from time tb to time (T+
However, in the monitoring method according to this embodiment, which has the relationship of equation (2), the same time τ is τ-1k...
(3) Or τ = α + tk × 2tk ... (4) However, α
: Either there will be a temporary storage delay in the FIFO buffer 403, and in reality, the above (3)
) is maintained in most cases.

In this way, according to this embodiment, the speed at which the sensor output is taken in to the CDU 30 (machine controller 10) is significantly improved. In addition, there is almost no variation in the speed of taking in the data, and a stable speed relationship is maintained in any case, and the concentrated taking of each sensor output to the CDU 3O is realized.

FIG. 2 shows a more specific configuration example of the LDU shown in FIG. 1 for reference.

In the configuration example shown in FIG. 2, the above-mentioned embodiment device uses an optical fiber cable as the communication medium 50 to transfer the above-mentioned signals (serial signals of ID code and sensor output) through optical communication. is assumed.

That is, as shown in FIG. 2, each of the LDUs 41 to 4n employs a transmitting circuit consisting of an optical transmitting circuit 406a and an electro-optical converter 406b as its transmitting circuit 406, and an optical transmitting circuit as its receiving circuit 407. - Electrical converter 40
A receiving circuit consisting of an optical receiving circuit 7a and an optical receiving circuit 407b is employed. The optical transmission circuit 406a receives the serial signal (
Normal NRZ: non return zero
The optical receiving circuit 407b is a circuit that performs Manchester modulation or CMI modulation (CMI encoding) of a bit string consisting of a code, and the optical receiving circuit 407b converts a serial signal (Manchester modulation or CMI encoding) into an electrical signal by an optical-electrical converter 407a. This is a circuit that demodulates a modulated bit string and returns it to a bit string consisting of an NRZ code. In particular, the optical receiving circuit 407b outputs a Din signal through its DiN terminal, which rises when the reception of the received signal starts and falls when the reception of the same signal ends.

In addition, in tLDU41 to 4n shown in FIG.
The code generation circuit 401 consists of a 7-bit DSW, that is, a dip switch (a jumper is also possible), and a maximum of 27=128 address spaces can be set according to the on-off combinations. ing. That is, in this example, it is possible to configure a sensor output monitoring device using a maximum of 128 LDUs from "0" to N27J.

Of course, the number of bits of such an ID code can be arbitrarily determined depending on the actual situation.

The FIFO buffer 1403 has a total of 8 bits, including the 10 codes made up of the above 7 bits and the sensor output made up of 1 bit (the output of the limit switch LS in case of rotation), depending on the time between the first gate buffer 402 or the second gate buffer 1410. A 1-byte buffer is used to temporarily store the parallel signals consisting of 1 byte on a first-in, first-out basis. The FIFO buffer 4o3 receives the 8-bit (1 byte) parallel signal according to the rise timing of the signal applied to the terminal WR (hereinafter referred to as WR signal), and receives the 8-bit (1 byte) parallel signal applied to the terminal RD (hereinafter referred to as RD signal).
It operates to discharge the received parallel signals in a first-in, first-out order at the rising edge of a signal (referred to as a signal). Also, this FIFO buffer 1403 is empty, that is, the buffer 4
When there is no signal being stored in the buffer 1403
However, the logic level of the EMP signal (signal ■) output through the terminal EMP becomes '1' (high level),
Conversely, when the buffer capacity of the buffer 14o3 is 1, when the reception signal is full up to (J-1>), the buffer 403 outputs FL through its terminal FLL.
The logic level of the L signal (signal ■) becomes 1''.Thus, the logic level of the signal ■ (FLL4\5) becomes 111 I+
In this case, the sensor output and the output from the first gate buffer F402 of the ID code at this point are temporarily held through AND circuits AD1 and AD2 until the logic level of the same signal becomes "'O" (low level). will be put on hold.

The relationship between the above-mentioned signals related to the operation of the FIFO buffer 1403 is shown in FIG. 3(a) as a timing chart.
- Shown in (d). In FIG. 3, the time α is the temporary storage delay in the FfFO buffer 403 in equation (4), that is, the time from when the input signal is input to the FIFO buffer 403 until it is shifted out to the output side. Show time. In addition, especially Fig. 3(a)
and 0.1, 2 as shown in (d). ...(J-2>, (
j! -1), 1st grade represents the number of signals stored in the FIFO buffer 403 at each time point. As described above, 1 indicates the buffer capacity of the buffer 1403.

In addition, the P/S conversion circuit 404 and the S/P shown in FIG.
The conversion circuit 409 starts each conversion operation at the rising timing of a signal applied to a terminal ST (hereinafter referred to as an ST signal). These conversions are performed on each terminal CLK
This is performed at the rate of the clock signal (which is oscillated and outputted from the oscillation circuit 411) applied to the clock signal. In addition, the BSY signal output from each terminal BSY (in the P/S conversion circuit 404, this becomes a signal ◎, and in the S/P conversion circuit 409, this becomes a signal ■) is synchronized with the start of each conversion operation. It rises (becomes logic level 1'') and falls (becomes logic level ``O'') in synchronization with the end of each conversion operation.

The operating mode of such a P/S conversion circuit 404 is shown in FIG.
) to (e), and the operation mode of the S/P conversion circuit 409 is shown in FIGS. 5(a) to (13), respectively. Note that the transmission and reception rate of each target signal by the optical transmitting circuit 406a and the optical receiving circuit 407b described above is also given by the clock signal (2).

In this example, the switching circuit 408 is constituted by a logic circuit as shown in FIG. That is, in the case of this example, as is clear from the figure, the above-mentioned switching control of the received demodulated signal to the output path R1 or R2 is performed according to the logic level of the signal @ generated through the OR circuit OR. If the logic level of this signal @ is 0'', the output path R1
is selected, and if the same logic level is #1 $1, the output path R2 will be selected. Incidentally, the reason why the logic level of this signal @ is 0'' is because o There is no signal being stored in the FIFO buffer 403 (signal ■ is logic 11011>).

o The P/S conversion circuit 404 is not performing a conversion operation (signal ◎ is logic ``0'').

o The S/P conversion circuit 409 is not performing a conversion operation (signals ■ and ■ are logic "'O").

is satisfied at least, and conversely, the logic level of the signal @ is "1" because there is a signal being stored in the o'FIFo buffer 403 (signal ■ is logic 11111).

o The P/S conversion circuit 404 is in conversion operation (
Signal ◎Logic゛1”).

0 When the first gate buffer 402 is closed and S/P
The conversion circuit 409 is in the middle of a conversion operation or has just finished a conversion operation (signals (2) and (2) are logic "'1").

is satisfied at least.

Regarding the relationship between these signals, please refer to the sensor output (signal ■
) and the DiN output from the optical receiving circuit 407b.
Assuming that the signals are generated in the manner shown in FIGS. 6A and 6B, they are collectively shown in FIGS. 6C to 6L. Control signal ■ (see Figure 6 (C)) and second gate buffer 4
The gate control signal 10 (see Fig. 6 (1)) is
The above FIF of the self-stage sensor output and the received demodulated signal, respectively.
Exclusive control for transfer to the O buffer 403 is performed.

As described above, the apparatus of the embodiment described above can be satisfactorily realized with the aspect shown in FIG.

In addition, in the embodiment device shown in FIG. 1, including the specific configuration example shown in FIG. Although the sensor output and the received demodulated signal (sensor output from the previous stage) are ranked, the point is that the configuration is sufficient as long as it can avoid collision of these two signals, and the configuration is limited to the configuration of this embodiment. It is not something that will be done. However, if the system is such that the relationship in equation (3) above is definitely satisfied, there is no need to take such consideration.

In addition, in the same embodiment device, the sensors 21 to 2n are assumed to be on-off sensors as described above, and a configuration is illustrated in which the sensor output consisting of 1 pin 1- is transferred, but sensor data consisting of multiple bits is The present invention can be similarly applied to other types of output sensors.

Furthermore, in the device of the same embodiment, signal processing within each LDU is performed using parallel signals; It is also possible to perform all of the above-mentioned signal processing using serial signals.

By the way, according to the configuration of the embodiment device, as shown in FIG.
Although they are connected in series in a ring, the connection between the CDU 3O and the LDU 41 is not required in principle for sensor output monitoring operation. However, in such systems, CDU3
The operation of each LDU 41 to 4n may be checked by issuing a test signal from O, and in this sense, the above-mentioned annular connection is useful.

〔Effect of the invention〕

As explained above, according to the present invention, (1) A rational and highly efficient sensor monitor is realized with a very simple signal line wiring structure.

■For this reason, even in machines with a large number of sensors, the space required for wiring can be reduced, and it is also possible to downsize the machine itself.

In addition to the inherent effects of the premised configuration, (1) The speed at which each sensor output is input to the controller is greatly improved.

■ Variations in the time from the generation of a certain sensor output until it is taken into the controller are also suppressed.

■ Since each LDIJ can be assigned an address (ID code) arbitrarily (there is no need to order the addresses according to their connection arrangement), the signal transmission system There is no need to take any consideration to this, and it becomes easy to modify the machine.

You can obtain many excellent effects such as.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of each LDU in an embodiment of the sensor output motor device according to the present invention, and FIG. 2 is a block diagram illustrating the configuration of the LDU shown in FIG. 1 in more detail. , FIGS. 3 to 6 are a timing chart showing an example of the operation of each part of the DU shown in FIG. 2, and FIG.
The figure is a block diagram showing an outline of the configuration of a sensor output monitoring device to which the present invention is applied. 10... Machine controller, 21-2n... Sensor, 3O-CDLI, 41-4n LDU, 50-...
Communication medium, 401... ID code generation circuit, 402° 410... Gate buffer, 403... FIFO buffer 1.404... P/S conversion circuit, 405... OR circuit, 406... Transmission circuit, 407...Reception circuit, 408...Switching circuit, 409...S/P conversion circuit. Figure 4

Claims (3)

[Claims] (1) When transferring the sensor outputs of multiple sensors to one central processing unit and centrally monitoring them, a peripheral processing unit that relays and processes each corresponding sensor output is provided for each of the multiple sensors. and connecting these peripheral processing devices in series in an annular manner via the central processing device,
In a sensor output monitoring method in which each sensor output is sequentially transferred to a central processing unit via peripheral processing units connected in series in a ring, an identification code is assigned to each of the peripheral processing units to identify each one; A sensor output monitoring method characterized in that only when a sensor output is generated from the sensor, the identification code of the corresponding peripheral processing device and the sensor output are asynchronously transferred to the central processing unit. (2) Regarding the sensor output generated during the transfer,
The sensor output monitoring method according to claim 1, wherein the sensor output is ranked in a predetermined order within the relevant peripheral processing device and transferred to the next stage. (3) When transmitting the sensor outputs of a plurality of sensors to one central processing unit and centrally monitoring the same, the plurality of peripheral processing units each have a signal transmitting means and a receiving means and relay processing of the sensor outputs. In the sensor output monitor device, which is provided corresponding to each of the sensors, and in which these peripheral processing devices are connected in series in a ring shape via the central processing device, each of the peripheral processing devices has its own peripheral processing device connected to the central processing device. an identification code generation means for generating an identification code assigned in advance to identify the sensor; a buffer means for temporarily storing the output sensor output and the identification code and outputting them to the transmitting means; and a signal transmission from the preceding peripheral processing device to the receiving means. switching means for outputting the transmission signal to the transmission means if there is no signal stored in the buffer means, and outputting the transmission signal to the buffer means if there is a signal stored in the buffer means; A sensor output monitoring device characterized by: