JPH01120663A - Microcomputer - Google Patents

Abstract

PURPOSE:To avoid useless power consumption at the part of a serial transfer circuit by detecting the start-stop bit of said transfer circuit and controlling the internal processing clock for transmission/reception of data. CONSTITUTION:A microcomputer 11 contains a CPU12 and a serial transfer circuit 13 set on the same substrate. A clock generator 14 supplies a clock signal to the CPU12 via a signal line S11 and also to a 2nd clock generator 15 for internal processing actions of the circuit 13. Then the clock signal is supplied to the circuit 13 via a signal line S14. The circuit 13 is connected to a clock generator 16 for transmission/reception. In such constitutions, the useless power consumption of the circuit 13 is avoided by stopping the working of the generator 15 as long as no start bit is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microcomputers. More specifically, the present invention particularly relates to a CPU on a complementary metal oxide semiconductor.
The present invention relates to a new configuration of a microcomputer that includes a clock generation source and a serial transfer circuit to execute the transfer process.

BACKGROUND OF THE INVENTION In recent years, as integrated circuit technology has progressed, CMO3 integrated circuit devices have become one of the technologies for realizing large-scale integrated circuits.

FIG. 3 is a block diagram schematically showing the configuration of a microcomputer equipped with a CPU, a serial data transfer circuit, a clock circuit prepared for transfer processing of the transfer circuit, internal processing, etc. on a CMO3 board. It is.

As shown in FIG. 3, this microcomputer 31 includes a CPU 32 and a serial transfer circuit section 33 on the same board.
It is equipped with Further, the clock generation source 34 that defines these operations is connected to the CPU 32 via the signal line S31.
In addition to supplying a clock signal to the serial transfer circuit unit 33, the second clock generation source 3
5, and this clock generation source 35 is supplied to the signal line S33.
A clock signal is supplied to the serial transfer circuit section 33 via the serial transfer circuit section 33. Furthermore, the serial transfer circuit section 33 includes a clock generation source 36 for transmitting and receiving, which defines the operation when this circuit exchanges data with the outside via the human power 133 and the output 033, and a clock generation source 36 for transmitting and receiving data via the signal lines 335 and 334. connected.

In a conventional microcomputer with such a configuration, when the serial transfer circuit section 33 is not in use, the internal processing for data transmission and reception of the serial transfer circuit section is controlled by the CPU 32 via the signal line S32. The operation of the clock generation source 35 is stopped, thereby reducing power consumption.

Furthermore, even if the serial transfer circuit 33 is in the transmission/reception enabled state, if the start bit is not detected, the second clock generation source 35 is in the operating state, and the serial data transmission/reception clock generation source 36 is activated via the signal line 335. The idea was to reduce power consumption by stopping the operation.

Problems to be Solved by the Invention However, in the conventional configuration as described above, if serial transmission/reception is enabled, the internal processing clock continues to be supplied from the signal line 333 regardless of whether or not a start bit is detected, which is still a waste. The disadvantage is that it consumes a lot of electricity.

That is, in a microcomputer that has a built-in serial transfer circuit on a CMO3 board that is equipped with a CPU, an internal processing clock, and a serial data transmission/reception clock, when the serial transfer circuit is ready for transmission and reception and is in a standby state, after the stop bit, It is not necessary to supply an internal processing clock for serial transmission and reception until the next start bit.

However, conventional microcomputers continue to supply internal processing clocks to serial transfer circuits even during standby periods when clocks are not needed, consuming wasted power.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a new microcomputer that further takes advantage of the low power consumption characteristic of CMO3.

Means for Solving the Problems According to the present invention, a first clock generation source for transmitting and receiving serial data and a first clock generation source for transmitting and receiving serial data are used for executing internal processing for transmitting and receiving serial data, together with a CPU, on a complementary metal oxide semiconductor substrate. In a microcomputer incorporating a serial transfer circuit equipped with a second clock generation source, means for detecting a start bit and a stop bit during serial transmission and reception of the serial transfer circuit, and a start bit detected by the output of the detection means. If the second
A microcomputer is provided, comprising: second clock generation source control means for starting the operation of the clock generation source and stopping the operation of the second clock generation source when a stop bit is detected.

Function: In contrast to the conventional microcomputer described above, the present invention has an original feature in that the supply of internal processing clocks for serial transmission and reception is stopped until a start bit is detected.

The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram schematically showing the configuration of a microcomputer constructed according to the present invention.

As shown in FIG. 1, this microcomputer 11 includes a CPU 12 and a serial transfer circuit section 13 on the same board.
It is equipped with In addition, a clock generation source 14 that regulates these operations supplies a clock signal to the CPU 12 via a signal line Sll, and also supplies a clock signal to the serial transfer circuit section 1.
A second clock source 15 for the internal processing operations of 3.
This clock generation source 15 supplies a clock signal to the serial transfer circuit unit 13 via a signal line 313. Furthermore, the serial transfer circuit unit 13 includes a clock generation source 16 for transmitting and receiving that defines the operation when this circuit exchanges data with the outside via the input 113 and the output 013, and a clock generation source 16 for transmitting and receiving data via the signal lines S15 and 314. connected. .

These structures are basically the same as those of the conventional microcomputer shown in FIG. 3, but the microcomputer of this embodiment further includes a serial transfer circuit section 1.
3. The clock generation source 15 is directly controlled by the CPU 12 via the signal lines 317 and S12, respectively. Also,
The clock generation sources 15 and 16 are controlled by the serial data transfer circuit unit 13 via signal lines S13 and 316, respectively.

In the microcomputer configured as described above, even if serial transmission/reception is enabled, if a start bit is not detected, the operation of the clock generation source 15 is stopped by the signal 313, and the clock signal is input to the serial transfer circuit section 13. By stopping the internal processing clock, it is possible to prevent wasted power consumed in this part.

FIG. 2 is a block diagram showing in detail the configuration of the serial transfer circuit section 13 in FIG. 1.

As shown in FIG. 2, this serial transfer circuit section 13 is
The input terminal Ill and the output terminal 011 are provided with a start bit detection section 21.23 and a stop bit detection section 22.24, respectively. The registers 25 and 26 respectively provided for the pair of detection sections of each terminal are configured to output LOW when a start bit is detected, and output HI when a stop bit is detected. Further, the logic gate 28 is configured to output Hi when the outputs of the registers 25 and 26 are both Hi ratio outputs.

Furthermore, the serial transfer circuit unit 13 includes a data processing unit 27 for serially transmitted and received data, and an internal processing unit 29 for data transmission and reception that generates a signal to the CPU after detecting a start bit.

FIG. 4 is a timing diagram illustrating the operation of the serial transfer circuit section 13 configured as described above and the microcomputer 11 including the same.

The reception operation will be explained. As shown in FIG. 4, between the input period 41 of the start bit and the manual input period 42 of the stop bit, the register 25 and the logic gate 28 become LOW outputs due to the detection of the start bit, and the output signal line of the logic gate 28 becomes LOW. 513 instructs the operation of the clock generation source 15.

Therefore, the clock generation source 15, as shown in FIG.
Supply of a clock signal is started via the signal line S14.

Next, in the stop bit detection period 42, when a stop bit is detected, the outputs of the register 25 and the logic gate 28 become Hi, instructing to stop the clock signal source 15 via the signal line S13.

Regarding transmission, the operation of the clock generation source 15 can be stopped and started in the same way. That is, since this microcomputer does not operate with the internal processing clock unless the start bit is detected, wasteful power consumption during standby can be prevented.

As described in detail, the present invention detects the start bit and stop bit of the serial transfer circuit and controls the internal processing clock for transmitting and receiving data supplied to the serial transfer circuit, thereby reducing wasted power. A microcomputer that can prevent the consumption of That is,
The microcomputer according to the present invention further improves the characteristics of a CMOS microcomputer, which requires even lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing a configuration example of a microcomputer constructed according to the present invention, and FIG. 2 shows a more detailed configuration of a serial transfer circuit section of the microcomputer shown in FIG. 3 is a block diagram schematically showing the configuration of a conventional microcomputer; FIG. 4 is a timing diagram illustrating the operation of the microcomputer shown in FIGS. 1 and 2; FIG. be. [Main reference numbers] Ill... Serial reception terminal, 011... Serial transmission terminal, IL 31... Microcomputer, 12.32.
...CPU1 13.33...Serial transfer circuit section, 14.34...
・Clock generation source 15.35...Clock generation source of serial transfer section, 2
1.23...Start bit detection means, 22.24.
... stop bit detection means, 25.26 ... flip-flop, 28 ... logic gate,

Claims (1)

[Scope of Claims] A first clock generation source for serial data transmission and reception and a second clock generation source used for executing internal processing for serial data transmission and reception are provided on a complementary metal oxide film semiconductor substrate together with a CPU. A microcomputer having a built-in serial transfer circuit includes means for detecting a start bit and a stop bit during serial transmission/reception of the serial transfer circuit, and when a start bit is detected by the output of the detection means, the second clock is generated. and said second clock generation source control means for starting the operation of said second clock generation source and stopping the operation of said second clock generation source when a stop bit is detected.