JPH01120392U - - Google Patents

Info

Publication number
JPH01120392U
JPH01120392U JP1988016490U JP1649088U JPH01120392U JP H01120392 U JPH01120392 U JP H01120392U JP 1988016490 U JP1988016490 U JP 1988016490U JP 1649088 U JP1649088 U JP 1649088U JP H01120392 U JPH01120392 U JP H01120392U
Authority
JP
Japan
Prior art keywords
protrusion
hole
electronic element
fixed
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988016490U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988016490U priority Critical patent/JPH01120392U/ja
Publication of JPH01120392U publication Critical patent/JPH01120392U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)
JP1988016490U 1988-02-10 1988-02-10 Pending JPH01120392U (US06252093-20010626-C00008.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988016490U JPH01120392U (US06252093-20010626-C00008.png) 1988-02-10 1988-02-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988016490U JPH01120392U (US06252093-20010626-C00008.png) 1988-02-10 1988-02-10

Publications (1)

Publication Number Publication Date
JPH01120392U true JPH01120392U (US06252093-20010626-C00008.png) 1989-08-15

Family

ID=31229472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988016490U Pending JPH01120392U (US06252093-20010626-C00008.png) 1988-02-10 1988-02-10

Country Status (1)

Country Link
JP (1) JPH01120392U (US06252093-20010626-C00008.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141279A (ja) * 2008-11-14 2010-06-24 Calsonic Kansei Corp 素子の放熱構造及び方法
JP2012227192A (ja) * 2011-04-15 2012-11-15 Astom Co Ltd 基板装置
JP2016004977A (ja) * 2014-06-19 2016-01-12 株式会社ジェイデバイス 半導体パッケージ及びその製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53126276A (en) * 1977-04-11 1978-11-04 Nippon Telegr & Teleph Corp <Ntt> Heat dissipation construction of multichip mounting substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53126276A (en) * 1977-04-11 1978-11-04 Nippon Telegr & Teleph Corp <Ntt> Heat dissipation construction of multichip mounting substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141279A (ja) * 2008-11-14 2010-06-24 Calsonic Kansei Corp 素子の放熱構造及び方法
JP2012227192A (ja) * 2011-04-15 2012-11-15 Astom Co Ltd 基板装置
JP2016004977A (ja) * 2014-06-19 2016-01-12 株式会社ジェイデバイス 半導体パッケージ及びその製造方法

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