JPH01120061A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a self-aligned transistor which can prevent an increase in an emitter contact resistance value due to an activation annealing operation, whose characteristic is good and whose manufacturing process is simple by a method wherein a high-concentration InGaAs emitter electrode is formed on a GaAs emitter layer of one conductivity type, ions of an impurity of an opposite conductivity type are implanted by making use of the electrode as a mask, and the like. CONSTITUTION:An InGaAs emitter electrode layer 11 whose concentration is higher than a GaAs emitter layer 6 of one conductivity type is formed on the layer 6 as an uppermost layer in a transistor layer structure having a GaAs/AlGaAs-based heterojunction; a mask pattern 12 is formed in an emitter electrode formation region on the emitter electrode layer 11; the InGaAs emitter electrode layer 11 is patterned by means of an etching operation by making use of the mask pattern 12 as a mask; an InGaAs emitter electrode 11A is formed. Then, while ions of an impurity of an opposite conductivity type are implanted by making use of the mask pattern 12 and the InGaAs emitter electrode 11A as masks, an activation annealing operation is executed; after that, the mask pattern 12 is removed. After that, e.g., a base electrode 9 and a collector electrode 10 are formed; as a result, an HBT is formed.

Description

[Detailed description of the invention] [Summary] II [l
T, (R) IIET.

Regarding the manufacturing method of RBT.

The purpose is to obtain a self-aligned transistor that can prevent an increase in emitter contact resistance due to activation annealing, has good characteristics, and has a simple process.

An InGaAs emifter electrode layer having a higher concentration than the core layer is formed on the uppermost one-conductivity type GaAs emifter layer of the layered structure of the transistor having a GaAs/AlGaAs heterojunction, and an emitter electrode formation region is formed on the emitter electrode layer. forming a mask pattern, and patterning the 1nGaAs emitter electrode layer by etching using the mask pattern as a mask to form an InGaAs emitter electrode, and etching impurities of opposite conductivity type using the mask pattern and the InGaAs emitter electrode as a mask A process of implanting ions and performing activation annealing.

and a step of removing the mask pattern.

[Industrial application field]

The present invention relates to semiconductor devices, particularly heterojunction bipolar transistors (I) using AlGaAs/GaAs heterojunctions.
The present invention relates to a method for manufacturing a resonant tunneling bibolar transistor (RBT), a (resonant tunneling) hot electron transistor ((R)HET), a resonant tunneling bibolar transistor (RBT), and the like.

HBT is expected to be a high-speed device with high current gain.
For example, the cutoff frequency is at most 28 GH for Si devices.
z, but 60 Gllz or more has been obtained in AlGaAs/Ga1s-based HET.

In HET, when electrons are injected from the emitter to the base,
It has the advantage of being able to run at high speed by converting high potential energy into kinetic energy. Its saturation speed is 10'cm/sec in a normal transistor.

In 11ET, it will be about 10 times that amount.

Among the +1ETs, RIIETs can control the movements of the high-energy Hontoelectrons by using the resonance tunneling effect, so they can have functions such as high-speed logic and memory. In addition, LSI with a small number of devices
It is attracting attention as a device with new functions in the future because it can realize the circuit functions that make up the circuit.

The RBT uses a resonant barrier instead of the heterojunction of the emitter of the IIBT to achieve a single functional element.

[Conventional technology]

As mentioned above, HBTs are attracting attention as high-speed devices, but they have problems such as slightly high base resistance, emitters and ivy, and large collector capacitance.
This was an important issue for improving the characteristics of T.

Therefore, a self-aligned structure of one emitter electrode was required. Now, the self-aligned structure will be explained using IIBT as an example.

FIG. 5 is a sectional view of a conventional self-aligned HBT.

The figure shows the basic layer configuration.

In the figure, on a semi-insulating (Sr)-GaAs substrate 1.

n”-GaAs collector contact layer 2. n-GaA
s collector layer 3. p''-GaAs base layer 4゜n-
8 IO, xGa6.7As layer 5. n-Ga
An As emitter contact layer 6 is sequentially grown.

The specifications of each of the above layers are as follows.

Drawing number Layer Concentration Thickness (.m-3)
(person) I 5l-GaAs M plate 2 n”-
GaAs 5EL8 30003n
-GaAs IE17 30004
p”-GaAs 5E18 10005
n-81GaAs 5E17
100 (16n-GaAs 2E1
8 3000 Next, a highly heat resistant WSi emitter vine electrode 8 was formed.

Using this as a mask, the n-GaAs emitter contact layer 6 is removed by etching to remove n-Al. , 3Ga, ),
7AS emitter vine layer 5 is exposed.

Next, using the WSi emitter electrode 8 as an implantation mask, Be
, by implanting p-type impurity ions such as Mg.

Activation annealing is performed at 900° C. for 5 seconds to form a p'-type electrode extraction region 7 that is self-aligned with the emitter electrode.

After this, the emitter layer 5,
p”-GaAs base 1ii 4 r n-Ga
The As collector layer 3 is removed by etching.

The n''-GaAs collector contact layer 2 in the collector electrode formation region is exposed.

Next, Au/Zn/Au is deposited on the p-type electrode extraction region 7.
An AuGe/^U collector electrode 10 is formed on the base tFi 9 + n''-GaAs collector contact layer 2 .

[Problem that the invention seeks to solve]

In the conventional self-aligned HBT described above, there are problems such as the contact at the interface between the WSi emitter electrode and the n''-GaAs emitter contact layer deteriorates due to activation annealing, increasing the contact resistance, and further deteriorating the hetero interface. was there.

Additionally, the process is complicated due to the formation of the WSi layer.

[Means for solving problems]

The solution to the above problem is to create an InGa layer with a higher concentration than the core layer on the uppermost single-conductivity type GaAs emitter layer of the layer structure of a transistor having a GaAs/AlGaAs heterojunction.
An As emitter electrode layer is formed, a mask pattern is formed in the emitter electrode formation region on the emitter electrode layer, and the 1nGa is etched using the mask pattern as a mask.
A step of forming an InGaAs emitter electrode by patterning the As emitter electrode layer, a step of implanting impurity ions of the opposite conductivity type using the mask pattern and the InGaAs emitter electrode as a mask, and performing activation annealing, and the mask pattern. A method for manufacturing a semiconductor device, the method comprising the step of removing.

Alternatively, an InGaAs emitter electrode layer having a concentration higher than that of the nucleus layer is formed on the uppermost one-conductivity type GaAs emitter layer of the layered structure of a transistor having a GaAs-based heterojunction, and an emitter electrode formation region is formed on the emitter electrode layer. manufacturing a semiconductor device, comprising: forming a mask pattern; patterning the 1nGaAs emitter electrode layer by etching using the mask pattern as a mask to form an InGaAs emitter electrode; and removing the mask pattern. This is accomplished by a method.

[Effect]

In the present invention, instead of the WSi emitter electrode for self-alignment, high concentration (about 5E19cn+-") n"-InGa
It has been experimentally confirmed that the As emitter electrode can be used as a notching mask for exposing the base electrode formation region and as an implantation mask for forming the p electrode extraction region, making it possible to form self-aligned HBTs, etc. The above n''-1n[;a with low resistance (10-'Ωcm) as
Since an As semiconductor is used, there is no effect of reaction at the emitter electrode interface and increase in interface resistance due to annealing, and an increase in emitter contact resistance is prevented.

〔Example〕

FIGS. 1(1) to 1(3) are cross-sectional views illustrating the steps of a self-aligned IBT according to an embodiment of the present invention.

In FIG. 1(1), on a 5l-GaAs substrate 1.

n”-GaAs collector contact layer 2. n-GaA
s collector layer 3, p''-GaAs base layer 4゜n
-Alo, :+Gao, Js emitter layer5. n-
GaAs emitter contact N 6 + n”-1n
o, , , Gao, 47 AS engineered mift electrode layer 11 is sequentially grown.

The specifications of each of the above layers are as follows, for example.

Drawing number Layer Concentration Thickness (cm-')
(person) I 5I-GaAs substrate 2 n”-GaAs 5E
18 30003 n-GaAs
IE17 30004 p”-GaAs
5E18 10005 n-AlG
aAs 5EI7 10006 n-
GaAs 2E18 100011
n″”-InGaAs 5E19 20
00 Next, a 12-layer SiO□ layer with a thickness of 3000 nm is formed as a mask pattern in the emitter electrode formation region on the grown substrate.

In FIG. 1(2), the 5in2 layer 12 is used as a mask.

Wet etching (etchant: H, O+H2
0 □ + 1 IF) and buttered with n”-1 nGa
An As emitter electrode 11A is formed.

In FIG. 1 (3), 5iOz layer 12 and n ” ”
- Using the TnGaAs emitter electrode 11A as an implantation mask, ions of p-type impurities such as Be'' and Mg'' are implanted, and activation annealing is performed at 900° C. for 5 seconds to form a p-type self-aligned to the emitter electrode. An electrode extraction region 7 is formed. Next, the SiO□ layer 12 of the mask is removed.

In the next step shown in FIG. 2, each layer other than the base electrode forming area is removed by etching to expose the n'-GaAs collector contact layer 2 in the collector electrode forming area.

Next, Au/Zn/Au is deposited on the p-type electrode extraction region 7.
An AuGe/Au collector electrode 10 is formed on the base TLfFi 9 and the n''-GaAs collector contact layer 2 .

As explained above, in the embodiment, the process can be simplified since it can be manufactured by only continuous growth of semiconductor.

FIG. 2 is a cross-sectional view of a self-aligned HBT formed according to an example.

The figure shows the basic layer configuration.

In the figure, 1 is a 5I-GaAs substrate.

2 is an n''-GaAs collector contact layer.

3 is an n-GaAs collector layer, and 4 is a p''-GaAs base layer.

5 is n-Alo, Ko Gao, 7AS engineering layer, 6
7 is an n-GaAs emitter contact layer, and 7 is a p° type electrode extraction region.

9 is the Au/Zn/8U base electrode, 10 is the AuGe/8U core electrode, and IIA is the n''-1n according to the present invention.
This is a GaAs emitter electrode.

Since the RIIET and RBT described below do not require activation annealing during the process, there is no need to worry about an increase in emitter contact. However, by adopting the present invention, a self-aligned element with a simple process can be obtained.

FIG. 3 illustrates another example of AlGaAs/GaAs
FIG. 2 is a cross-sectional view of R II ET using a heterojunction.

In the figure, 1, for example, M
By the BIE method, the n"-GaAs collector layers 32°, 8Io, zGao, and Js collector barrier layers 33.n
-GaAs base layer 34. Furthermore, Al6.3Gao
, Js barrier layer 35. GaAs well layer 36. Eight Io
, =Gao, ? A quantum well layer consisting of a ^S barrier layer 37 and an n''-GaAs emitter layer 38゜n''-1n
A GaAs mift electrode layer 39 is grown.

The specifications of each of the above layers are as follows.

Drawing number Layer Concentration Thickness (cm-3)
(person) 31 GaAs substrate 32 n”-GaAs 5E18 3
00033 AlGaAs
Undoped 200034 n-
GaAs InI3
100035 ^lGaAs
Undoped 4036 Ga
As undoped
4037 81GaAs
Undoped 4038 n-Ga
As InI3 50039 n”
-1nGaAs 5E19 4000 base layer 34. on the collector layer 32 with a thickness of 200/30 respectively.
00 AuGe/Au electrodes are installed.

Simply I (in the case of ET, instead of the barrier layer 35, which is a resonant quantum well layer.well layer 36.barrier layer 37).

As the emitter barrier layer, the thickness of 100-250 people
o, xGa6. Form a tAs layer.

FIG. 4 illustrates another embodiment of AlGaAs/GaA
FIG. 2 is a cross-sectional view of an RBT using an s-heterojunction.

In the figure, 1, for example, M
N''-GaAs collector contact layer 42゜rl-GaAs collector layer 43.p'-G is sequentially formed by BE method.
aAs base layer 44゜Al), 3Gao, 7
AS barrier layer 45+ GaAs well layer 46, AIo
, zGao, and Keiko Ido, which consists of S Barrier N47.

and n''-GaAs emitter layer 48゜n'''-
A 1nGaAs microelectrode layer 49 is grown.

The specifications of each of the above layers are as follows.

\、 \,.

＼ ＼ ＼ Drawing number Layer Concentration Thickness (cm-3)
(person) 41 5I-GaAs substrate 42 n”-GaAs 5E18 3
00043 n-GaAs IE17
300044 p”-GaAs 5E
18 100045 AlGaAs
Undope 4046
GaAs Anne F-
4047 AlGaAs
Undope 4048
n-GaAs IE18 500
49 n”4nGaAs 5E19 4
000 Next, Au is deposited on the N″-GaAs base layer 44.
/Zn/8U pace to extreme 9. AuGe/Au collector electrode 1 is formed on the n”-GaAs collector contact layer 42.
form 0.

In both of the embodiments shown in FIGS. 3 and 4, the emitter electrode is replaced with the conventional AuGe/Au metal electrode.
This is a self-aligned transistor that uses a -rnGaAs semiconductor and is etched using this as a mask.

C Effects of the Invention] As explained in detail above, according to the present invention, it is possible to prevent an increase in emitter contact resistance due to activation annealing,
A self-aligned transistor with good characteristics and a simple process can be obtained.

[Brief explanation of the drawing]

FIGS. 1 fl) to 1 (3) are cross-sectional views illustrating the steps of a self-aligned 11BT according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a self-aligned type 118T formed according to the embodiment. FIG. 3 explains another embodiment A] GaAs/GaAs
Cross-sectional view of R II ET using a heterojunction. FIG. 4 shows another example of AlGaAs and GaAs.
A cross-sectional view of an RBT using a heterojunction. FIG. 5 is a sectional view of a conventional self-aligned 11BT. , The figure is dangerous. 1 is a 5l-G'aAs substrate. 2 is an n"-GaAs collector contact layer. 3 is an n-GaAs collector layer. 4 is a p'-GaAs base layer. 5 is an n-8lo, 1Gao, Js emitter layer. 6 is an n-GaAs emitter contact layer. 7 9 is the p-type electrode extraction region. 9 is the Au/Zn/Au base N, pole. 10 is the uGe/he U collector electrode. 11A is the n'''-1nGaAs emitter electrode. 31 is a 5I-GaAs substrate. 32 is an n'-GaAs collector layer. 33 is 810. ,,Gao, 7 to S collector barrier layer. 34 is an n-GaAs base layer. 35 is an AlGaAs barrier layer. 36 is a GaAs well layer. 37 is ^16.3 Gao, q to s barrier layer. 38 is an n''-GaAs emitter layer. 39 is an n''-1nGaAs emitter electrode. 4I is S I-G a A s jJ board. 42 is an n''-GaAs collector contact layer. 43 is an n-GaAs collector layer 1. 44 is a p''-GaAs base layer. 45 is an 8Io, :1Gao, 7As barrier layer. 46 is a GaAs well layer. 47 is Alo, 3Gao, Js barrier layer. 48 is an n"-GaAs emitter electrode layer. 49 is an n to -1n GaAs emitter electrode layer.
TnL 纒 1 Senko Danki 1 Diagram recording threat +) (r) Self 7th H8T/: Curved surface diagram 2
figure

Claims (2)

[Claims] (1) An InGaAs emitter electrode layer with a higher concentration than that layer is formed on the top layer of one conductivity type GaAs emitter layer of the layer structure of a transistor having a GaAs/AlGaAs heterojunction, and an emitter electrode on the emitter electrode layer is formed. forming a mask pattern in a formation region and patterning the InGaAs emitter electrode layer by etching using the mask pattern as a mask to form an InGaAs emitter electrode; A method for manufacturing a semiconductor device, comprising the steps of implanting impurity ions and performing activation annealing, and removing the mask pattern. (2) An InGaAs emitter electrode layer with a higher concentration than that layer is formed on the uppermost one-conductivity type GaAs emitter layer of the layer structure of a transistor having a GaAs/AlGaAs heterojunction, and an emitter electrode is formed on the emitter electrode layer. forming a mask pattern in a formation region, patterning the InGaAs emitter electrode layer by etching using the mask pattern as a mask to form an InGaAs emitter electrode; and removing the mask pattern. A method for manufacturing a semiconductor device.