JPH01119902A - Sound recording and reproducing circuit - Google Patents

Sound recording and reproducing circuit

Info

Publication number
JPH01119902A
JPH01119902A JP27861487A JP27861487A JPH01119902A JP H01119902 A JPH01119902 A JP H01119902A JP 27861487 A JP27861487 A JP 27861487A JP 27861487 A JP27861487 A JP 27861487A JP H01119902 A JPH01119902 A JP H01119902A
Authority
JP
Japan
Prior art keywords
recording
transistor
signal
sound recording
playback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27861487A
Other languages
Japanese (ja)
Other versions
JP2583916B2 (en
Inventor
Tsuneo Okubo
大久保 常男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62278614A priority Critical patent/JP2583916B2/en
Publication of JPH01119902A publication Critical patent/JPH01119902A/en
Application granted granted Critical
Publication of JP2583916B2 publication Critical patent/JP2583916B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the distortion of a signal at the time of sound recording and to reduce the number of the change over switch circuits for sound recording and reproducing by providing a second transistor between the collector of a first transistor in a reproduction amplifier circuit and one of power sources. CONSTITUTION:One of heads 1 for sound recording and reproducing and a sound recording signal transmission system are connected to the base 22 of the first transistor 22 in a reproduction signal amplifier 2, and the second transistor 52 is provided between the collector of the first transistor 22 and one of the power sources. Consequently, the circuits of the transistors 22 and 52 become equal to diodes 61-64 at the time of sound recording, and the diode 64 becomes the bias of an opposite direction, whereby it is impervious to be conducted. Even if >=0.6V of the sound recording signal is added to negative, distortion does not occur and the number of the circuits of the changeover switches S3 for sound recording and reproducing can be reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテープレコーダなどの録音再生装置に用いる録
音再生回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a recording/reproducing circuit used in a recording/reproducing apparatus such as a tape recorder.

従来の技術 録音再生装置の録音再生回路は録音時と再生時に機械的
スイッチによって従来から切換えられていたが、最近で
は電子スイッチによって切換えられる方向になってきて
いる。
Conventional technology Recording and playback circuits of recording and playback devices have traditionally been switched between recording and playback using mechanical switches, but recently there has been a trend toward switching over using electronic switches.

以下図面を参照しながら上述した従来の録音再生回路の
一例について説明する。第10図は従来の録音再生回路
例を示すものである。第10図において、1は録音再生
用ヘッド、2は再生信号増幅回路、3は録音バイヤス信
号発生回路、8は低周波増幅回路、9はスピーカ、10
は録音信号増幅回路、Sly S2+ 83は切換スイ
ッチである。
An example of the conventional recording/reproducing circuit mentioned above will be described below with reference to the drawings. FIG. 10 shows an example of a conventional recording/reproducing circuit. In FIG. 10, 1 is a recording/playback head, 2 is a playback signal amplification circuit, 3 is a recording bias signal generation circuit, 8 is a low frequency amplification circuit, 9 is a speaker, 10
is a recording signal amplification circuit, and Sly S2+ 83 is a changeover switch.

この第10図の動作について説明すると、再生動作時に
はスイッチSIT S218sはA側に接続され、録音
再生用ヘッド1によって磁気テープから再生した信号は
スイッチSlを通して再生信号増幅回路2に加えられ、
トランジスタ22,23゜24.25,26.41を通
って増幅され、コンデンサ7を通って低周波回路8で増
幅し、スピーカ9で再生音が鳴る。
To explain the operation shown in FIG. 10, during the reproduction operation, the switch SIT S218s is connected to the A side, and the signal reproduced from the magnetic tape by the recording and reproduction head 1 is applied to the reproduction signal amplification circuit 2 through the switch Sl.
The signal is amplified through the transistors 22, 23, 24, 25, 26, 41, the capacitor 7, the low frequency circuit 8, and the speaker 9 produces a reproduced sound.

次に録音動作時にはスイッチSl+ S2e S3はB
側に接続されている。録音するための信号を端子11に
加え、録音信号増幅回路10で増幅した後、抵抗5.コ
ンデンサ6を介して、録音再生用ヘッド1に加えるとと
もに録音バイヤス信号発生回路3からバイヤス信号を録
音再生用ヘッド1に加えて磁気テープに録音する。
Next, during recording operation, switch SL+ S2e S3 is B
connected to the side. A signal for recording is applied to the terminal 11, amplified by the recording signal amplification circuit 10, and then connected to the resistor 5. A bias signal is applied to the recording and reproducing head 1 via the capacitor 6, and a bias signal is also applied from the recording bias signal generating circuit 3 to the recording and reproducing head 1 to be recorded on the magnetic tape.

発明が解決しようとする問題点 しかしながら、上記のような構成では録音動作時と再生
動作時とを機械的スイッチによって切換える切換回路が
多く必要であった。
Problems to be Solved by the Invention However, the above configuration requires a large number of switching circuits that use mechanical switches to switch between recording and reproducing operations.

本発明は上記問題点に鑑み、録音動作時と再生動作時と
の切換回路を少くするための録音再生回路を提供するも
のである。
In view of the above-mentioned problems, the present invention provides a recording and reproducing circuit that reduces the number of switching circuits between recording and reproducing operations.

問題点を解決するための手段 上記問題点を解決するために本発明の録音再生回路は再
生信号増幅回路内の第1のトランジスタのベースに録音
再生用ヘッドの一方と録音信号伝送系とを接続し、この
第1のトランジスタのコレクタと一方の電源との間に第
2のトランジスタを設け、この第1のトランジスタのベ
ースが少くとも再生動作時には電源の一方にバイヤスさ
れ、再生状態では再生信号増幅回路を動作させるととも
に、前記第2のトランジスタをオン状態にして再生信号
を増幅し、録音状態では再生信号増幅回路を不動作とす
るとともに、第2のトランジスタをオフ状態にする構成
を備えたものである。
Means for Solving the Problems In order to solve the above problems, the recording and reproducing circuit of the present invention connects one of the recording and reproducing heads and the recording signal transmission system to the base of the first transistor in the reproduced signal amplification circuit. However, a second transistor is provided between the collector of this first transistor and one power supply, and the base of this first transistor is biased to one of the power supplies at least during playback operation, and the playback signal is amplified in the playback state. The circuit is operated and the second transistor is turned on to amplify the playback signal, and in the recording state, the playback signal amplification circuit is made inactive and the second transistor is turned off. It is.

作用 本発明は上記した構成によって録音再生用ヘッドと再生
信号増幅回路内の第1のトランジスタのベースに録音信
号伝送系を接続したままでも第2のトランジスタを設け
ることによって録音動作時に信号が歪まなく、しかも切
換スイッチの回路数を少(することができる。
Effect of the present invention With the above-described configuration, even if the recording signal transmission system is connected to the recording/reproducing head and the base of the first transistor in the reproduced signal amplification circuit, the signal is not distorted during the recording operation by providing the second transistor. Moreover, the number of changeover switch circuits can be reduced.

実施例 以下本発明の一実施例の録音再生回路について、図面を
参照しながら説明する。第1図は本発明の第1の実施例
における録音再生回路の電気的結線図を示すものである
。第1図において、1は録音再生用ヘッド、2は再生信
号増幅回路、3は録音バイヤス信号発生回路、4,6.
7はコンデンサ、8は低周波増幅回路、9はスピーカ、
10は録音信号増幅器、S3は切換スイッチ、14゜2
2.23.24,25.26.27.30,35゜36
.40.41.52,56,57はトランジスタ、38
はダイオード、5.13.21・、28゜51.29.
31,33,34,37.39は抵抗である。
Embodiment Hereinafter, a recording and reproducing circuit according to an embodiment of the present invention will be explained with reference to the drawings. FIG. 1 shows an electrical connection diagram of a recording/reproducing circuit in a first embodiment of the present invention. In FIG. 1, 1 is a recording/playback head, 2 is a playback signal amplification circuit, 3 is a recording bias signal generation circuit, 4, 6 .
7 is a capacitor, 8 is a low frequency amplifier circuit, 9 is a speaker,
10 is a recording signal amplifier, S3 is a changeover switch, 14゜2
2.23.24, 25.26.27.30, 35°36
.. 40.41.52, 56, 57 are transistors, 38
is a diode, 5.13.21., 28°51.29.
31, 33, 34, 37.39 are resistances.

以上のように構成された録音再生回路について、以下第
1図から第9図までを用いてその動作を説明する。
The operation of the recording and reproducing circuit configured as described above will be explained below using FIGS. 1 to 9.

まず、第1図は本発明の一実施例を示すものであって、
再生動作時にはスイッチS3はA側に接続されている。
First, FIG. 1 shows an embodiment of the present invention,
During the reproducing operation, the switch S3 is connected to the A side.

磁気テープに記録された信号は録音再生用ヘッド1によ
って再生され、トランジスタ22のベースに加えられ、
トランジスタ23゜24.25,26.41によって増
幅され、コンデンサ7、低周波増幅回路8を通して、ス
ピーカ9で再生音が鳴る。次に、録音動作時には録音す
るための信号が端子11に加えられると、録音信号増幅
回路10.抵抗5とコンデンサ6を介して録音再生用ヘ
ッド1に加えられるとともに、録音バイヤス信号発生回
路3からバイヤス信号を録音再生用ヘッド1に加えて磁
気テープ上に録音する。
The signal recorded on the magnetic tape is reproduced by the recording/reproducing head 1 and applied to the base of the transistor 22.
The sound is amplified by the transistors 23, 24, 25, 26, 41, passed through the capacitor 7 and the low frequency amplification circuit 8, and then reproduced sound is produced by the speaker 9. Next, during a recording operation, when a signal for recording is applied to the terminal 11, the recording signal amplification circuit 10. A bias signal is applied to the recording/reproducing head 1 via a resistor 5 and a capacitor 6, and a bias signal is also applied to the recording/reproducing head 1 from a recording bias signal generating circuit 3 to record on the magnetic tape.

゛、この録音状態の時にトランジスタ52がない場合に
は、トランジスタ22のコレクタが、直接、アースされ
、再生信号増幅回路2にはスイッチS3がIllのため
に電圧が供給されていなく、トランジスタ22には電流
が流れていない。そのために、トランジスタ22の第5
図に示す部分は第6図のようにダイオード61.62を
接続したのとほぼ等価となる。そのため、抵抗5とコン
デンサ6からの信号がトランジスタ22のベースに加わ
った時において、信号の振幅が負側に振られるとマイマ
ス0.6v位でダイオード62が導通となり、信号がク
リップされ第7図のようになる。
If the transistor 52 is not present in this recording state, the collector of the transistor 22 is directly grounded, and the playback signal amplification circuit 2 is not supplied with voltage because the switch S3 is set to Ill. no current is flowing through it. For this purpose, the fifth
The part shown in the figure is almost equivalent to connecting diodes 61 and 62 as shown in FIG. Therefore, when the signal from the resistor 5 and capacitor 6 is applied to the base of the transistor 22, if the amplitude of the signal is swung to the negative side, the diode 62 becomes conductive at about 0.6 V, and the signal is clipped, as shown in FIG. become that way.

そのために、本発明の第1図の実施例ではトランジスタ
22を設け、第゛8図に示すトランジスタ22.52の
回路は録音時には第9図のグイオードロ1.62,63
.64と等価となり、ダイオード64が逆方向バイヤス
となり導通しなくなり、録音信号が負に約0.6V以上
加わっても歪まない。しかも録音再生の切換スイッチの
回路数を少くすることができる。
For this purpose, the embodiment of the present invention shown in FIG. 1 is provided with a transistor 22, and the circuit of the transistor 22, 52 shown in FIG.
.. 64, the diode 64 becomes reverse biased and no longer conducts, and even if the recording signal is applied negative by about 0.6 V or more, it will not be distorted. Moreover, the number of circuits for recording/playback changeover switches can be reduced.

次に、本発明の第2の実施例について図面を参照しなが
ら説明する。第2図は本発明の第2の実施例を示す録音
再生回路を示す電気的結線図である。第2図は第1図の
差動増幅器を構成するトランジスタ23.24の代りに
トランジスタ22と42とで差動増幅器を構成したもの
で、第1図と同じようにトランジスタ22のコレクタと
アースとの間にトランジスタ52をそのコレクタとエミ
ッタとで接続して挿入し、トランジスタ52は再生動作
時にはオン、録音動作時にはオフとなるように動作し、
第1図と同じ効果を有するものである。
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is an electrical wiring diagram showing a recording/reproducing circuit according to a second embodiment of the present invention. In Figure 2, a differential amplifier is constructed using transistors 22 and 42 instead of transistors 23 and 24 that constitute the differential amplifier in Figure 1, and as in Figure 1, the collector of transistor 22 and the ground are connected. In between, a transistor 52 is inserted with its collector and emitter connected, and the transistor 52 operates so as to be on during playback operation and off during recording operation,
This has the same effect as in FIG.

次に、第3図、第4図では、第1図、第2図の入力抵抗
21が録音動作時にインピーダンスを低くするのを防ぐ
ために、トランジスタ53を設けたもので、再生時には
トランジスタ53がオンし、録音時にはオフとなり、録
音時のインピーダンスを高くすることができるものであ
る。録音動作時にはトランジスタ14がオンしているた
め、トランジスタ22のベースは録音再生用ヘッド1と
トランジスタ14を介してアースされている。
Next, in FIGS. 3 and 4, a transistor 53 is provided to prevent the input resistor 21 in FIGS. 1 and 2 from lowering the impedance during recording operation, and the transistor 53 is turned on during playback. However, it is turned off during recording, making it possible to increase the impedance during recording. Since the transistor 14 is on during the recording operation, the base of the transistor 22 is grounded via the recording/reproducing head 1 and the transistor 14.

その他の動作及び効果は第1図;第2図と同じようであ
る。
Other operations and effects are the same as in FIGS. 1 and 2.

以上のように再生増幅回路の第1のトランジスタのコレ
クタと一方の電源との間に第2のトランジスタを設ける
ことによって録音時の信号の歪をな(し、しかも録音再
生の切換スイッチ回路を少くすることができる。
As described above, by providing the second transistor between the collector of the first transistor of the playback amplifier circuit and one of the power supplies, signal distortion during recording can be avoided (and the number of switch circuits for recording and playback can be reduced). can do.

発明の効果 以上のように、本発明は再生信号増幅器の第1のトラン
ジスタのベースに録音再生用ヘッドの一方と録音信号伝
送系とを接続し、この第1のトランジスタのコレクタと
一方の電源との間に第2のトランジスタを設け、この第
1のトランジスタのベースが少くとも再生動作時には電
源の一方にバイヤスされ、再生状態では再生信号増幅回
路を動作させるとともに、第2のトランジスタをオン状
態にして再生信号を増幅し、録音状態では再生信号増幅
回路を不動作とするとともに、第2のトランジスタをオ
フ状態にすることにより録音時の信号の歪をなくし、録
音再生の切換スイッチ回路を少くすることができる。
Effects of the Invention As described above, the present invention connects one side of the recording/playback head and the recording signal transmission system to the base of the first transistor of the reproduction signal amplifier, and connects the collector of the first transistor with one power source. A second transistor is provided in between, and the base of the first transistor is biased to one side of the power supply at least during the regeneration operation, and in the regeneration state, the reproduction signal amplification circuit is operated and the second transistor is turned on. to amplify the playback signal, disable the playback signal amplification circuit in the recording state, and turn off the second transistor to eliminate signal distortion during recording and reduce the number of recording/playback changeover switch circuits. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例における録音再生回路の
電気的結線図、第2図は本発明の第2の実施例における
録音再生回路の電気的結線図、第3図、第4図は本発明
における第3.第4の実施例における録音再生回路の電
気的結線図、第5図、第6図、第7図、第8図、第9図
は本発明の実施例における説明図、第10図は従来の録
音再生回路の電気的結線図である。 1・・・・・・録音再生用ヘッド、2・・・・・・再生
信号増幅回路、3・・・・・・録音バイヤス信号発生回
路、4゜β、7・・・・・・コンデンサ、8・・・・・
・低周波増幅回路、9・・・・・・スピーカ、10・・
・・・・録音信号増幅回路、S I 、S 2 + S
 3・・・・・・切換スイッチ、14,22,23゜2
4.25.26.27,30,35.36.40゜41
.52.50.57・・・・・・トランジスタ、38・
・・・・・ダイオード、5.13.21,28.51゜
29.31,33,34.37.39・・・・・・抵抗
。 、代理人の氏名 弁理士 中尾敏男 ほか1名第5図 
  第6図 第 7 図 第8あ  第9図
FIG. 1 is an electrical wiring diagram of the recording/playback circuit in the first embodiment of the present invention, FIG. 2 is an electrical wiring diagram of the recording/playback circuit in the second embodiment of the invention, and FIGS. The figure shows the third aspect of the present invention. 5, 6, 7, 8, and 9 are explanatory diagrams of the embodiment of the present invention, and FIG. 10 is an electrical wiring diagram of the recording/playback circuit in the fourth embodiment. FIG. 2 is an electrical wiring diagram of a recording/playback circuit. 1... Head for recording and playback, 2... Playback signal amplification circuit, 3... Recording bias signal generation circuit, 4°β, 7... Capacitor, 8...
・Low frequency amplifier circuit, 9...Speaker, 10...
... Recording signal amplification circuit, S I, S 2 + S
3...Choice switch, 14, 22, 23゜2
4.25.26.27,30,35.36.40゜41
.. 52.50.57...Transistor, 38.
...Diode, 5.13.21, 28.51°29.31, 33, 34.37.39...Resistance. , Name of agent Patent attorney Toshio Nakao and one other person Figure 5
Figure 6 Figure 7 Figure 8A Figure 9

Claims (1)

【特許請求の範囲】[Claims] 再生信号増幅回路の第1のトランジスタのベースに、録
音再生用ヘッドの一方と録音信号伝送系とを接続し、こ
の第1のトランジスタのコレクタと電源の一方との間に
第2のトランジスタを設け、この第1のトランジスタの
ベースが少くとも再生動作時には前記電源の一方にバイ
ヤスされ、再生状態では再生信号増幅回路を動作させる
とともに前記第2のトランジスタをオン状態にして再生
信号を増幅し、録音状態では再生信号増幅回路を不動作
とするとともに、前記第2のトランジスタをオフ状態に
することを特徴とする録音再生回路。
One of the recording and reproducing heads and the recording signal transmission system are connected to the base of the first transistor of the reproduction signal amplification circuit, and a second transistor is provided between the collector of the first transistor and one of the power supplies. , the base of this first transistor is biased to one of the power supplies at least during the playback operation, and in the playback state, the playback signal amplification circuit is operated and the second transistor is turned on to amplify the playback signal and perform recording. 1. A recording/reproducing circuit characterized in that in this state, a reproduction signal amplification circuit is rendered inoperative and the second transistor is turned off.
JP62278614A 1987-11-04 1987-11-04 Recording / playback circuit Expired - Lifetime JP2583916B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62278614A JP2583916B2 (en) 1987-11-04 1987-11-04 Recording / playback circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62278614A JP2583916B2 (en) 1987-11-04 1987-11-04 Recording / playback circuit

Publications (2)

Publication Number Publication Date
JPH01119902A true JPH01119902A (en) 1989-05-12
JP2583916B2 JP2583916B2 (en) 1997-02-19

Family

ID=17599733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62278614A Expired - Lifetime JP2583916B2 (en) 1987-11-04 1987-11-04 Recording / playback circuit

Country Status (1)

Country Link
JP (1) JP2583916B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5545530U (en) * 1978-09-18 1980-03-25
JPS5737708A (en) * 1980-08-20 1982-03-02 Toshiba Corp Electronic switching device
JPS58133606A (en) * 1982-01-30 1983-08-09 Hitachi Ltd Recording and reproducing circuit
JPS58205903A (en) * 1982-05-24 1983-12-01 Matsushita Electric Ind Co Ltd Magnetic recorder and reproducer
JPS5930212A (en) * 1982-08-11 1984-02-17 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5545530U (en) * 1978-09-18 1980-03-25
JPS5737708A (en) * 1980-08-20 1982-03-02 Toshiba Corp Electronic switching device
JPS58133606A (en) * 1982-01-30 1983-08-09 Hitachi Ltd Recording and reproducing circuit
JPS58205903A (en) * 1982-05-24 1983-12-01 Matsushita Electric Ind Co Ltd Magnetic recorder and reproducer
JPS5930212A (en) * 1982-08-11 1984-02-17 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing device

Also Published As

Publication number Publication date
JP2583916B2 (en) 1997-02-19

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