JPH01119112A - Voltage comparator - Google Patents
Voltage comparatorInfo
- Publication number
- JPH01119112A JPH01119112A JP27681587A JP27681587A JPH01119112A JP H01119112 A JPH01119112 A JP H01119112A JP 27681587 A JP27681587 A JP 27681587A JP 27681587 A JP27681587 A JP 27681587A JP H01119112 A JPH01119112 A JP H01119112A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- terminal
- switch
- control signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 230000010354 integration Effects 0.000 abstract description 2
- 230000006978 adaptation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000000284 extract Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電圧比較回路に関し、特にＭＯ５型集積回路に
適した電圧比較回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage comparison circuit, and particularly to a voltage comparison circuit suitable for an MO5 type integrated circuit.
Ｃ従来の技術〕
従来の電圧比較回路としては第３図に示すような回路が
ある。C. Prior Art] As a conventional voltage comparison circuit, there is a circuit as shown in FIG.
第３図の回路において、被測定電圧が入力端子１．２の
一方の端子１に接続され制御信号φにより非導通となる
スイッチ４と、基準電圧が他方の端子２に接続され、制
御信号φにより導通するスイッチ５が、カップリング容
量６の一方の端子に接続され、カップリング容量６の他
方の端子にインバータ７の入力端子が接続され、インバ
ータ７の出力端子にインバータ９の入力端子が接続され
、インバータ７の入力端子と出方端子との間に制御信号
φで導通するスイッチ８が接続された構成となっており
、インバータ９の出力端子を出カ端子３としている。In the circuit of FIG. 3, the voltage to be measured is connected to one terminal 1 of the input terminals 1.2, and the switch 4 is made non-conductive by the control signal φ, and the reference voltage is connected to the other terminal 2, and the switch 4 is turned off by the control signal φ. A switch 5 that conducts is connected to one terminal of a coupling capacitor 6, an input terminal of an inverter 7 is connected to the other terminal of the coupling capacitor 6, and an input terminal of an inverter 9 is connected to an output terminal of the inverter 7. A switch 8 is connected between the input terminal and the output terminal of the inverter 7 and is made conductive by a control signal φ, and the output terminal of the inverter 9 is the output terminal 3.
第３図の回路においてインバータ７とインバータ９とに
同一のインバータを用いた場合の動作波形を第４図に示
す。次に第４図を用いてその動作について説明する。FIG. 4 shows operating waveforms when the same inverter is used for inverter 7 and inverter 9 in the circuit of FIG. 3. Next, the operation will be explained using FIG. 4.
まず制御信号φによりスイッチ５，８が導通のとき、カ
ップリング容量６にはインバータ７のスレッショルド電
圧７丁１と基準電圧ＶＲＥＦとの差に比例した電荷ｑ□
が蓄えられる。ｑ工はカップリング容量６の容量値をＣ
工とすると、次式で表される。First, when the switches 5 and 8 are turned on by the control signal φ, the coupling capacitor 6 has a charge q□ proportional to the difference between the threshold voltage 7-1 of the inverter 7 and the reference voltage VREF
is stored. q is the capacitance value of coupling capacitor 6 as C
It is expressed by the following formula.
ｑ□＝Ｃ，（ＶＲＥＦ ＶＴｌ） （
１）またこのとき出力端子３には、インバータ９のスレ
ッショルド電圧ＶＴｚゲインをＧ２とすると、ＶＯＵＴ
＝’ Ｇ （ＶＴＩ ＶＴ２） ＋ＶＴ２
（２）となり、インバータ７とインバータ９とは同一イ
ンバータであるから
ＶＴ、＝Ｖ７２ ＝Ｖ７ テ（２）式はｖｏｕＴ＝ｖｒ
（３）となる。q□=C, (VREF VTl) (
1) At this time, if the threshold voltage VTz gain of the inverter 9 is G2, the output terminal 3 has VOUT.
=' G (VTI VT2) +VT2
(2), and since inverter 7 and inverter 9 are the same inverter, VT, = V72 = V7 The equation (2) is vouT = vr
(3) becomes.
次に制御信号φが「Ｌ」となりスイッチ４が導通となり
、スイッチ５，８が非導通となると、インバータ７の入
力端子に入力される電圧■１は、被比較電圧ＶｒＮとす
ると、電荷保存則により（１）式の電荷が保存され、
Ｃｘ （Ｖｍ ’Ａ） ＝Ｃｘ （ＶＲＥＦ ＶＴＩ）
Ｖｌ ＝’ｈＮ ＶＲＥＦ＋ＶＴｈ （４）と
なり
出力端子３に出力される電圧ｖｏＵＴはＶＯＵＴ”Ｇ２
（Ｇｌ （Ｖｘ−ＶＪ”ＶＴｔ−Ｖｒｚ）”Ｖｔｚ
（５）となる。インバータ７と９とは同一であるか
ら−Ｇ１＝−Ｇ２＝−〇□、ｖＴ、＝ｖＴ２＝ｖＴとす
ると、ＶＯＵＴ＝０２ （Ｖｒｓ ＶＲＥＦ） ＋ＶＴ
２ （６）となる。インバータのゲインＧが
十分大きいとすれば、
Ｖ ］：Ｎ ＞ Ｖ ＲＥＦ （７）場合 ■。０丁：
「Ｈ」となりＶ ＩＮ ＜ Ｖ ＲＰ：Ｆ （７）場合
Ｖｏｕｔ：ｒＬＪとなり第３図の回路は電圧比較回路
として動作する。Next, when the control signal φ becomes "L", the switch 4 becomes conductive, and the switches 5 and 8 become non-conductive, the voltage 1 inputted to the input terminal of the inverter 7 is set to the compared voltage VrN, according to the conservation of charge principle. The charge in equation (1) is conserved, and Cx (Vm 'A) = Cx (VREF VTI)
Vl ='hN VREF+VTh (4) The voltage voUT output to the output terminal 3 is VOUT''G2
(Gl (Vx-VJ”VTt-Vrz)”Vtz
(5) becomes. Since inverters 7 and 9 are the same, -G1=-G2=-〇□, vT, =vT2=vT, then VOUT=02 (Vrs VREF) +VT
2 (6). If the gain G of the inverter is sufficiently large, then V ]: N > VREF (7) Case ①. 0 pieces:
It becomes "H" and V IN < V RP:F (7) When Vout: rLJ, the circuit of FIG. 3 operates as a voltage comparison circuit.
ところで、上述した従来の電圧比較回路は、制御信号φ
によりスイッチ４が非導通でスイッチ５゜８が導通とな
るときに、インバータ７とインバータ９とが同一インバ
ータの場合には（３）式で示したように出力端子に中間
レベルｖ丁が出力される。またインバータ７とインバー
タ９とが異なる場合は、（２）式よりｖ、１＞ｖＴ２の
場合は出力端子はＨｉｇｈレベルとなり、Ｖ ＴＬ ＜
Ｖ Ｔ２の場合には出力端子はＬＯＷレベルとなり、
被比較電圧と何ら関係のない値となるため、電圧比較回
路の出力端子にフリップフロップやカウンタが接続され
るような場合には。By the way, the conventional voltage comparison circuit described above uses the control signal φ
When switch 4 is non-conductive and switch 5.8 is conductive, if inverter 7 and inverter 9 are the same inverter, an intermediate level v is output to the output terminal as shown in equation (3). Ru. Furthermore, if the inverter 7 and the inverter 9 are different, according to equation (2), if v, 1>vT2, the output terminal becomes High level, and V TL <
In the case of V T2, the output terminal becomes LOW level,
This value has no relation to the voltage to be compared, so when a flip-flop or counter is connected to the output terminal of the voltage comparison circuit.
本来所望している動作と異なる動作をする可能性があり
、これを防ぐためには、電圧比較回路の出力を更にラッ
チすることが必要である。このため。There is a possibility that the operation differs from the originally desired operation, and in order to prevent this, it is necessary to further latch the output of the voltage comparison circuit. For this reason.
チップ面積が増加し、消費電流も増加するという欠点が
ある。This has the drawbacks of increased chip area and increased current consumption.
本発明の目的は上記問題点を解消した電圧比較回路を提
供することにある。An object of the present invention is to provide a voltage comparison circuit that solves the above problems.
本発明は第１の端子に基準電圧が加えられ、第１の制御
信号により導通する第１のスイッチと、被比較電圧がそ
の第１の端子に加えられ、前記第１の制御信号と逆相の
第２の制御信号で導通する第２のスイッチと、その第１
の端子に前記第１及び第２のスイッチの第２の端子が接
続された第１の容量と、該第１の容量の第２の端子に入
力端子が接続された第１のインバータと、該第１のイン
バータの入力端子と出力端子の間に接続され、前記第１
の制御信号により導通する第３のスイッチと、その第１
の端子が前記第１のインバータの出力端子に接続され、
前記第２の制御信号により導通する第４のスイッチと、
該第４のスイッチの第２の端子と接地点との間に接続さ
れた第２の容量と、前記第４のスイッチと前記第２の容
量の共通端子に入力端子が接続された第２のインバータ
とを有し、該第２のインバータの出力端子から出力信号
を取り出すことを特徴とする電圧比較回路である。The present invention includes a first switch to which a reference voltage is applied to a first terminal and is made conductive by a first control signal; a second switch that conducts in response to a second control signal;
a first capacitor having terminals connected to second terminals of the first and second switches; a first inverter having an input terminal connected to a second terminal of the first capacitor; connected between the input terminal and the output terminal of the first inverter;
a third switch that is made conductive by a control signal;
a terminal is connected to the output terminal of the first inverter,
a fourth switch turned on by the second control signal;
a second capacitor connected between a second terminal of the fourth switch and a ground point; and a second capacitor whose input terminal is connected to a common terminal of the fourth switch and the second capacitor. This is a voltage comparison circuit characterized in that it has an inverter and extracts an output signal from an output terminal of the second inverter.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
図中、第３図と同一構成部分には同一番号が付しである
。図において、ＮチャネルＭＯＳトランジスタ１２とＰ
チャネルＭＯＳトランジスタ１３からなり、制御信号φ
で非導通となるスイッチ４，１０と、ＮチャネルＭＯＳ
トランジスタ１２とＰチャネルＭＯＳトランジスタ１３
からなり、制御信号φで導通となるスイッチ５，８と、
２つのインバータ７．９と２つの容量６と１１から構成
され、インバータ９の出力端子を出力端子３としている
。一方の入力端子１には被比較電圧ｖｘＮが印加され、
他方の入力端子２には比較基準電圧ＶＲＥＦが印加され
る。In the figure, the same components as in FIG. 3 are given the same numbers. In the figure, an N-channel MOS transistor 12 and a P
Consisting of a channel MOS transistor 13, the control signal φ
Switches 4 and 10 that become non-conductive and N-channel MOS
Transistor 12 and P channel MOS transistor 13
switches 5 and 8, which are made conductive by the control signal φ;
It is composed of two inverters 7 and 9 and two capacitors 6 and 11, and the output terminal of inverter 9 is used as output terminal 3. A compared voltage vxN is applied to one input terminal 1,
A comparison reference voltage VREF is applied to the other input terminal 2.
第２図は本発明の動作波形図である。まず制御信号φが
ＬＯＷの場合について説明する。制御信号がし０すの場
合、スイッチ５と１０が導通となり、従来例のインバー
タ７の出力端子と接地間に容量１１が接続された回路と
なる。このときの動作は従来例と同様で、インバータ７
とインバータ９を同一のインバータとすると出力端子３
に出力される電圧■。０τは（５）式と同じで
ＶＯＵＴ＝Ｇ” （ＶＤＪ ＶＲＥＦ） ＋Ｖｔ
（６）となり、Ｖ ｘＮ＞ Ｖ ＲＥＦ （７）
ときｖｏｕＴはｒＨｉｇｈＪとなり、ＶＩＮ＜ＶＲＥＦ
のときｖ０υＴはｒＬｏυ」となる。またこのとき容量
１１にはインバータ７の出力電圧に比例した電荷ｑ２が
蓄えられる。ここで容ｔｈ１１１の容量値を０２とする
と電荷ｑ２は
ｑｚ＝ｃ２（−Ｇ （ＶＩＩＮ ＶＲＥＦ） ＋ＶＴ）
（７）である。FIG. 2 is an operational waveform diagram of the present invention. First, the case where the control signal φ is LOW will be explained. When the control signal is 0, the switches 5 and 10 become conductive, resulting in a circuit in which the capacitor 11 is connected between the output terminal of the inverter 7 and the ground of the conventional example. The operation at this time is the same as the conventional example, and the inverter 7
and inverter 9 are the same inverter, output terminal 3
The voltage output to■. 0τ is the same as equation (5), VOUT=G” (VDJ VREF) +Vt
(6), and V xN> V REF (7)
When vouT becomes rHighJ, VIN<VREF
When , v0υT becomes rLoυ. At this time, a charge q2 proportional to the output voltage of the inverter 7 is stored in the capacitor 11. Here, if the capacitance value of capacitor th111 is 02, charge q2 is qz=c2(-G (VIIN VREF) +VT)
(7).
次に制御信号φがＨｉｇｈとなると、スイッチ４，１０
が非導通となり、スイッチ５，８が導通となり、容量６
の一方の端子には基準電圧が印加され、インバータ７は
短絡される。従って（３）式と同様に容量６にはｑｌ：
Ｃ２（ＶＲＥＦ−ＶＴＬ）（７）電荷が蓄えラレル。Next, when the control signal φ becomes High, the switches 4 and 10
becomes non-conductive, switches 5 and 8 become conductive, and the capacitance 6
A reference voltage is applied to one terminal of the inverter 7, and the inverter 7 is short-circuited. Therefore, as in equation (3), the capacity 6 is ql:
C2 (VREF-VTL) (7) Charge is stored in the parallel.
また、インバータ７とインバータ９とがスイッチｌＯに
より非導通となっており、容量１１には制御信号φがＨ
ｉｇｈとなる直前の（７）式で示した電荷が蓄えられて
いるので、出力端子３には制御信号がＨｉｇｈとなる直
前の値が保持されている。従って、従来回路のようにラ
ッチ回路を用いることなく、出力電圧を保持することが
できる。Further, the inverter 7 and the inverter 9 are made non-conductive by the switch IO, and the control signal φ is set to H to the capacitor 11.
Since the charge shown in equation (7) immediately before the control signal becomes high is stored, the value immediately before the control signal becomes high is held at the output terminal 3. Therefore, the output voltage can be held without using a latch circuit as in conventional circuits.
以上説明したように本発明は、従来の電圧比較器にスイ
ッチと容量とを加えることにより、ラッチ回路を用いな
くても出力電圧を保持できるため、消費電流が抑えられ
るとともに、占有面積の増加も抑えられ、集積化に適す
る効果がある。As explained above, the present invention can hold the output voltage without using a latch circuit by adding a switch and a capacitor to a conventional voltage comparator, thereby reducing current consumption and increasing the occupied area. It has an effect that is suppressed and suitable for integration.
第１図は本発明の一実施例を示す回路図、第２図は本発
明の動作を表す波形図、第３図は一従来例を示す回路図
、第４図は従来例の動作を表す波形図である。
１．２・・・入力端子 ３・・・出力端子４．
５，８，１０・・・ＭＯＳスイッチ ６，１１・・・容
量７．９・・・インバータFig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation of the present invention, Fig. 3 is a circuit diagram showing a conventional example, and Fig. 4 is a circuit diagram showing the operation of the conventional example. FIG. 1.2... Input terminal 3... Output terminal 4.
5, 8, 10...MOS switch 6,11...Capacity 7.9...Inverter
Claims (1)
号により導通する第１のスイッチと、被比較電圧がその
第１の端子に加えられ、前記第１の制御信号と逆相の第
２の制御信号で導通する第２のスイッチと、その第１の
端子に前記第１及び第２のスイッチの第２の端子が接続
された第１の容量と、該第１の容量の第２の端子に入力
端子が接続された第１のインバータと、該第１のインバ
ータの入力端子と出力端子の間に接続され、前記第１の
制御信号により導通する第３のスイッチと、その第１の
端子が前記第１のインバータの出力端子に接続され、前
記第２の制御信号により導通する第４のスイッチと、該
第４のスイッチの第２の端子と接地点との間に接続され
た第２の容量と、前記第４のスイッチと前記第２の容量
の共通端子に入力端子が接続された第２のインバータと
を有し、該第２のインバータの出力端子から出力信号を
取り出すことを特徴とする電圧比較回路。(1) A first switch to which a reference voltage is applied to a first terminal and is made conductive by a first control signal; a second switch that is turned on by a second control signal; a first capacitor whose first terminal is connected to the second terminals of the first and second switches; a first inverter having an input terminal connected to a second terminal; a third switch connected between the input terminal and the output terminal of the first inverter and made conductive by the first control signal; a fourth switch whose first terminal is connected to the output terminal of the first inverter and is rendered conductive by the second control signal; and a fourth switch connected between the second terminal of the fourth switch and a ground point. a second inverter having an input terminal connected to a common terminal of the fourth switch and the second capacitor, and receiving an output signal from the output terminal of the second inverter. A voltage comparison circuit characterized by taking out the voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27681587A JPH01119112A (en) | 1987-10-31 | 1987-10-31 | Voltage comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27681587A JPH01119112A (en) | 1987-10-31 | 1987-10-31 | Voltage comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01119112A true JPH01119112A (en) | 1989-05-11 |
Family
ID=17574776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27681587A Pending JPH01119112A (en) | 1987-10-31 | 1987-10-31 | Voltage comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01119112A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127467A (en) * | 1990-06-04 | 1992-04-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1987
- 1987-10-31 JP JP27681587A patent/JPH01119112A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127467A (en) * | 1990-06-04 | 1992-04-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
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