JPH01119106A - Digital voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To realize an equivalent function by a ROM small in capacity by constituting the title oscillator by an adder, a central frequency setter, a phase modulator, a sine wave generator, and an amplitude polarity converter. CONSTITUTION:The adder 31 which inputs a phase error signal quantized by a sampling cycle and adds a constant value from the central frequency setter and the phase error signal at every sampling period cumulatively is constituted of the adder A, the adder B, and a latch A. The sine wave generator 32 connected to the output of the phase modulator 33 is constituted of the ROM, and the phase modulator 33 connected to the output of the adder 31 is constituted of an exclusive OR circuit. Also, the amplitude polarity converter 34 which converts the amplitude polarity of the output signal of the sine wave generator 32 corresponding to a control signal from the phase modulator 33 is constituted of a latch B. In such a way, it is possible to realize the equivalent function by the ROM small in capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital voltage controlled oscillator (VCO) essential to a digital phase locked circuit, and particularly to a digital VCO with improved phase resolution and amplitude resolution.

(Prior Art) Fig. 4 shows the configuration of a conventional digital phase-locked loop. Here, 1 is a multiplier, 2 is a loop filter, and 3 is a center frequency setter 30, an adder 31, and a sine wave generator 32.
Digital ■ consisting of.

It is CO. Ideally, it is desirable for the sine wave generator 32 to maintain analog continuity in phase and amplitude characteristics as shown in FIG. The selection of the number of bits and the number of quantization bits is important for digitization.

Now, at -i, the sine wave generator 32 is a ROM (Rea).
d 0nly Memory).

In this case, the adder 31 is added every sampling period T! Time series C(jT) of phase error signal C quantized into bits
and are input to the constant value from the center frequency setter 30, and are cumulatively added to obtain the time series D(jT) of the ROM address designation signal d.
is created based on the formula below.

D(jT) = C(jT)+ +D ((j-1)T
) The amplitude values of the sine waves at each phase are stored in the ROM at addresses designated by the address designation signal d (which is actually the phase itself). Now, if the number of ROM address specification bits is m and the number of memory output bits is n, then the ROM output signal f is sin (360°/211xD (j
T)) is quantized by n bits.

Here, D(jT) is an integer value from 0 to 2'I-1,
Generally, it is often used at 12m.

- As an example, m=4 in FIG. 6 and Table 1. Taking the case of n=3 as an example, waveforms corresponding to the phase/amplitude characteristics of the continuous system in FIG. 5 are shown.

[Problems to be solved by the invention] In the conventional digital CO described above, as can be seen from FIG. 6 and Table 1, the larger the number of m and n, the higher the phase resolution and amplitude resolution. As mentioned above, increasing the number of bits increases the scale of the peripheral arithmetic circuits2.2 Processing time increases, resulting in a decrease in operating speed.At the same time, due to the memory capacity limit of the ROM itself, it is difficult to downsize and economically. A serious problem will arise.

The object of the present invention is to provide a digital C which is effective especially in cases where the memory capacity of ROM is an important selection point of the system.
It provides O.

(Means for Solving the Problems) The digital CO of the present invention inputs a phase error signal quantized at a sampling period, and uses a constant value from a center frequency setter and the phase error signal during the sampling period. an adder that performs cumulative addition at each time; a phase converter connected to the output of this adder; a sine wave generator connected to the output of this phase converter; and an amplitude polarity converter that converts the amplitude polarity of the output signal of the sine wave generator.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a vCO according to the present invention. In the figure, 30 is a center frequency setter, 31 is an adder, 32 is a sine wave generator, 33 is a phase converter, and 34 is an amplitude polarity converter. Here, as an example, m=2, n=
A configuration in which two ROMs are used as the sine wave generator 32 is shown in FIG.

In FIG. 2, adder 31 is composed of adder A, adder B, and latch A. The sine wave generator 32 is composed of a ROM, and the phase converter 33 is composed of an exclusive OR circuit. Further, the amplitude and polarity converter 34 is constituted by a latch B.

In this configuration, the quantization number of the phase error signal C is 4 bits, and the address designation signal d cumulatively added by the adder 31 is converted to the MSB (most significant bit) by the phase converter 33.
is outputted to the amplitude and polarity converter 34 as a polarity conversion signal. On the other hand, the second M5B signal is outputted to the sine wave generator 32 as a ROM address designation signal g by performing an exclusive OR operation on the remaining lower two bits. Here, sine wave generator 3
As shown in FIG. 3 and Table 2, the contents of the ROM constituting ROM 2 are characterized in that only absolute values of amplitudes in the 0°-90° range are written.

Furthermore, Table 3 shows the CO output amplitude in the O'-360' range. That is, the input signal d of the phase converter 33
By controlling the phase of the lower two bits every 906 in the second M5B of the ROM address O.

A necessary 2-bit sine wave absolute value amplitude signal i is read out over the entire range from -90° to 0° to 360° and output to the amplitude polarity converter 34. In this amplitude/polarity converter 34, the polarity conversion signal is assigned to the MSB, and the absolute value amplitude signal i is assigned to the lower two bits, thereby forming the CO output amplitude signal f.

From Table 3, this means m=4. This is consistent with Table 1 showing the operation of a conventional vCO using n=3 ROMs, and the present invention allows m=2. It can be seen that an equivalent function can be achieved with a small capacity ROM of n=2.

The above explanation shows that the vCO of the present invention can be configured with 1/8 of the ROM required for a conventional vCO, but conversely, when the same ROM is used,
Compared to conventional vCOs, the amplitude resolution can be doubled and the phase resolution can be quadrupled, making it possible to configure a vCO with less quantization noise and phase jitter.

Table 1 Table 2 Table 3 [Effects of the Invention] As explained above, the present invention is configured with an adder, a center frequency setter, a phase changer, a sine wave generator, and an amplitude polarity converter, thereby improving the efficiency of the conventional VCO. Small capacity R compared to
Equivalent functions can be realized with OM, and this has the effect of being extremely effective in reducing size and cost, especially when the memory capacity of ROM has a large effect on the system configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a VCO according to the present invention;
FIG. 2 is a circuit diagram of an embodiment of a VCO according to the present invention;
4 is a block diagram showing the configuration of a conventional vCO in a digital phase-locked loop. FIG. 5 is a diagram showing ideal phase amplitude characteristics. Figure 6 shows R in a conventional VCO.
It is a figure showing the phase amplitude characteristic of OM. DESCRIPTION OF SYMBOLS 1... Multiplier, 2... Loop filter, 3... Digital voltage controlled oscillator (VCO), 30... Center frequency setter, 31... Adder, 32... Sine wave generator , 33... Phase converter, 34... Amplitude polarity converter.

Claims (1)

[Claims] (1) An adder that inputs the phase error signal quantized at the sampling period and cumulatively adds the constant value from the center frequency setter and the phase error signal every sampling period, and the output of this adder. a sine wave generator connected to the output of the phase converter; and an amplitude converting the amplitude polarity of the output signal of the sine wave generator in accordance with a control signal from the phase converter. A digital voltage controlled oscillator characterized by comprising a polarity converter.