JPH01117521A - Speed conversion circuit - Google Patents

Abstract

PURPOSE:To attain speed conversion simply even at asynchronous state by supplying an analog signal decode output of a CODEC to an analog signal encode input and using a pulse with a bit rate different from that of the input side so as to convert the analog signal supplied to the encode input into a PCM signal. CONSTITUTION:An input side device 1 applies PCM coding to the voice signal and supplies the PCM signal to a terminal 2b of the CODEC 2 and gives a synchronizing signal to a terminal 2c and a clock signal to a terminal 2d. Since the terminals 2a, 2e are connected by a signal line, the PCM signal supplied from the input side device 1 is demodulated into an analog signal at the CODEC 2 and outputted from the terminal 2a. Then the signal is fed to the terminal 2e, subject to PCM coding synchronously with the new synchronizing signal and the clock signal supplied from the pulse generator 3 and the result is outputted from a terminal 2f. Thus, the bit rate of the outputted PCM signal is dominant by the bit rate of the pulse generator 3 and the bit rate is determined entirely independently of the bit of the input side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed conversion circuit that converts the speed of a PCM signal used for data transmission of a digital telephone.

[Conventional technology]

In general, digital telephones transmit signals using the I''CM method, and the bit rate when converting voice data to PCM is generally about 64 kilobits/second.This is time-division multiplexed. When sending data to a transmission line, mega-order bit rates are used to increase the multiplexing density.

[Problem that the invention seeks to solve]

However, conventional devices are not economical because it is difficult to change the bit rate in an asynchronous system.

[Means for solving problems]

In order to solve such problems, the present invention provides a receiving means for converting a PCM signal into an analog signal, a transmitting means for converting the analog signal into a PCM signal, and an analog signal input of the transmitting means to convert the analog signal output of the receiving means into an analog signal input of the transmitting means. A clock signal generator supplies a clock signal of a desired bit rate to the transmitting side.

[Effect]

The decoded signal is encoded again, and the encoding is performed at the new pit rate.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is the input 'Il[device], 2 is the codec,
3 is a pulse generator, and the input side device 1 converts the audio signal into I'CM at a bit rate of, for example, 64 kilobits/second, and supplies the PCM signal to the terminal 2b of the codec 2, as shown in FIG. 2(a). The synchronous signal No. 18 shown in FIG. 2 is supplied to the terminal 2c, and the clock signal shown in FIG. 2(b) is supplied to the terminal 2d. Pulse generator 3 is connected to terminal 2g of codec 2
The transmission synchronization signal shown in Fig. 2(e) is supplied to the terminal 2h.
A transmission clock signal shown in FIG. 2(a) having a different rate from the clock signal of the input device 1 is supplied to the input device 1.

Codec 2 uses a synchronization signal supplied to terminal 2c and terminal 2
Based on the clock signal supplied to terminal d, the PCM signal supplied to terminal 2b is taken in, the PCM (No. 8) is decoded, and the decoded analog signal is sent out from terminal 2a. Based on the synchronization pulse supplied to terminal 2g and the clock signal supplied to terminal 2h,
The analog signal supplied to the terminal 2e is converted into a PCM signal and outputted from the terminal 2f.

In the device configured in this way, the terminal 2a and the terminal 2
Since e is connected by a signal line, input side device 1
The PCM signal supplied from the terminal 2a is demodulated into an analog signal and output from the terminal 2a. The signal is then supplied to the terminal 2e, converted into PCM in synchronization with a new synchronization signal and clock signal supplied from the pulse generator 3, and is converted into PCM at the terminal 2f.
is output from. Therefore, the bit rate of the output PCM signal is controlled by the pulse generator 30 bit rate9, and the bit rate can be determined completely independently of the pits on the input side.

The codec 2 can be, for example, the MB6020 series manufactured by Fuji Tsushin Construction Co., Ltd., and speed conversion can be easily performed by only having one codec chip and a pulse generator.

〔Effect of the invention〕

As explained above, in this invention, the analog signal decode output of the codec is supplied to the analog signal encode input, and the analog signal supplied to the second code input is converted into a PCM signal by pulses having a bit rate different from that on the input side. This has the effect that speed conversion can be easily performed even asynchronously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part. 1... Input side device, 2... Codec, 3...
...Pulse generator.

Claims (1)

[Claims] Receiving means that captures PCM reception data based on a reception synchronization pulse and reception clock, converts the captured PCM reception data into analog data, and outputs it, and when analog data is input, transmits the data as a transmission synchronization pulse. It consists of a transmitter that outputs PCM transmit data based on a synchronized clock, and a connection line that connects analog data output from the receiver to an analog input terminal of the transmitter, and the bit rates of the receive clock and transmit clock are different. A speed conversion circuit characterized by being