JPH01116445U - - Google Patents
Info
- Publication number
- JPH01116445U JPH01116445U JP1172488U JP1172488U JPH01116445U JP H01116445 U JPH01116445 U JP H01116445U JP 1172488 U JP1172488 U JP 1172488U JP 1172488 U JP1172488 U JP 1172488U JP H01116445 U JPH01116445 U JP H01116445U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- area
- transistor circuit
- gate array
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012634 fragment Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は一実施例を示す平面図、第２図はゲー
トアレイの一チツプを示す平面図、第３図Ａは他
の実施例を示す平面図、同図ＢはそのＢ―Ｂ線位
置での断面図、第４図Ａはさらに他の実施例を示
す平面図、同図ＢはそのＣ―Ｃ線位置での断面図
、第５図Ａ，Ｂ，Ｃは実施例における配線領域の
配線断片形状を表わす平面図である。第６図Ａは
従来のゲートアレイにおける配線領域の配線例を
示す平面図、同図Ｂは本考案の実施例による配線
領域の配線例を示す平面図である。第７図Ａは従
来のゲートアレイを示す平面図、同図ＢはそのＡ
―Ａ線位置での断面図である。
１……トランジスタ回路領域、２，２ａ，２ｂ
，２ｃ，２ｄ……配線領域、１６，１７，１９，
２０……ゲート電極、１８，２１……拡散領域、
３１，３３，３４，３５，３６……配線断片。
FIG. 1 is a plan view showing one embodiment, FIG. 2 is a plan view showing one chip of the gate array, FIG. 3 A is a plan view showing another embodiment, and FIG. FIG. 4A is a plan view showing another embodiment, FIG. 4B is a sectional view taken along the line C--C, and FIGS. FIG. 3 is a plan view showing the shape of a wiring fragment. FIG. 6A is a plan view showing an example of wiring in a wiring area in a conventional gate array, and FIG. 6B is a plan view showing an example of wiring in a wiring area according to an embodiment of the present invention. FIG. 7A is a plan view showing a conventional gate array, and FIG. 7B is a plan view of the conventional gate array.
- It is a sectional view at the A line position. 1...Transistor circuit area, 2, 2a, 2b
, 2c, 2d... wiring area, 16, 17, 19,
20... Gate electrode, 18, 21... Diffusion region,
31, 33, 34, 35, 36... Wiring fragments.
Claims (1)
分離して配置されており、配線領域にもＭＯＳト
ランジスタが形成されているゲートアレイ。 (2) 配線領域とトランジスタ回路領域が互いに
分離して配置されており、配線領域にはトランジ
スタ回路領域につながつていない配線断片が形成
されているゲートアレイ。[Claims for Utility Model Registration] (1) A gate array in which a wiring area and a transistor circuit area are arranged separately from each other, and MOS transistors are also formed in the wiring area. (2) A gate array in which the wiring area and the transistor circuit area are arranged separately from each other, and the wiring area has wiring fragments that are not connected to the transistor circuit area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172488U JPH01116445U (en) | 1988-01-30 | 1988-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172488U JPH01116445U (en) | 1988-01-30 | 1988-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116445U true JPH01116445U (en) | 1989-08-07 |
Family
ID=31220529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1172488U Pending JPH01116445U (en) | 1988-01-30 | 1988-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116445U (en) |
-
1988
- 1988-01-30 JP JP1172488U patent/JPH01116445U/ja active Pending