JPH01115126A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01115126A JPH01115126A JP27426687A JP27426687A JPH01115126A JP H01115126 A JPH01115126 A JP H01115126A JP 27426687 A JP27426687 A JP 27426687A JP 27426687 A JP27426687 A JP 27426687A JP H01115126 A JPH01115126 A JP H01115126A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic package
- thermal expansion
- stage
- semiconductor device
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000919 ceramic Substances 0.000 claims abstract description 22
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 6
- 239000000956 alloy Substances 0.000 claims abstract description 6
- 239000010949 copper Substances 0.000 abstract description 8
- 229910001080 W alloy Inorganic materials 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 238000005336 cracking Methods 0.000 abstract 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 235000011089 carbon dioxide Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は半導体装置に係り、特にセラミックパッケージ
に密着させるステージの材質に関し、パッケージクラッ
クの発生を防止可能な半導体装置の提供を目的とし、
半導体チップを収容するセラミックパッケージからなる
半導体装置において、前記セラミックパッケージの熱膨
張率に近似する銅・タングステン（ＣｕＷ）合金を前記
半導体チップをｉ３ｃ置するステージに用いて構成する
。[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device, and in particular, an object of the present invention is to provide a semiconductor device that can prevent the occurrence of package cracks regarding the material of a stage that is brought into close contact with a ceramic package. In a semiconductor device comprising a ceramic package, a copper-tungsten (CuW) alloy having a coefficient of thermal expansion close to that of the ceramic package is used for a stage on which the semiconductor chip is placed.
本発明は、半導体装置に係り、特にセラミックパッケー
ジに密着させるステージの材質に関する。The present invention relates to a semiconductor device, and particularly to the material of a stage that is brought into close contact with a ceramic package.
第４図は従来のセラミック〉クツケージ型の半導体装置
例の断面図を示す。図において、■は半４体チップ、２
は半導体チップ１をダイス付けしたステージであって通
常その部材としてはモリブデンＭｏが用いられている。FIG. 4 shows a cross-sectional view of an example of a conventional ceramic shoe cage type semiconductor device. In the figure, ■ is a half-quad chip, 2
1 is a stage on which a semiconductor chip 1 is diced, and molybdenum Mo is normally used as the material thereof.
３はステージ２およびシールリング５をロウ付けしたセ
ラミックパッケージであってその材質はアルミナＡβ２
０．が用いられる。４はキャップ、シールリング５には
例えばコバール合金が用いられる。６はピン・グリッド
・アレイを示す。3 is a ceramic package in which the stage 2 and the seal ring 5 are brazed, and its material is alumina Aβ2.
0. is used. For example, a Kovar alloy is used for the cap 4 and the seal ring 5. 6 indicates a pin grid array.
従来構成のセラミックパッケージ型半導体装置は、セラ
ミックパッケージ３とステージ２とをロウ付けした部分
にクラックが発生し易い欠点がある。The ceramic package type semiconductor device having the conventional structure has a drawback that cracks are likely to occur at the part where the ceramic package 3 and the stage 2 are brazed.
この原因はセラミックパッケージ３を構成するアルミナ
ＡｌｚＣｈＯ熱膨張率６．７ Ｘｌ０−”／’Ｃに対し
てステージ２の部材モリブデンＭＯの熱膨張率が５．４
Ｘｌ０−ｂ／”Ｃと相違するためにストレスが集中的
にロウ付は部分に発生するためである。The reason for this is that the thermal expansion coefficient of the molybdenum MO of stage 2 is 5.4 compared to the thermal expansion coefficient of alumina AlzChO that constitutes the ceramic package 3, which is 6.7 Xl0-''/'C.
This is because stress is concentrated and brazing occurs in a portion due to the difference from Xl0-b/''C.
このパッケージクラックの発生を防止するためには、セ
ラミックパッケージ３の厚みを厚くしなければならない
欠点があった。In order to prevent the occurrence of package cracks, there is a drawback that the thickness of the ceramic package 3 must be increased.
本発明は上記従来の欠点に鑑みて創作されたもので、パ
フケージクランクの発生を防止可能な半導体装置の提供
を目的とする。The present invention was created in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a semiconductor device that can prevent the occurrence of puff cage crank.
ｃ問題点を解決するための手段〕 第１図は、本発明の半導体装置の断面図である。c.Means for solving problems] FIG. 1 is a sectional view of a semiconductor device of the present invention.
半導体チップ１を収容するセラミックパッケージ３から
なる半導体装置において、前記セラミックパッケージ３
の熱膨張率に近似する銅・タングステン（ＣｕＷ）合金
を前記半導体チップ１を載置するステージ７に用いて構
成する。In a semiconductor device including a ceramic package 3 that houses a semiconductor chip 1, the ceramic package 3
The stage 7 on which the semiconductor chip 1 is placed is made of a copper-tungsten (CuW) alloy having a coefficient of thermal expansion similar to that of the semiconductor chip 1.
銅タングステン合金の材質をＣｕ（１０χ）Ｗ（９０χ
）あるいはＣｕ （１５％） Ｗ （８５χ）とすれば
その熱膨張率はそれぞれ６．０（６，５） ｘ １０−
”／ ℃となって前記アルミナの熱膨張率６．７ ｘｌ
Ｑ−’／℃に近似する。これによりパッケージクラック
の発生を防止することができる。The material of the copper tungsten alloy is Cu(10χ)W(90χ
) or Cu (15%) W (85χ), the coefficient of thermal expansion is 6.0(6,5) x 10-
”/°C, and the thermal expansion coefficient of the alumina is 6.7 xl
Approximate to Q-'/°C. This can prevent package cracks from occurring.
以下本発明の実施例を図面によって詳述する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
なお、構成、動作の説明を理解し易くするために全図を
通じて同一部分には同一符号を付してその重複説明を省
略する。Note that, in order to make the explanation of the configuration and operation easier to understand, the same parts are given the same reference numerals throughout all the figures, and repeated explanation thereof will be omitted.
第１図は本発明の半導体装置の断面図を示す。FIG. 1 shows a sectional view of a semiconductor device of the present invention.
図において、７は銅・タングステン合金を用いたステー
ジであって、その片面に半導体チップ１をダイス付けし
、その裏面はセラミックパッケージ３にロウ付けされて
いる。In the figure, 7 is a stage using a copper-tungsten alloy, on one side of which a semiconductor chip 1 is diced, and on the back side thereof is soldered to a ceramic package 3.
第２図は銅ＣｕとタングステンＷの成分比と熱膨張率と
の関係を示した表であって、銅Ｃｕの成分が１５％近辺
でセラミックパッケージを構成するアルミナＡ ｌ ｇ
ｏｚの熱膨張率に近似するようになる。Figure 2 is a table showing the relationship between the component ratio of copper Cu and tungsten W and the coefficient of thermal expansion.
It comes to approximate the coefficient of thermal expansion of oz.
第３図はセラミックパッケージとして富士通型の半導体
装置ＲＩ Ｔ２５６−０３を試験対象とした耐熱衝撃試
験データを示す０図において、コンデイションＡとは０
℃の水と１００℃の湯の中に各５分間漬ける試験であっ
て、その繰り返し数をサイクル数で示している。コンデ
イションＢとは一５５℃のエタノール＋ドライアイスの
環境と＋１２５℃のフロリナートＦＣＪ３の環境に各５
分間漬ける試験である。Figure 3 shows thermal shock resistance test data for a Fujitsu type semiconductor device RI T256-03 as a ceramic package.
The test involves immersing the product in water at 100°C and hot water at 100°C for 5 minutes each, and the number of repetitions is shown in the number of cycles. Condition B is an environment of ethanol + dry ice at -55℃ and an environment of Florinat FCJ3 at +125℃.
This is a minute soak test.
ステージ部材としては銅・タングステン合金のＣｕ（１
０χ）Ｗ（９０χ）とモリブデンＭｏを用いて実施し、
データはクラック発生数／サンプル総数の形式で記入し
ている。試験結果から明らかなように熱膨張率を近位値
に合わせることによりクラック発生数は激減しているこ
とが分かる。The stage member is made of copper/tungsten alloy Cu(1
Conducted using 0χ)W(90χ) and molybdenum Mo,
Data is entered in the form of number of cracks/total number of samples. As is clear from the test results, the number of cracks is drastically reduced by adjusting the coefficient of thermal expansion to a proximate value.
以上の説明から明らかなように本発明によれば、セラミ
ックパッケージとステージ間のクランク発生数を減少さ
せることができ、セラミックパッケージを小型にできる
効果がある。As is clear from the above description, according to the present invention, the number of cranks occurring between the ceramic package and the stage can be reduced, and the ceramic package can be made smaller.
第１図は本発明の半導体装置の断面図、第２図は銅・タ
ングステン合金の成分比と熱膨張率の関係を示す表、
第３図は耐熱衝撃試験データ、
第４図は従来の半導体装置例の断面図を示す。
第１図において、１は半導体チップ、３はセラミックパ
ッケージ、７はステージ（ＣｕＷ）をそれ７ステーシ”
（Ｃｕｂ）
滞発呵＾弔導停父１シ斯向■
第１図
第２図
２ 又デージ゛’（Ｍｏ）
ｒε表。半導Ａ不舊３［仮ｊの崖印面の第４図Fig. 1 is a cross-sectional view of the semiconductor device of the present invention, Fig. 2 is a table showing the relationship between the component ratio of copper-tungsten alloy and the coefficient of thermal expansion, Fig. 3 is thermal shock resistance test data, and Fig. 4 is a conventional semiconductor device. Figure 3 shows a cross-sectional view of an example device. In Figure 1, 1 is a semiconductor chip, 3 is a ceramic package, and 7 is a stage (CuW).
(Cub) Delay 2 ＾ Condolence Stop Father 1 Situation ■ Fig. 1 Fig. 2 Fig. 2 Also Dage ゛' (Mo) rε table. Semiconductor A Fugen 3 [Figure 4 of the cliff face of Kari J
Claims (1)
（３）からなる半導体装置において、 前記セラミックパッケージ（３）の熱膨張率に近似する
銅・タングステン（ＣｕＷ）合金を前記半導体チップ（
１）を載置するステージ（７）としたことを特徴とする
半導体装置。[Claims] A semiconductor device comprising a ceramic package (3) that houses a semiconductor chip (1), wherein a copper-tungsten (CuW) alloy having a coefficient of thermal expansion close to that of the ceramic package (3) is used in the semiconductor chip (1).
1) A semiconductor device characterized in that it is a stage (7) on which the semiconductor device is placed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27426687A JPH01115126A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27426687A JPH01115126A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01115126A true JPH01115126A (en) | 1989-05-08 |
Family
ID=17539272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27426687A Pending JPH01115126A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078040A (en) * | 2011-08-22 | 2013-05-01 | Lg伊诺特有限公司 | Light emitting device package and light unit |
-
1987
- 1987-10-28 JP JP27426687A patent/JPH01115126A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078040A (en) * | 2011-08-22 | 2013-05-01 | Lg伊诺特有限公司 | Light emitting device package and light unit |
| US9634215B2 (en) | 2011-08-22 | 2017-04-25 | Lg Innotek Co., Ltd. | Light emitting device package and light unit |
| CN107425103A (en) * | 2011-08-22 | 2017-12-01 | Lg伊诺特有限公司 | Light emitting device packaging piece and electro-optical device |
| CN107425103B (en) * | 2011-08-22 | 2019-12-27 | Lg伊诺特有限公司 | Light emitting device package and light apparatus |
| USRE48858E1 (en) | 2011-08-22 | 2021-12-21 | Suzhou Lekin Semiconductor Co., Ltd. | Light emitting device package and light unit |
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