JPH01114216A - Digital/analog converter - Google Patents

Digital/analog converter

Info

Publication number
JPH01114216A
JPH01114216A JP27204587A JP27204587A JPH01114216A JP H01114216 A JPH01114216 A JP H01114216A JP 27204587 A JP27204587 A JP 27204587A JP 27204587 A JP27204587 A JP 27204587A JP H01114216 A JPH01114216 A JP H01114216A
Authority
JP
Japan
Prior art keywords
weighted
digital
resistor
output
load circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27204587A
Other languages
Japanese (ja)
Inventor
Motohiko Kishigami
岸上 元彦
Sadayoshi Hatsutori
服部 定善
Yasuaki Amamiya
保明 雨宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Keiki Inc
Original Assignee
Tokyo Keiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Keiki Co Ltd filed Critical Tokyo Keiki Co Ltd
Priority to JP27204587A priority Critical patent/JPH01114216A/en
Publication of JPH01114216A publication Critical patent/JPH01114216A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To always keep the inter-terminal resistance value of a load circuit constant, and to obtain a stable output by providing the individual resistor of a weighted resistor array with the respective contact points of a first contact point group and a second contact point group in parallel. CONSTITUTION:The title device is provided with a first weighted resistor array 5 provided with plural resistors weighted correspondingly to an input digital code in series, and a second weighted resistor array 6 cascade-connected to the above-mentioned first array, and the load circuit 4 provided with both the first contact point group which acts always to 'open' the individual resistor 5 of the first weighted resistor array, and the second contact point group 8 which acts always to 'close' the individual resistor of the second weighted resistor array 6 and is linked with the first contact point group respectively. Thus, analog quantity is obtained as the output of the load circuit according to an input digital signal, and the total sum of the resistance value of the resistor array of the load circuit comes constant always, and a stable voltage output is obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は例えば重みコードで表わされた入力のディジ
タル信号に対応する各ビットの重みに比例した電気量か
らアナログ量を出力するディジタル・アナログ変換器、
特に重みコードに比例した電気量への変換に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital/analog device that outputs an analog quantity from an electrical quantity proportional to the weight of each bit corresponding to an input digital signal represented by a weight code, for example. converter,
In particular, it concerns the conversion into an electrical quantity proportional to the weight code.

[従来の技術] 第5図は従来のディジタル・アナログ変換器のブロック
図を示し、1は所定ビットのディジタル信号を出力する
ディジタル信号発生器、4は各ビットの表わす重みに比
例した電気量を出力する荷重回路、11は定電圧を発生
するW準電源、16は電圧−電流変換器、17は加算増
幅器である。
[Prior Art] Fig. 5 shows a block diagram of a conventional digital-to-analog converter, in which 1 is a digital signal generator that outputs a digital signal of predetermined bits, and 4 is a digital signal generator that outputs an electric quantity proportional to the weight represented by each bit. 11 is a W quasi-power supply that generates a constant voltage; 16 is a voltage-current converter; and 17 is a summing amplifier.

従来のディジタル・アナログ変換器は上記のように構成
され、入力ディジタル信号は所定のビット数で構成され
た2進または1o進のディジタルワードであり、各ビッ
トはそれぞれ♀子化されており、これらに対応して各ビ
ットの重みに応じた電圧または電流の電気量【こ変換さ
れ、これを加締することによりアナログ信号が出力され
る。
A conventional digital-to-analog converter is configured as described above, and the input digital signal is a binary or decimal digital word consisting of a predetermined number of bits, and each bit is converted into a digital word. The electric quantity of voltage or current corresponding to the weight of each bit is converted, and by tightening this, an analog signal is output.

上記例は電流加算形のディジタル・アナログ変換器であ
る。
The above example is a current addition type digital-to-analog converter.

第6図は従来の他のディジタル・アナログ変換器の回路
図を示し、18は定電流源でありディジタル信号発生器
1からの2進信号によりスイッチ群を「開」、「閉」さ
せ、荷重回路4内の各ビットに対応した値の入力信号の
重みに比例した複数の定電流源18からの電流を加算増
幅器17にて加算することにより所定レベルのアナログ
信号が得られる。
FIG. 6 shows a circuit diagram of another conventional digital-to-analog converter, in which 18 is a constant current source that opens and closes a group of switches in response to a binary signal from the digital signal generator 1. An analog signal of a predetermined level is obtained by adding currents from a plurality of constant current sources 18, which are proportional to the weight of the input signal having a value corresponding to each bit in the circuit 4, in the summing amplifier 17.

第7図は従来の他のディジタル・アナログ変換器の回路
図を示し、はしご形抵抗回路を用いた例である。抵抗R
および2Rからなる回路の各ノードに定電流源18を接
続し、定電流源18を入力ディジタル信号で「開」、「
閉」すると入力ディジタル信号の重みに比例した電圧が
加算されて出力に得られる。
FIG. 7 shows a circuit diagram of another conventional digital-to-analog converter, and is an example using a ladder-shaped resistance circuit. Resistance R
A constant current source 18 is connected to each node of the circuit consisting of
When closed, a voltage proportional to the weight of the input digital signal is added to the output.

[発明が解決しようとする問題点] 上記のような従来のディジタル・アナログゆ換器では、
電流加算形においてはパノノ信号の重みに比例して各ビ
ットに対しIs/20、Ts/21 ・・・・Is/2
n−1のの複数の定電流源18を設(プる。
[Problems to be solved by the invention] In the conventional digital/analog exchanger as described above,
In the current addition type, Is/20, Ts/21...Is/2 for each bit in proportion to the weight of the panono signal
A plurality of n-1 constant current sources 18 are set.

n=10とするとその電流比は Is /2” −Is 1512   となり最も重み
の大きい電流と、最も重みの小さい電流比は1:512
となり所定の精度の定電流源18を実現することは難し
い。
If n=10, the current ratio is Is /2" - Is 1512, and the ratio of the current with the largest weight to the current with the smallest weight is 1:512
Therefore, it is difficult to realize the constant current source 18 with a predetermined accuracy.

またはしご形抵抗回路においては同一の定電流源18が
使用できるが、しかし各ピッ!〜毎に複数段(プなεプ
ればならない。
Alternatively, in a ladder resistor circuit the same constant current source 18 can be used, but each pip! For each ~, multiple stages (pu na ε must be pulled).

またディジタル・アナログ変換器の出力回路は一端が接
地され、その出力信号は各ピッ]〜毎の電流の加算され
た加算電流または加算電圧に限定されるという問題点が
あった。
Another problem is that one end of the output circuit of the digital-to-analog converter is grounded, and its output signal is limited to the summed current or summed voltage obtained by adding up the currents for each pin.

この発明はかかる問題点を解決するためになされたもの
で、荷重回路の端子間抵抗値は常に一定に保持でき単一
の電源より安定した給電が行え、出力回路には電圧以外
の抵抗信号が得られ且つ平衡出力が形式できるディジタ
ル・アナログ変換器を得ることを目的とする。
This invention was made in order to solve these problems.The resistance value between the terminals of the load circuit can always be kept constant, power can be supplied more stably than a single power supply, and the output circuit can receive resistance signals other than voltage. The object of the present invention is to obtain a digital-to-analog converter that can provide a balanced output.

[発明が解決するための手段] この発明に係るディジタル・アナログ変換器は、入力デ
ィジタル信号の重みに対応した所定ビットの複数の重み
付抵抗器が直列に設けられ且つ互いに縦続接続された2
組の重み付抵抗列と、第1重み付抵抗列のそれぞれの抵
抗器に個別に並列に設けられ常時「開Jをなし各ビット
に応じ個別に応動する接点よりなる第1接点群と、第2
重み付抵抗列のそれぞれの抵抗器に個別に並列に設けら
れ常時「閉」をなし第1接点群のビットと対応するビッ
ト毎に連動する接点を有する第2接点群よりなる荷重回
路を設けたものである。
[Means for Solving the Invention] A digital-to-analog converter according to the present invention includes two weighting resistors in which a plurality of weighting resistors of predetermined bits corresponding to the weighting of an input digital signal are provided in series and cascaded with each other.
a first contact group consisting of contacts that are individually connected in parallel to each resistor of the first weighted resistor string and are always open and respond individually according to each bit; 2
A load circuit consisting of a second contact group is provided, which is individually connected in parallel to each resistor of the weighted resistance series, and has a contact that is always "closed" and is interlocked for each bit corresponding to the bit of the first contact group. It is something.

[作用] この発明においては、入力ディジタルコードに対応して
重み付された複数の抵抗器が直列に設Cプられた第1重
み付抵抗列ならびにこれと縦続接続される第2重み付抵
抗列と、第1小み何抵抗列の個別の抵抗器に常時「開」
をなす第1接点群また第2重み付抵抗列の個別の抵抗器
に常時「閉」をなし第1接点群のピッ1〜に対応Jるビ
ット毎連動する接点よりなる第2接点肝をそれぞれ並設
する荷重回路を設(プたので、入力ディジタル信号に応
じ荷重回路出力にはアナ]」グ量が得られる。各ビット
毎に対応する第1接点群と第2接点群の所定の接点はそ
れぞれ「聞−1、「閉J動作が同時に行われるので荷重
回路の抵抗列の抵抗値の総和は常に一定となり、第2重
み付抵抗列の端子間には入力ディジタルコードに対応し
た抵抗値が得られる。定電流電源を抵抗値が常に一定な
抵抗列に付設することにより安定した電圧出力となる。
[Function] In the present invention, a first weighted resistance string in which a plurality of resistors weighted in accordance with an input digital code are connected in series, and a second weighted resistance string cascade-connected thereto. and the individual resistors in the first small resistor string are always "open".
The first contact group consisting of the individual resistors of the second weighted resistance series is always "closed" and the second contact point consisting of the contacts that are interlocked for each bit corresponding to the pins 1 to 1 of the first contact group is connected respectively. Since the load circuits are installed in parallel, an analog amount can be obtained for the output of the load circuits according to the input digital signal.Predetermined contact points of the first contact group and the second contact group corresponding to each bit are set. Since the ``-1'' and ``close J'' operations are performed at the same time, the sum of the resistance values of the resistance strings of the weighted circuit is always constant, and the resistance value corresponding to the input digital code is set between the terminals of the second weighted resistance string. A stable voltage output can be obtained by attaching a constant current power supply to a resistor string whose resistance value is always constant.

また荷重回路用ノJは中間端子を共通とした抵抗または
電圧の平衡出力とすることかできる。
In addition, the load circuit J can have a common intermediate terminal and have a balanced output of resistance or voltage.

[実施例] 本発明の一実施例を添付図面を参照して詳細に説明する
[Example] An example of the present invention will be described in detail with reference to the accompanying drawings.

第1図はこの発明の一実施例を示すブロック図であり、 図において、1.4.11は上記従来のディジタル・ア
ナログ変換器と同一であり、2は2進入力デイジタル信
号を所定のn進ディジタル出力に変換するデコーダ、3
は荷重回路4内に設けられた接点を作動させる選択回路
、5はn進ディジタルに対応した複数の重み付抵抗器が
直列に設けられた第1重み付抵抗列、6は第1重み付抵
抗列5と同一構成をなし且つ縦続接続される第2重み付
抵抗列、7は第1重み付抵抗列5を構成する個別の抵抗
器へそれぞれ並列に設けられ常時「開」をなし選択回路
3により個別に作動する接点よりなる第1接点群、8は
第2重み付抵抗器6を構成する個別の抵抗器へそれぞれ
並列に設けられ常時「閉」をなす第1接点7のビットと
対応するビット毎に連動する接点よりなる第2接続群、
9は端子、10は中間端子を示している。
FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1.4.11 is the same as the conventional digital-to-analog converter, and 2 converts a binary input digital signal into a predetermined a decoder for converting to a hexadecimal digital output, 3
5 is a selection circuit that operates a contact provided in the load circuit 4, 5 is a first weighted resistor string in which a plurality of weighted resistors corresponding to n-ary digital are provided in series, and 6 is a first weighted resistor. A second weighted resistor array 7 having the same configuration as the array 5 and connected in cascade is provided in parallel with each of the individual resistors constituting the first weighted resistor array 5 and is always kept open. A first contact group 8 is provided in parallel with each individual resistor constituting the second weighted resistor 6 and corresponds to the bit of the first contact 7 which is always "closed". a second connection group consisting of contacts interlocking for each bit;
9 indicates a terminal, and 10 indicates an intermediate terminal.

上記のように構成されたディジタル・アナログ変換器に
おいては、ディジタル信号発生器1からの2進または1
0進のディジタル信号はデコーダ2において所定のn進
ディジタルへ変換され、選択回路3内にデコーダ2の出
力に対応して設けられた例えばリレーを励磁する。
In the digital-to-analog converter configured as described above, the binary or binary signal from the digital signal generator 1 is
The 0-ary digital signal is converted into a predetermined n-ary digital signal by the decoder 2, and excites, for example, a relay provided in the selection circuit 3 corresponding to the output of the decoder 2.

荷重回路4は直列に接続された複数の重み付抵抗器より
構成される第1重み付抵抗列5ならびにこれに縦続接続
される第2重み付抵抗列6と、各抵抗器に個別に並設さ
れた第1接点群7と第2接点群8よりなり、選択回路3
内のリレーの励磁によりそれぞれ該当するビットが連動
して、第1接点群7の内の所定の接点は「開」から1閉
」へ、第2接点群8の内の同一ビットの接点は「閉」か
ら「開」へ同時に作動するので、各ビットについて縦続
接続された第1重み付抵抗列5と第2重み付抵抗列6は
常時何れか一方の接点が1開」となる補間的作用が行わ
れる。
The load circuit 4 includes a first weighted resistance string 5 composed of a plurality of weighted resistors connected in series, a second weighted resistance string 6 connected in series thereto, and a first weighted resistance string 6 that is individually connected to each resistor in parallel. The selection circuit 3 consists of a first contact group 7 and a second contact group 8
The corresponding bits are linked by the excitation of the relays in the first contact group 7, and the predetermined contacts in the first contact group 7 change from "open" to "1 closed", and the contacts of the same bit in the second contact group 8 change to "1 closed". Since the operation simultaneously changes from "closed" to "open," the first weighted resistor array 5 and the second weighted resistor array 6 connected in cascade for each bit have an interpolation effect such that one of the contacts is always open. will be held.

従って、荷重回路4の出力嫡子8間の抵抗列の総和は 2°R+2’ R+−−−+2nR となり常に一定である。Therefore, the sum of the resistance strings between the output heirs 8 of the load circuit 4 is 2°R+2' R+---+2nR and is always constant.

n−77ビツトとすると抵抗値の総和は255Ωとなる
If n-77 bits are used, the total resistance value will be 255Ω.

また中間端子9を共通端子としそれぞれの端子8を出力
とすると平衡出力が得られる。そのときの出力抵抗は全
抵抗値の1/2即ち127Ωならびに128Ωとなる。
Further, if the intermediate terminal 9 is used as a common terminal and each terminal 8 is used as an output, a balanced output can be obtained. The output resistance at that time is 1/2 of the total resistance value, that is, 127Ω and 128Ω.

第2図は荷重回路の一例を示す回路図で、2進化10進
デイジタル例を示し、入力ディジタル信号を2進としデ
ィジタル・アナログ変換器出力を10進アナログ量とす
る。このとき荷重回路4内の第1重み付抵抗列5と第2
重み付抵抗列6ならびにデコーダ8を変えるのみで上記
実施例と同様の動作が行える。
FIG. 2 is a circuit diagram showing an example of a load circuit, and shows an example of a binary coded decimal digital signal, in which the input digital signal is binary and the output of the digital-to-analog converter is a decimal analog quantity. At this time, the first weighted resistance array 5 and the second weighted resistance array in the load circuit 4
The same operation as in the above embodiment can be achieved by simply changing the weighted resistor array 6 and decoder 8.

第3゛図はデコーダの一例を示す回路図、入力ディジタ
ル10進から出力ディジタル2進への変換例である。
FIG. 3 is a circuit diagram showing an example of a decoder, and is an example of conversion from input digital decimal to output digital binary.

第4図はデコーダの他の一例を示す回路図、入力ディジ
タル2進から出力ディジタル10進への変換例である。
FIG. 4 is a circuit diagram showing another example of the decoder, and is an example of conversion from input digital binary to output digital decimal.

第1重み付抵抗列5と第2重み付抵抗列6の抵抗値を平
衡時における出力抵抗値が所定値になるよう選定するこ
とにより、ディジタル・アナログi換器は中間端子9を
共通としそれぞれの端子8から平衡出力が得られる。デ
ィジタル・アナログ変換器出力はアナログ電気量として
抵抗値のj也に端子8に定電流電源を付加して電圧出力
とすることができる。
By selecting the resistance values of the first weighted resistance series 5 and the second weighted resistance series 6 so that the output resistance value at equilibrium becomes a predetermined value, the digital/analog i converter shares the intermediate terminal 9 with each other. A balanced output is obtained from terminal 8 of. The output of the digital-to-analog converter can be made into a voltage output by adding a constant current power source to the terminal 8 to the resistance value as an analog electrical quantity.

計測信号や遠隔伝送された信号の2進ならびにn進ゲイ
ジしルのアナログ量への変換にも勿論利用できる。
Of course, it can also be used to convert measurement signals and remotely transmitted signals into binary and n-ary analog quantities.

本発明によるディジタル・アナログ変換器出力回路は一
端接地または平衡形式とすることができるので、広い分
野の計測や制御に利用できる。
Since the digital-to-analog converter output circuit according to the present invention can be of one-end grounded or balanced type, it can be used for measurement and control in a wide range of fields.

荷重回路4の端子8間の抵抗列の総和は常に一定値をな
して6)るので、定電流電源を付加するときその負荷が
一定にでき、ディジタル・アナログ変換器の電圧変換が
安定且つ精度良く行えるので高精度の計測や制御が行え
る。
Since the sum of the resistance strings between the terminals 8 of the load circuit 4 always forms a constant value 6), the load can be kept constant when a constant current power source is added, and the voltage conversion of the digital-to-analog converter is stable and accurate. This allows for highly accurate measurement and control.

[発明の効果] ′ この発明は以上説明したとc15つ、荷重回路には重み
付抵抗器が直列に設けられた第1ならびに第2抵抗列と
、各抵抗列の個別の抵抗器へ並列に第1接点群ならびに
第2接点群の各接点を設ける簡単な構造により、 入力の2進または10進デイジタルの各ビットに対応し
て作動する荷重回路の出力端子間抵抗列の総和は常に一
定値となり、測定信@ヤ遠隔伝送された信号としての2
進または10進デイジタルのアナログ量への変換につい
ては、デコーダならびに第1および第2重み付抵抗列の
抵抗値を所定値に修正するのみにて利用できる。
[Effects of the Invention] 'This invention has been explained above, and the load circuit has first and second resistance strings in which weighted resistors are provided in series, and a weighted resistor is connected in parallel to each individual resistor in each resistance string. Due to the simple structure in which each contact of the first contact group and the second contact group is provided, the sum of the resistance strings between the output terminals of the load circuit that operates in response to each bit of the input binary or decimal digital is always a constant value. Therefore, the measurement signal @2 as a remotely transmitted signal
Conversion of base or decimal digital into an analog quantity can be used simply by correcting the resistance values of the decoder and the first and second weighted resistor arrays to predetermined values.

荷重回路の端子間抵抗値が常に一定にできるので、定電
流電源を付加して電圧出力とするときその負荷抵抗は常
に一定になるので安定した出力が得られる。
Since the resistance value between the terminals of the load circuit can be kept constant at all times, when a constant current power source is added to output voltage, the load resistance is always constant and a stable output can be obtained.

またディジタル・アナログ変換器の出力回路は中間端子
を共通とした抵抗またf、tl電圧の平衡出力にできる
ので、平衡入力形式の制御回路への利用が容易に行える
という効果がある。
Further, since the output circuit of the digital-to-analog converter can be used as a balanced output of a resistor or f and tl voltages with a common intermediate terminal, there is an effect that it can be easily used in a control circuit of a balanced input type.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示すブロック図、第2図
は荷重回路の一例を示す回路図、第3図はデ′]−ダの
一例を示す回路図、第4図はデコーダの他の一例を示す
回路図、第5図(J、従来のディジタル・アナログ変換
器のブロック図、第6図は従来の他のディジタル・アナ
ログ変換器の回路図、第7図は従来の他のデ゛イジタル
・アナログ変換器の回路図である。 図において、1はディジタル信号発生器、2はデコーダ
、3は選択回路、4は荷重回路、5は第1重み付抵抗列
、6は第2重み付抵抗列、7は第1接点群、8は第2接
点群、9は端子、10は中間端子である。 なお、各図中同一符号は同一または相当部分を示す。 特許出願人  株式会社 東 京 計 器〜 12− 第1図 第2図
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a load circuit, Fig. 3 is a circuit diagram showing an example of a decoder, and Fig. 4 is a circuit diagram showing an example of a decoder. A circuit diagram showing another example, FIG. 5 (J), a block diagram of a conventional digital to analog converter, FIG. 6 is a circuit diagram of another conventional digital to analog converter, and FIG. 7 is a block diagram of another conventional digital to analog converter. 1 is a circuit diagram of a digital-to-analog converter. In the figure, 1 is a digital signal generator, 2 is a decoder, 3 is a selection circuit, 4 is a load circuit, 5 is a first weighted resistor string, and 6 is a second weighted resistor string. In the weighted resistor array, 7 is a first contact group, 8 is a second contact group, 9 is a terminal, and 10 is an intermediate terminal. Note that the same reference numerals in each figure indicate the same or equivalent parts. Patent applicant Co., Ltd. Tokyo Meter ~ 12- Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 重みコードを有する入力ディジタル信号により制御され
る荷重回路を設け、入力の各ビットの重みに比例したア
ナログ電気量を出力するディジタル・アナログ変換器に
おいて、 所定ビットの複数の重み付抵抗器が直列に設けられ且つ
互いに縦続接続される第1ならびに第2の2組の重み付
抵抗列と、該第1重み付抵抗列の抵抗器に個別に並設さ
れ常時「開」をなし各ビットに応じ個別に応動する接点
よりなる第1接点群と、該第2重み付抵抗列の抵抗器に
個別に並設され常時「閉」をなし該第1接点群のビット
と対応するビット毎に連動する接点を有する第2接点群
よりなる荷重回路を備えたことを特徴とするディジタル
・アナログ変換器。
[Claims] A digital-to-analog converter that includes a weight circuit controlled by an input digital signal having a weight code and outputs an analog electrical quantity proportional to the weight of each input bit, comprising: two sets of weighted resistors, first and second, in which resistors are provided in series and cascade-connected to each other; and resistors in the first weighted resistor series are individually arranged in parallel and are kept "open" at all times. None A first contact group consisting of contacts that respond individually according to each bit, and a resistor of the second weighted resistor string, which are individually arranged in parallel and are always "closed" and correspond to the bits of the first contact group. A digital-to-analog converter comprising a load circuit comprising a second contact group having contacts interlocking for each bit.
JP27204587A 1987-10-28 1987-10-28 Digital/analog converter Pending JPH01114216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27204587A JPH01114216A (en) 1987-10-28 1987-10-28 Digital/analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27204587A JPH01114216A (en) 1987-10-28 1987-10-28 Digital/analog converter

Publications (1)

Publication Number Publication Date
JPH01114216A true JPH01114216A (en) 1989-05-02

Family

ID=17508343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27204587A Pending JPH01114216A (en) 1987-10-28 1987-10-28 Digital/analog converter

Country Status (1)

Country Link
JP (1) JPH01114216A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831580B2 (en) 2001-12-18 2004-12-14 Hynix Semiconductor Inc. Digital-to-analog converter with linear amplification rate
DE102020133891A1 (en) 2020-12-17 2022-06-23 Maschinenfabrik Reinhausen Gmbh adapter device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104534A (en) * 1980-01-23 1981-08-20 Toshiba Corp Converter
JPS61287311A (en) * 1985-06-14 1986-12-17 Oki Electric Ind Co Ltd Variable resistor output circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104534A (en) * 1980-01-23 1981-08-20 Toshiba Corp Converter
JPS61287311A (en) * 1985-06-14 1986-12-17 Oki Electric Ind Co Ltd Variable resistor output circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831580B2 (en) 2001-12-18 2004-12-14 Hynix Semiconductor Inc. Digital-to-analog converter with linear amplification rate
KR100477158B1 (en) * 2001-12-18 2005-03-17 매그나칩 반도체 유한회사 Cmos image sensor with digital-analog converter
DE102020133891A1 (en) 2020-12-17 2022-06-23 Maschinenfabrik Reinhausen Gmbh adapter device

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