JPH01114118A - Inverter circuit - Google Patents

Abstract

PURPOSE:To reduce undershoot or ringing by inputting a signal to other N- channel MOSFET via an N-channel MOSFET whose gate receives a positive power voltage and which is normally turned on so as to limit the trailing time. CONSTITUTION:A positive power voltage VDD is given to a gate of an N-channel MOSFET 5, turned on normally and a signal outputted from a node N1 of a CMOS inverter 11 is given to the gate of an N-channel MOSFET 4 via the FET 5. When the potential at a node N3 changes from L to H level, the FET 5 acts on the slow leading of the potential of a node N4 given to the gate of the FET 4. Thus, the FET 4 is conductive slowly and the trailing waveform of an output signal VOUT is slower than a conventional circuit. As a result, undershoot or ringing at the trailing of the output waveform is eliminated or reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an inverter circuit applicable to an output buffer 7 circuit, and particularly relates to an inverter circuit constituted by metal oxide film semiconductor field effect transistors (hereinafter referred to as rMO8FETJ). It is.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional output buffer 7 circuit composed of two inverter circuits. In the figure, 1 is a P-type MO8FET, and 2 is an N-type MO3FET, and both MO8FETs 1°2 constitute a CMOS inverter 1. That is, P-type MO8FET
I and N-type MO8FET2 are connected in series to provide a positive power supply voltage V. 0 and the ground level GND, and the PI
An input signal ■1- is given to each gate of MMO8FET1 and N-type MO8FET2 from an internal circuit (not shown), and an output signal (hereinafter referred to as "signal ■") is taken out from the node N1 of each drain. It is configured. Also, 3 is a P-type MO8FET, and 4 is an N-type MO8FE.
T, and both MO8FETs 3 and 4 constitute a CMOS inverter 2. That is, P-type MO8F
ET3 and N-type MO8FET4 are connected in series and inserted between the positive power supply voltage vDD and the ground level GND,
The signal V from the CMOS inverter 1 is applied to the gates of each of the PIMO8FET3 and the N-type MO8FET4, and the output signal V is output from the node N between the respective drains.

It is configured so that the U-work can be taken out. The output signal (2) of the CMOS inverter circuit I2 is output to the outside of this circuit via a bonding pad (not shown), a wire (not shown), and a lead frame (not shown) connected to the node N2.

Next, the operation of the output buffer circuit configured as above will be explained based on FIG. 4. Figure 4 shows the input signal v
1N and output signal V. This is a timing chart with ol. First, at time t1, the input signal SV,N becomes “L II
When it changes from “H” to “H”, P type MO8FETI and N
"FI II" is applied to the gates of the MO8FET2, and the P-MO8FET1 becomes cut off, while the N-MO8FET2 becomes conductive.As a result, the signal at the node N1, which had been at H level until then, becomes begins to fall after the inherent delay time of CMOS inverter 1 has elapsed from time t1, and after a certain period of time, ゛L
” level.

When the signal V at node N1 reaches the LTT level, the P-type M
O3FET3 becomes conductive, while N-type MO8FE
T4 becomes cut off. As a result, until then “L II
The output signal VOtl of the node N2, which was at the level, changes to the CMOS
At time t2, when the inherent delay time of inverter I2 has passed, it starts to rise, and at time t3, II H
Becomes II level.

Next, at time t4, the input signal V T, S ” H”
When the signal changes from "LH" to "LH," the P-type MO8FET1 becomes conductive, while the N-type MO8FET2 becomes cutoff.As a result, the "L II level signal (■) at the node N1 changes from time t4 to the CMOS Inverter 11
After the specific delay time has elapsed, it starts to rise and reaches the 11H" level after a certain period of time.

When the signal V of the node N1 is at °゛H''H'' level, the P-type MO
8FET3 is in the cut-off state, while N-type MO3FET
4 becomes conductive. As a result, the “H” level output signal @vOUT of the node N2 is different from the “H” level output signal @vOUT of the node N1.
At time t5, after the delay time specific to the CMOS inverter 2 has elapsed, the signal begins to fall, and at time t6, it reaches the "low" level.

[Problem that the invention seeks to solve]

In this output balance circuit, as is clear from FIG. 4, the output signal V. At the falling edge of Ul (time t5 in Figure 4)
Undershoot and ringing occur in the output waveform only at ~t6), and the output signal ■. No undershoot or ringing is observed when U□ rises (times t2 to t3 in FIG. 4). The reason is,
When the output signal ■ falls (time t5 to t in Figure 4)
6) In case of 0/1, the time (1-15) for the output waveform to go from "H" to "L" is short and the waveform is steep and flat, whereas the output signal V. When the UT rises (time 1 - 13 in Figure 4), the output waveform changes from "low" to "H".
This is because the time required for the output waveform to rise and fall (t3 t2) is long and the waveform is gentle. The charging/discharging time is determined by the charging/discharging time of the external circuit (formed by the input capacitance, etc. of the next stage external circuit (not shown) to which the UT is applied).In addition, this charging/discharging time is determined by the value of the output capacitance and the P type or N type MO8
It is proportional to the product of the on-resistance value of FET3.4.

Therefore, if the output capacitance is constant, P-type MO8
Depending on the on-resistance value of FET3 or N type MO8
-t2) and fall time (t6-t5) are to be determined. Here, P type MO8FET3 and N
Comparing the on-resistance values with the type MO8FET4, if the transistor sizes are the same, the on-resistance value of the P-type MO8FET3 is larger than the on-resistance value of the N-type MO8FET4. The reason is that the mobility of P-type MO8FET3 is lower than the mobility of N-type MO8FET4.

As mentioned above, since the on-resistance value of P-type MO8FET3 is larger than the on-resistance value of N-type MO8FET4,
O8FET3 becomes conductive (at this time, N-type MO8
FE 3 is in a cut-off state) output signal V. Ul is from “shi”
Charging time when rising to H'' (time 1 -1 in Figure 4)
3) is the output signal V when the N-type MO8FET 4 is in a conductive state (at this time, the P-type MO8FET 3 is in a cut-off state). ol
is longer than the discharge time when falling from 11 H'' to L'' (times t5 to 16 in Fig. 4).In other words, the rise time is longer than the fall time, and the rise is gradual; , the fall is steep.

As mentioned above, in addition to the reason that the output waveform at the time of falling is steep, in addition to the output capacitance, the inductance of the package and external wiring is added to the output side of this circuit. Coupled with the fact that the impedance and the impedance outside this circuit (not shown) are not matched, the output signal V. When ol falls (
At times t5 to t6 in FIG. 4, undershoot and ringing occur in the output waveform, causing a problem of causing external equipment to malfunction.

In particular, as semiconductor devices become more highly integrated due to recent advances in microfabrication technology and the operating speed of gates inside integrated circuits improves, the output waveform in the output buffer 7 circuit also becomes steeper, resulting in a higher degree of undershoot and ringing. has become even bigger, and the above-mentioned problems are getting more and more attention.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide an inverter circuit that can reduce undershoot and ringing by controlling the falling operation time.

(Means for Solving Problem rI4) The inverter circuit according to the present invention has a first N-type transistor whose source is grounded and whose output signal is taken out from the drain side, so that the inverter circuit is always on. The input signal is applied to the gate of the first N-type transistor via a second N-type transistor whose gate is provided with a positive power supply potential.

[Effect]

According to the inverter circuit of the present invention, when the input signal changes from "1" to "1", the change is gently adjusted by the second N-type transistor, and the first N-type transistor Since the output signal falls slowly, undershoot and ringing are prevented or reduced.

〔Example〕

FIG. 1 shows an output balance circuit having an inverter circuit, which is an embodiment of the present invention. The difference between this figure and the conventional example shown in FIG. 3 is that the gate has a positive power supply potential (■).

0 is given to the N-type MO8FE which is always on.
is newly installed, and CMO is connected via this N type MO8FE 5.
The signal (2) output from the node N1 of the S inverter (2) is applied to the gate of the N-type M08FET4. Note that N3 is connected to node N1 and P-type MO8FE.
N4 is a node that connects the gate of T3 and one electrode of N-type MO3FET5, and N4 is a node between the gate of T3 and one electrode of N-type MO3FET5.
This is a node that is a connection between the gate of the N-type MO8FET 5 and the other electrode of the N-type MO8FET 5.

Next, the operation of the output buffer 7 circuit configured as above will be explained based on FIG. 2. Figure 2 shows the input signal ■
and 1N of nodes N and N, respectively.
3 4 potential v, ■ and output signal ■. It is a timing chart showing the relationship with Uo. First, at time t1,
When the input signal V1 changes from “L” to H”, the P-type MO
"HTe" is applied to the gates of 8FET1 and N-type MO8FET2, respectively, and PJ2MO8FET1 becomes cut off, while N-type MO8FET2 becomes conductive.As a result, as in the conventional case, from time t1, the characteristic of CMOS inverter l At time t2, when the delay time has elapsed, the signal V1, that is, the potential V3 at node N, begins to fall from "H" to "low", and at time t3, the potential at node N3 begins to fall.
The potential of becomes L''. Then, “L” is applied to the gate of P-type MO8FET3, and this P-type MO8FET3
becomes conductive. At the same time, “H” of node N3
N-type MO8F whose potential change from to “L” is in a conductive state
It begins to propagate to the node N4 via ET5, and the potential 4 of the node N4 begins to fall from "H" to "L", and at time t4, the propagation is completed and becomes "L". And time t3-t4
The potential V4 of node N4 is between N-type MO8FET
When the voltage drops below the threshold voltage of node N2, the N-type MO3FE 4 enters the cut-off state, resulting in the output signal V of node N2, which was previously at "L"L". Ul begins to rise at time t, when the inherent delay time of CMOS inverter 2 has elapsed after the potential V4 of node N4 reaches the threshold voltage of N-type MO8FET4, and reaches the "H" level at time t6. Become. - Next, at time t7, when the input signal V 1- changes from "H" to "OFF", the P-type MO8FET1 becomes conductive, while the N-type MO8FET2 becomes cutoff. As a result, at time t, when the inherent delay time of CMOS inverter 1 has elapsed from time t7, the signal v1, that is, the potential ■3 of node N3, starts to rise from L'' to II H++, and at time t, the potential v3 of node N3 increases. °
Then, "H" is applied to the gate of P-type MO5FET3, and this P-type MO3FET3 becomes in a cut-off state.At the same time, the potential change of node N3 from "L11 to H" causes a conduction state. N-type MO8FET in
5 to the node N4, and the potential V4 of the node N also begins to rise from "L'" to HPI, and at time t
The propagation is completed at 11 and becomes H++. And time t
Between 9 and t11, the potential N4 of node N becomes N-type M
When the threshold voltage of O3FET4 is exceeded, N-type MO8
FET4 becomes conductive, resulting in “
Output signal V at H11 level. Uo is after the potential 4 of the node N4 reaches the threshold voltage of the N-type MO8FET4,
It starts to fall at time t10, when the inherent delay time of CMOS inverter 2 has elapsed, and at time t12, it reaches 1111 levels.

Here, the potential N4 of the node N changes from “HII” to “LI
Comparing the time required to reach I (14-13) and the time required to go from "L" to "HII" (tll-19), it is clear from Figure 2 that from L to "
The time required to reach H'' is longer.The reason for this will be explained below.

In the N-type MO8FET 5, when the voltage between the source and the bulk increases, the threshold voltage of the N-type MO8FET 5 also increases accordingly. Therefore, the potential v of node N
3 goes from "L" to "H" (if you think about it,
As the potential of the node N3 increases, that is, the source voltage increases, the threshold voltage of the N-type MO8FE 5 also increases, so the drain voltage is longer than the time required for the source voltage to go from "L" to "HIT". The time required to go from "L" to "L" is longer. On the other hand, when the potential of node N3 goes from "H" to "L", the potential of node N4 differs from the above case. The time required for the change from "H11" to "Shi" is beyond the above.

As described above, in this output buffer 7 circuit, the node N
When the potential ■3 switches from “L II” to “H”, N
Since the potential N4 of the node N4 applied to the gate of the N-type MO8FET 4 is gradually raised by the action of the MO8FET 5, the N-type MO8FET 4 also becomes conductive slowly, and the output signal V shown in FIG. 2 is generated. The falling waveform of UT is also more gradual than before. As a result, undershoot and ringing at the fall of the output waveform can be eliminated or reduced.

Note that the degree of fall of the potential V4 at the node N4 can be controlled by the gate length and gate width of the N-type MO8FET5, so by appropriately setting these gate length and gate width, the falling waveform of the output signal voU□ can be controlled. Can be adjusted freely.

Although the above description has been made using an example of an output buffer circuit consisting of two inverter circuits I 1 and I 2 , the present invention is also effective when the inverter circuit (2) is used alone.

〔Effect of the invention〕

As described above, according to the inverter circuit of the present invention, when the input signal changes from "L II to H", the change is made gradual by the second N-type transistor which is always on, and the first Since the output signal is applied to the gate of the first N-type transistor, the fall of the output signal output from the drain side of the first N-type transistor is gradual, undershoot and ringing are prevented or reduced, and the reliability is high. This has the effect of providing an inverter circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of an output buffer circuit constructed from an inverter circuit according to the present invention, and FIG.
Fig. 3 is a diagram showing an output buffer circuit constructed from a conventional inverter circuit;
The figure is a timing chart of FIG. 3. In the figure, 3 is P-type MO8FET, 4.5 is N-type MO8
FET-I2 has cMOs < 9. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In an inverter circuit that has a first N-type transistor whose source is grounded and an output signal is taken out from the drain side, a second N-type transistor whose gate is supplied with a positive power supply voltage so that it is always on is connected. An inverter circuit characterized in that an input signal is applied to the gate of the first N-type transistor through the gate of the first N-type transistor. (2) The inverter circuit according to claim 1, wherein the inverter circuit is a CMOS inverter.