JPH01113338U - - Google Patents
Info
- Publication number
- JPH01113338U JPH01113338U JP1988008511U JP851188U JPH01113338U JP H01113338 U JPH01113338 U JP H01113338U JP 1988008511 U JP1988008511 U JP 1988008511U JP 851188 U JP851188 U JP 851188U JP H01113338 U JPH01113338 U JP H01113338U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- evaluation
- bonding pad
- edge
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 4
- 239000011093 chipboard Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示す拡大概略平面
図であつて、Ａは評価用チツプ、１はチツプ基板
、２はボンデイング・パツド、３は評価用配線で
ある。
図であつて、Ａは評価用チツプ、１はチツプ基板
、２はボンデイング・パツド、３は評価用配線で
ある。
Claims (1)
- チツプ基板上の端部でボンデイング・パツドよ
りも外側に評価用配線を配して成るクラツク評価
用チツプ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988008511U JPH01113338U (ja) | 1988-01-26 | 1988-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988008511U JPH01113338U (ja) | 1988-01-26 | 1988-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01113338U true JPH01113338U (ja) | 1989-07-31 |
Family
ID=31214451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988008511U Pending JPH01113338U (ja) | 1988-01-26 | 1988-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01113338U (ja) |
-
1988
- 1988-01-26 JP JP1988008511U patent/JPH01113338U/ja active Pending