JPH01112812A - Phase comparator - Google Patents

Abstract

PURPOSE:To read a digital data stably by providing the two output means (1st and 2nd) to an output of phase comparison, combining outputs of the two output means so as to detect an error thereby generating a phase error voltage. CONSTITUTION:In giving a digital data and a phase comparison clock to a phase comparator 1, the phase comparison output of the both enters an output fixing circuit 2, where the output is controlled by a phase comparison control signal 1 to bring phase comparison outputs 1, 2 to a high impedance. The phase comparison outputs are combined by the phase error detection means and a phase error is detected to output the result. A phase error detection means 4 combines the signals from the phase comparison outputs 1, 2 to detect a phase error and output the phase error.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a phase comparator circuit that decodes a group of digital data that appears intermittently, and particularly relates to a phase comparator circuit that decodes a group of digital data that appears intermittently. The present invention relates to a phase comparator circuit that can read digital data.

(B) Prior Art Conventionally, as shown in Fig. 5, in the playback signal of a rotary head type digital audio recorder (hereinafter referred to as R-DAT), a time data signal of 7.5 ms appears, followed by (7.5 ms).
ms is an intermittent signal indicating that there is no data at all. Therefore, a period in which phase comparison between the read clock of the reproduced signal (digital data) and the reproduced signal (digital data) can be performed and a period in which it cannot be performed appears every 7.5 ms. Furthermore, if the period of digital data transmission lock is T, it is supposed to change as It, 2t, 3t, and 4t, and it must be the same period as the read clock and be phase-synchronized with the digital data. In the conventional phase comparator, as shown in FIGS. 2 and 4, the error between the change point of the digital data and the change point of the read clock is measured using one output terminal.

As for the phase comparison output, waveforms of various parts of the conventional circuit shown in FIG. 4 and the phase comparison output are shown in FIG.

In this case, the period of the digital data phase comparison clock must be 1/2 of the digital data transmission lock period T, and in the case of Japan-DAT, this period τ is I/9,408 MHz.
Therefore, the phase comparison clock required a frequency of 18.816 MHz. From Figure 6, the H part of the phase comparison output at this time is constant at T/4, and when comparing the change point of the phase comparison clock and the change point of the digital data, the digital data is ahead. In this case, (T/2) ~ (τ/4)
The length up to this point becomes L, and the L portion becomes longer. Conversely, if the digital data is delayed, (τ/2) ~ (0
) becomes L, and the L portion becomes shorter. During other periods, it is set to high impedance.

(c) Problems to be solved by the invention However, in such a phase comparator circuit, P L
L(7) VC○ oscillation frequency is 18.816MHz 2
The disadvantage is that the frequency is twice as high as 37.632 MHz, which makes operation by C-MOS difficult. In addition, as shown in Figure 6, the phase comparison output becomes high impedance after outputting the phase error, which has the disadvantage that it is difficult to obtain an accurate error voltage due to the influence of stray capacitance of the pattern during mounting. .

The present invention eliminates the drawbacks of the conventional example and makes it possible to stably read digital data during normal playback and search of a DAT using a phase comparator circuit that decodes digital data groups that appear intermittently. The purpose of this invention is to provide a phase comparator circuit that can

(d) Means for Solving the Problems Figure 1 is a block diagram showing the configuration of the present invention.
In a phase comparison circuit between digital data and a read clock of digital data of a digital data reproducing device in which groups of digital data appear intermittently in T) etc., the phase comparison circuit includes two output means, first and second, for the phase comparison output,
This phase comparator circuit is characterized in that it generates a phase error voltage by combining the outputs of these two output means and detecting an error.

(E) Operation In this invention, as shown in FIG. 1, when the digital data and the phase comparison lock are input to the phase comparator 1, the phase comparison outputs of both enter the output fixing circuit 2, where the phase comparison control is performed. The output is controlled by signal 1, and when the phase comparison control signal 1 is set to H, it is output through a three-state buffer circuit, and the phase comparison outputs 1 and 2 become high impedance.The 0 phase comparison output is a phase error detection means. It works to detect and output the phase error.

(F) Embodiment An embodiment of the present invention will be explained with reference to FIG. 1. Normally, a 7.5 ms data signal appears in the playback signal of a rotary head type digital audio recorder (R-DAT). , Continued (7.5 ms is recorded as an intermittent signal in which there is no data signal at all. Therefore, during playback, there is a period during which phase comparison between the digital data read clock and the digital data cannot be performed. This means that the period between the two times appears alternately every 7.5 ms.Also, if the period of the digital data transmission lock is τ, then 1t,
It is supposed to change at 2t, 3t, and 4t, and must have the same period as the read clock and be phase-synchronized with the digital data.

An embodiment of the present invention will be described below with reference to FIG.

When digital data and a phase clock are input, a data edge detection circuit 1 performs edge differentiation of the digital data.
a, a data phase lead detection circuit 1b that detects that the digital data is ahead of the phase by this signal, and a data phase lag detection circuit 1C that detects that the digital data is behind the phase clock. A phase comparator 1 consists of a logic circuit 1d that performs a logical operation to determine whether the output is ahead or behind; an output fixing circuit 2 that controls and fixes the output using a phase comparison control signal 1; Three-state buffer circuit 3 that outputs phase comparison outputs 1 and 2r8 depending on whether the data and phase comparison clock are ahead, in phase, or behind each other.
and a phase error detection means 4 which combines these signals from the phase comparison outputs 1 and 2, detects a phase error, and outputs the phase error.

FIG. 8 shows waveforms at various parts in FIG. 3 when the digital data is ahead of the phase comparison clock. Digital data is edge differentiated by EXOR (■
EXOR output).

This signal applies rising pulses to the D flip-flops ① and ②. Since the D input of the D flip-flop (2) is H, it outputs H to Q. Similarly, the Q of ■ remains H until the darkness of L. Therefore, the output on the 0th day of ■ has the same waveform as the Q output of ■. ■The D flip-flop is D at the rising edge of the phase comparison clock.
The input H is latched and the L is output from Q. The d of ■ is added to the B terminal of the D flip-flop of ■, and the Q of ■ is fixed up to H. 6 If the phase comparison control signal 1 is H, the output of ■ and the output of B of ■ are the AND of ■.
If 6 phase comparison control signals 2 are transmitted to the three-state buffer circuits of ■ and ■ through ○R of and ■, then ■ and ■ output the input signals and send the signals to phase outputs 1 and 2, respectively. Since the 0 phase error output is a combination of these signals, it becomes an output as shown in FIG.

FIG. 9 shows waveforms of various parts of FIG. 1 in the case where the digital data lags behind the phase comparison clock in the opposite case. The digital data enters the EXOR (2) and is edge differentiated. This output goes into the D flip-flops ① and ②. At this time, L is applied to the R terminal of the D flip-flop (2), and Q is always fixed at L. The input of the D flip-flop of ■ is H, and when the output of ■ is input, Q
becomes H(L:Q((t). The D flip-flop of ■ latches the H input of the D flip-flop at the rising edge of the phase comparison clock, resulting in Q1.tL. However, ■ The R terminal of is connected to the Q of ■.
When is H, QfJ<L of ■, or when it rises to H, Q of ■ becomes L, and when Q of ■ becomes L, the Ht ratio is output. Q of ■ and Q of ■ belong to ■.

Since the Q of (2) is always positive, the output of (2) and the Q output of D are transmitted to the subsequent stage. Further, the outputs of ■ and ■ are transmitted to the phase comparison outputs 1 and 2 through the three-state buffers of ■ and ■ if the phase comparison control signal 2 is valid. The phase error voltage at this time is as shown in Figure 9.0 When the phase comparison control signal 1 is set to H, the phase error output is fixed at (H+L)/2. This is for adjusting the free run frequency of the VCO connected in turn. Further, when the phase comparison control 2 is set to H, the phase error output also becomes high impedance. This is to maintain the oscillation frequency of the VCO that will be connected later for a while, and the phase comparison clock (this is created by the oscillation of vCQ) is set so that the phase error output is (+-1+L).
This is used when there is no digital data that is clearly different from the frequency when the frequency is /2. Specifically, the phase comparison is set to H when there is no RF signal during a search or the like.

(g) Effects of the invention As explained above, according to the invention, the phase comparison outputs 1 and 2 do not become high impedance during the phase comparison between the digital data and the phase comparison clock, thereby reducing the phase error. The voltage will be accurate. In addition, since there are two phase comparison output terminals, the cycle of the clock for phase comparison is only required, and the VCO (7) output i frequency is (2/T) = +8.81.
Since the frequency is 6MH2, which is half that of the conventional one, it is a frequency that is sufficient for C-MOS operation. Further, in the case of the conventional example, the phase comparison output has a variation range of ±7/4, whereas the present invention has excellent features such as a wide variation range of ±τ/2.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase comparator according to the present invention,
FIG. 2 is a block diagram of a conventional phase comparator. Fig. 4 is a circuit diagram of the phase comparator shown in Fig. 2, Fig. 5 is an RF waveform diagram of the R-DAT using the present invention, and Fig. 6 is a phase comparison output of the phase comparator shown in Fig. 2. FIG. 7 is a waveform diagram of the phase comparison output of the phase comparator in FIG. 1, FIGS. 8 to 9 are waveform diagrams when each part of FIG. 1 is operating, and FIG. 4 is a waveform diagram of each part in FIG. 4. FIG. 1: Phase comparator 1a: Data edge detection circuit 1b: Data phase lead detection circuit 1c: Data phase lead detection circuit 1d: Logic circuit 2: Output fixing circuit 3 Nissly state buffer circuit 4: Phase error detection means Patent application Fig. 8 ■ ExOR's blood power ■ EXOR's i power Fig. 10: 2.! LP-Yen 1 Convex 1=-f'-=-Ste 1 Procedure Neho Seisho (Method) November 1988 298 Sent September 22, 1988 Commissioner of the Patent Office Yoshi 1) Moon Takeshi, Lord 1, Incident Indication of 1986 Patent Application No. 86922 2, Name of the invention Phase comparator circuit 3, Relationship to the case of the person making the amendment Patent applicant address 2-17-5 Shibuya, Shibuya-ku, Tokyo Name
(359) Kenwood Co., Ltd. Statement”
“Drawing 6, Contents of Amendment (&) On page 12, line 14 of the specification, after ``...'', ``Figure 3 is a circuit diagram of the phase comparator in Figure 1.''
join.

Claims (3)

[Claims] (1) In a phase comparison circuit that performs a phase comparison between digital data of a digital data reproducing device in which a group of digital data appears intermittently and a read clock of the digital data, when the digital data and the phase clock are input, when the digital data A data edge detection circuit that differentiates the edge of the signal, a data phase lead detection circuit that detects that the digital data is ahead of the phase based on this signal, and a data phase lag detection circuit that detects that the digital data lags behind the phase clock. and a logic circuit that performs a logical operation to determine whether the data phase is ahead or behind; an output fixing circuit that controls and fixes the output using a first phase comparison control signal; A second phase comparison control signal determines whether the digital data and the phase comparison clock are ahead, in phase, or behind each other, and outputs a phase comparison output. A three-state buffer circuit comprising a comparison output means and outputting the first and second phase comparison outputs, and detecting a phase error by synthesizing these signals from the first and second phase comparison outputs. and phase error detection means for outputting a phase error. (2) The first and second output means of the phase comparator circuit do not become high impedance at least while a digital data group appears. phase comparison circuit. (3) In the phase comparison circuit, if it is clear that there will be a difference between the digital data read clock and the digital data readout clock when no digital data group appears, the output means of the phase comparison circuit is set to high impedance. A phase comparator circuit according to claim 1, characterized in that: