JPH01112453A - Information storing device for magnetic recording device - Google Patents

Abstract

PURPOSE:To easily give necessary information for trouble survey by providing an information converting part to arbitrarily edit external information and internal information and to output them to a storing part. CONSTITUTION:An information converting part 14 adds a bit value, which shows the information are effective, to a deciding bit on a signal line 27 according to the encoded information on a signal line 6 and a control signal on a signal line 7b to instruct the fetching of the information. In a control part 15, a memory address is sent to a signal line 25 to store the information on the signal line 27 to a storing part 11 and a memory write signal is sent on the signal line 25. Thus, the bit value is provided and the bit value is added to show that all storing information are ineffective to the deciding bit when there is no guarantee for the storing information. Then, the rewriting of initial data can be executed. Accordingly, even in case of using as the information of the trouble survey of a sub-system, erroneous decision is not given.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to fault detection in a magnetic recording subsystem, and more particularly to an information storage device that provides information necessary for fault detection.

(Prior Art) Conventionally, fault detection in a magnetic storage subsystem has been performed by collecting and analyzing fault information detected in each device constituting the subsystem. However, there are cases where the cause of the failure is not due to the time of failure detection but to past operations, and it is effective to know the operation history of each device that makes up the subsystem. What is the operating history of such a device? An information storage is provided for storage.

An information storage device is a device that accumulates information that specifies the operation history of a device, such as instructions processed by the device and input/output information, over time, and provides the accumulated information upon request. .

FIG. 1θ is a block diagram showing an information storage device located within the device. In FIG. 10, 1 is an information storage device, 2
3 is a maintenance diagnosis processing section, 4 is a device control section, and 5 is a device. Further, 6.9 is a signal m carrying 7'L information, 7.8 is a signal line carrying a control $ll signal, and 10 is a signal line carrying a command signal.

The functional blocks in FIG. 1 only show those directly related to the operation of the information storage device 1. As shown in FIG. The device control unit 4 controls the device 5
decodes the received command, controls each part of the device to execute the command, and sends the received command to the information storage 1 and information encoded so that the execution process can be decoded onto the signal line 6. A control signal is generated on the signal line 7 to designate its capture. Upon receiving the above signal, the information storage device 1
The information on the signal line 6 is taken in and stored in accordance with the designation of the control signal above. An index signal indicating the operating state and information accumulation state is output onto the signal line 10, and accumulated information specified by a control signal received from the maintenance diagnosis control unit 2 via the signal line 8 is output onto the signal line 9. .

The maintenance diagnosis control section 2 controls maintenance diagnosis processing as a component of the maintenance diagnosis processing section 3 together with the information storage device 1. on the other hand,
For the information storage device 1, the maintenance diagnosis control section 2 specifies target information while referring to the index signal on the signal line 10 in response to an operation in the maintenance diagnosis processing section 3 or a request for information by an external command. A sixth control signal is generated on the signal line 4 to extract the stored information onto the signal line s, and the extracted information is presented to the requester.

Conventionally, the information storage device 1 described above uses a storage element that electrically stores information, stores and presents information while the device is in operation, and retains the stored information using an auxiliary power source when the device is stopped. We are hiring. Newer information is given priority, and when the amount of information exceeds the storage capacity of the information storage device 1, the oldest information is discarded and replaced with newer information in sequence.

Therefore, initialization of information has been performed under external control or has been deemed unnecessary.

(Problems to be Solved by the Invention) In the conventional information storage device described above, information is initialized only by an external signal generated by a command or operation. Therefore, there is a drawback that the stored information cannot be guaranteed after the effective period of the information retention function by the auxiliary power supply has elapsed even when the device is powered on for the first time or when it is powered on again.

The above information: is used as information for fault detection,
If the information is incorrect, there is a risk of confusion and an incorrect decision. Furthermore, there is a drawback that if an incorrect mental judgment is made, it may develop into a more serious disorder.

When the power is turned on, all functions are generally initialized, and in this case, the stored valid information is also discarded unconditionally, which is a drawback.

The purpose of the present invention is to store input information in the order of input and address order, to make it possible to read out information at any address, and to remove the above-mentioned drawbacks by retrieving information in order of addresses, and to detect faults. An object of the present invention is to provide an information storage device of a magnetic recording device configured so that necessary information can be easily provided.

(Means for Solving the Problems) An information storage device of a magnetic recording device according to the present invention includes a storage section,
The memory section b, which is composed of a power supply section, an IF bell generating section, an information conversion section, and a control section, has an independent power supply path and can write/read information arbitrarily. This is the sixth type that can be specified and stores information electrically.

The power supply unit is intended to supply power to operate the storage unit and retain information.

The IIF bell generating section is a precautionary device that generates an alarm signal according to the output state of the power supply section.

The information conversion unit is for arbitrarily editing external information and internal information and outputting the edited information to the storage unit.

The control unit is on the 11th floor! This is for generating an external response index signal and a control signal for each of the above sections by referring to the signal and the external control signal.

(Example) Next, the present invention will be explained with reference to Drawing i.

FIG. 1 is a block diagram showing one embodiment of an information storage device according to the present invention.

In FIG. 1, 1 is an information storage device, 11 is a storage section, and 12 is an information storage device.
1 is a power supply unit, 13 is a power generation unit, 14 is an information conversion unit,
15 is a control section.

FIG. 2 is a block diagram showing one embodiment of the storage unit 11;
The figure is a block diagram showing an embodiment of the power supply section 12 and the alarm generating section 13, and FIG. 4 is an embodiment of the information conversion section 14.
FIG. 5 is a block diagram showing one embodiment of the control section 15.

In Figure 2, 301 and 302 are respectively de:ff-
da, 303, 305 are buffers, 304.30 respectively
8. 306 are memories, and 307 is a D-type flip-flop. In Figure 8, 401 and 402 are inverters, 403 and 404 are capacitors, respectively.
405 is a comparator. In Figure 4, 501
is a D type flip-flop, and 502 to 50S are A type flip-flops.
It is an ND gate. In Fig. 5, 601 to 603 degrees and 606 to 616 are D-shaped lips 70 and 60, respectively.
4 is a binary counter, 605 and 605 are each AN
D10R gate 617 is a clock generator.

In FIGS. 1 to 5, information is stored in response to instructions from the parent device. Coded information on signal line 6;
A control signal on the signal line 7b instructs the import,
The information converter 14 in FIG.
The information is put on standby, and a bit value indicating that the information is valid is added to the determination bit on the signal line 2F by the AND gates 502 to SOS.

On the other hand, in order to store the information on the signal line 2F in FIG. 4, the control unit 15 in FIG. 5 sends out the memory address to the signal line 2Sd, and sends out a memory write signal to the signal line 2Sa. A clock signal To generated by the D-type flip 70 knobs 601 to 803 and an internal clock generator 617 generates a timing pulse based on the control signal on the signal line 7b. So, the memory address on signal 1125d? At the same time, a memory write signal is generated on the signal 112sa. The memory address on the signal line 2Sa is set by a synchronous binary counter 604,
Each time you input information, count by 1 and connect signal line 10b.
Upper count value tl - AND10R gate 605.60
5 to select and output. The count value of the binary counter 604 is increased by % each time the color/return 604 overflows.
Return to Ol and repeat for the count.

In the storage unit 11 in FIG. 2, a memo I7306.

306 and decoders 301 and 302 correspond to storage elements for the number of addresses that can be specified by the memory address on the signal line 25d, and the number of bits of information input from the signal line 2F for each address. Write information/! 5! Make a delivery. The controller 15 receives address designation using the memory address on the signal line 2Sd, and the signal line 2Sa is
When the above memory write signal becomes active, the information converter 14 writes the awaited information on the signal line 27 to the designated memory address, and simultaneously writes and stores the memory address in the memory 304.

Therefore, the stored information input from the parent device is converted and stored in the order of input and address, and information for determining the validity of the stored information is added to the stored information.

FIG. 6 is a timing diagram showing the information storage operation.

Information is read by referring to the count value on the signal fII 1106 indicating the memory address where the latest information is stored. That is, information is read out in response to an address signal on signal line 8b set to obtain past information and a sideways signal on signal line Ba requesting reading. The output of the D-type flip-flops 606 and 607 and the clock signal T0 from the clock generator 61 and 75 determine the timing based on the signal on the signal line 8a. control, AND1
0R gate 608. At SO8, the address signal on the signal line Sb is selected and output as a memory address onto the signal line 2Sd. At the same time, a memory out signal is sent onto the signal line 1Sb, and after timing is taken until the read information is finalized, a latch signal for the read information is set on the signal 1125c. Furthermore, an index signal indicating the completion of reading on the signal line 10a with timing? to report completion of the read operation.

In the storage section 11 of FIG. 2, when the memoriat signal on the signal line 2Sb becomes active, the output of the write data buffer 303 on the signal line 27 is cut off, and the output of the write data buffer 303 on the signal line 2Sb is cut off.
The output of the storage element specified by the memory address on Sd becomes active, and the information stored at the specified memory address is output. In this state, a latch signal is input onto the signal line 25c, and the read information is secured in the D-type 2 lip 70 tube 307. When the index signal on the signal @10a indicating the completion of reading is reported, the information requester reads the output information on the 1st occupancy code line 9, refers to the determination bit, confirms that it is valid, and uses it. By tracing the memory address designated by the address signal on the signal line 8b and reading the stored information, the operation history of the parent device can be known.

When receiving a control signal instructing to take in information from the signal line Fb during a read operation, the control section 15 in FIG. 5 suspends the read operation and takes in the information, giving priority to the operation. When the D-type flip-flops 602 and 603 for holding control start operating, the D-type flip-flops 70 and 606 for readout control start operating.
608 enters a forced reset state, and the tiger accumulation operation described above is performed.

After the storage operation is completed, the D-type flip-flop 602.60
Upon returning to the 375E17 set state, the DE-type rough flip-flops 606 to 608 are reset and the read control is repeated.

FIG. 7 is a timing chart showing an example of the operation of the read system.

Even after the power of the main body is cut off, the information in the memo U3G4゜3os, 3os (memo U3G4゜3os, 3os) in the storage section 11 of FIG.

When power is applied to the main body and the control signal on the signal line 28a becomes active, the driver 401 is driven in the power supply unit 12 in FIG. Instead of supplying the power, switch to supply it from the power supply Vce of the main body. At the same time, the control signal on the signal line 21a which sets the operation mode of the storage element is switched to the M mode. When the set-up sequence described below is completed and the control signal on the signal line 26b becomes active, the relay RL2 operates and starts accumulating charges in the backup power supply capacitor 401.

The signal line 26a is where the main unit's power is cut off.

The control signal on 26b becomes inactive and relay R
Both L1 and RL2 are restored and the main body power is cut off. At the same time, the control signal on the signal line 21m also sets the operation mode of the storage element to standby. At this time, power line 2
Power from 1b to the storage element is supplied from a backup power supply capacitor 404 (7) IF accumulated charge. In addition, instantaneous disconnection when switching the power supply source can be achieved by using the capacitor 40.
Supplement with the accumulated charge of 3.

Therefore, even after the power to the main body is turned off, the previous operation history can be stored and stored. However, there is a limit to memory retention by the backup power supply, and if the backup power possessed by the power supply section 12 runs out, the stored information cannot be guaranteed.

The information storage device 1 makes this determination when the main body is powered on.

Upon receiving the control signal on the signal line F from the parent device indicating power-on, the control section 1S in FIG. Before supplying power from the main body to the backup power source, the Q-tone signal output from the alarm generator 13 onto the signal line 22 is read.

The third alarm generating section 13 uses a comparator to determine the state of charge accumulation in the backup power supply capacitor 401 supplied from the power supply section 12 based on a voltage value. A value with a sufficient margin is set with respect to the limit value that guarantees memory retention of the memory element, and the comparator 405 compares this value with the voltage value of the charge accumulated via the signal line 22. The output of the alarm signal on the signal line 23 is inverted depending on the magnitude relationship. It is set so that when the voltage value of the accumulated charge on the signal line 22 is larger, the IIF signal on the signal +Wa 23 becomes logic@0.

The control unit 15 in FIG. 4 reads the 1IiF bell signal on the signal line 23 at the rising edge of the output 0 of the D-type flip-flop 610, and then reads the signal line 2aa
Activate the control signal above to supply power from the main body to the memory element of the memory unit 11 via the power supply unit 12-,
Switch to normal operating mode. When entering the set-up sequence, the control unit 1S operates the D-type flip 70 knobs 612 to 6.
The timing is controlled by the output of No. 14 and the clock T to generate a control signal A141 (No. 8) for setup. When the reset is released, the D-type flip 70 knob 612
The D-type flip-flop 613 generates one cycle timing with four clocks by mutual set/reset relationship, and the D-type flip-flop 614 is set when its first cycle is completed. The set-up sequence is activated by determining the alarm signal on the signal line 23 that was previously read.

When the D-type flip 70 knob 615 is set and the stored information is not guaranteed, all the information in the storage section 11 is rewritten to initial data to prevent the information from being used erroneously. When the D-type flip-flop 615 is set, the control on the signal line 24! The ill signal becomes active, a pit value indicating invalidity of data is added to the judgment pit sent from the information converter 14 onto the signal line 27S, a code for the initial data is set, and the information is transferred to the signal line 27S.
) is output on top.

In the control unit 15, the output of the binary counter 604 is selectively outputted from the AND10R gate SOS, and outputted onto the signal line 25d as a memory address. When the D-type flip-flop 611 is set to start the sequence, the D-type flip-flops 612 and 613 operate in conjunction with each other, and the D-type flip-flop 612 uses the clock (CLO) of the binary counter 604 that specifies the address.
CK) signal, and the D-type flip-flop 813 outputs a memory line l (M number), which instructs writing to the storage element, on the signal #!2ga.

D-type flip-flop 614 layers unset first
In the cycle, since the D-type flip-flop 61g is set, the RESgT input of the binary counter 604 becomes active.

The binary counter 604 is reset at the rise timing of the D-type flip-flop 612 in the fa1 cycle. This value is output on the signal line 2Sd as a memory address, and since the M & D type rough flip-flop 618 is set, a memory write signal representing the set width of the D type flip-flop 6130 is output on the signal line 2Sa, It is written to memory address O as initial data.

From the second cycle onward, the binary input 9-interface 604 enters the count-up mode, and the value of the memory address on the signal line 2Sd changes in order with the CLOCK signal of the set width of the D-type flip-flop 612, and each time the memory write signal is It is output onto the signal line 2Sa. By repeating the above operations, initial data is sequentially written into the storage section 11.

When the count value of the binary counter 6040 reaches the maximum value, the CARRY output becomes active, and after writing to that address is completed, the D-type flip-flop 616 is set and the D-type flip-flop 615 is reset. When the D-type 7 lip-flop 61s is reset,
The D-type flip 70 knobs 612 and 613 are also reset and stop operating. At this time, the index signal on the signal line 10c indicating the completion of set-up becomes active, the set-up sequence is completed, and at the same time, the control signal on the signal line 26b becomes active and the charge in the backup capacitors 403 and 404 is reduced. Accumulation begins. Once setup completion is reported, the parent device begins normal operation.

FIG. 8 is a timing chart showing the operation at this time.

Next, when entering the set-up sequence, the storage unit 11
The following describes the operation when the information is guaranteed. When the D-type 7 lip-flop 615 is in the reset state, it returns the information storage 1 to the operating state in which it was previously powered off.

As a result, the above-mentioned D-shaped lip-flop 612°6
Only 13 @1 cycles work and finish. At this time,
Since the D-shaped lip 70g 615 is not set, the LOAD input of the binary counter 604 is more active. This signal is for switching the address memory to read mode, and the control on signal line 2Se is
The signal is also sent to the storage unit 11 in FIG. 8 as a signal. Storage part 1
1, the buffer 30 receives the control signal on the signal line 2Se.
5 is cut off, the memory 304 is set to output mode, and the data is stored there. At this time, the last address information written in the previous operation -% & row 6 is signal 111i! 28
is output above.

Therefore, the content of the information on the signal line 28 is taken into the binary counter 604 at the rising timing of the D-type flip-flop 812. Since the D-type rip-flop 615 is in the reset state, the D-type 7 rip-flop 6130
Neither the set width nor the memory write signal is output on signal #25a.

When the first cycle is completed, the D-type flip-flop 614
is set, and l? is set in the D-type flip-flops 612 and 613. Once set, the operation stops. Mana, the binary counter 60441 LOAD input is out! f! The normal count-up mode is entered, and the address memory of the storage unit 11 is also returned to the write mode. Then, the index signal on the signal line 10c indicating the completion of the set-up becomes active, and the set-up sequence is completed.

FIG. 9 is a timing chart showing the operation at this time. Therefore, if there is an instruction to take in information from the parent device after this, the above-mentioned take-in control is performed, and information storage can be resumed from the next address where the last information was stored.

(Effects of the Invention) As explained above, the present invention stores input information in the order of input and in the order of addresses, makes it possible to read n information from any address, and extracts information in the order of addresses. This has the advantage that it is possible to easily know the operation history of the parent device that gave the input information, and that the information can be retained by the backup power supply even when the main body is powered off.

The stored information is equipped with a judgment pit that indicates the authenticity of the information to prevent it from being used incorrectly, and is also equipped with a backup power supply check function, so when the storage information is no longer guaranteed, the judgment bit is set. With Jin whose entire memory information is invalid? The reliability of the stored information is improved by adding the indicated bit value and rewriting the initial data. Therefore, the memory information of Honzuke@Memory 4 is highly reliable, and there is no risk of making a wrong judgment even when it is used as information for subextem fault detection r, and the effect is that it can be used effectively for a long period of time. I don't like it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information storage device of a magnetic recording device according to the present invention. 2 to 6 are block diagrams showing each element constituting the information storage device Jk of the magnetic recording device shown in the FIN diagram. FIGS. 6 to 9 are timing charts showing the operation of FIG. FIG. 10 is a block diagram showing one row in the information storage device 3 of a magnetic recording device according to the prior art. 1--Information recorder 11...Storage unit 12...Power supply unit 13...Alarm generating unit 14...Self information exchange unit 15...Control unit 301.302---Decoder 303.305・・Working buffer 304.306.3060・・Memory 307.501.601~603.606~616・・
・D-type flip-flop 401.4020--Inverter 403.404--Capacitor 405--Comparators 502-505--AND gate 604-S binary counter gos, gog---AND10R gate 617...
Clock generator RLl, RL2...Relay

Claims (1)

[Claims] It has an independent power supply path so that writing/reading of information can be designated as desired, and a storage section for electrically storing the information, and a power supply for operating the storage section and retaining the information. a power supply section for supplying a power supply; an alarm bell generation section for generating an alarm signal according to the output state of the power supply section; and an alarm bell generation section for arbitrarily editing external information and internal information and outputting the edited information to the storage section. A magnetic recording device comprising: an information conversion section; and a control section for generating an external response index signal and a control signal for each section by referring to the alarm signal and the external control signal. Device information storage.