JPH01109745A - Semiconductor layout equipment - Google Patents

Abstract

PURPOSE:To eliminate defects by real wiring length simulation, by inputting virtual wiring length added to logic connection information, and performing layout in which the virtual wiring length is set as limit value at the time of layout, and real wiring length does not exceed the limit value. CONSTITUTION:Logic connection information 1 is input to a virtual wiring length simulation equipment 2, which calculates virtual wiring length, performs simulation, verifies logic and timing, and outputs virtual wiring length 6. When the result of this simulation coincides with the developer's expectation, the logic connection information 1 and the virtual wiring length 5 are input to a semiconductor layout equipment 3, which set the virtual wiring length as limit value, and performs layout in which real wiring length does not exceed the limit value. The real wiring length 6 is input to a real wiring length simulation equipment 4, which performs final verification. Therefore decreasing defects in the real wiring length simulation after layout.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor layout device.

[Conventional technology]

FIG. 2 shows a development flow diagram of a conventional L8 process, etc., and shows a virtual wiring length simulation device 121. It consists of a semiconductor layout device 13) and an actual line length alignment device (41).

Next, the VC operation will be explained. The virtual wire length simulation device (21) inputs the logical connection information, calculates the virtual wire length, performs virtual simulation, and verifies logic and timing.

If the result is as expected by the developer, then the semiconductor layout device 13 inputs the logical connection information 1111+, performs layout, and outputs the actual wiring length (6).

Next, the actual wiring length; 6) and the logical connection information +11 are inputted to the actual wiring length simulation device +41, and the actual wiring length simulation is performed for final verification 4.

[Problem that the invention seeks to solve]

Conventional semiconductor layerer)! ! [#-1 Because the data is used as above, the virtual wire length simulation data is not effectively used when laying out the data, and even though it has been verified effectively and timing-wise with the virtual wire length simulation. However, there was a problem in that problems occurred during actual wiring length simulation.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor layout device that effectively utilizes virtual wiring length simulation data.

[Means to resolve the issue]

The semiconductor layout apparatus according to the present invention is configured to input virtual wiring length in addition to logical connection information.

[Effect]

The input virtual wiring length acts as a limit value during layout, and layout is performed so that the actual wiring length does not overlap the virtual wiring length.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 shows a development flow diagram of the L8 process of the present invention, which is composed of a virtual wire length simulation device +21, a semiconductor layout device) 31, and an actual wire length simulation device 141, similar to the conventional technology shown in FIG. In this invention, the Vi virtual wire length simulation device +21 outputs the virtual wire length +51 for semiconductor layout! i i
ll 131.

Next, the operation will be explained.

Logical connection information...ft virtual wiring length simulation device 1
21 is input and the virtual wiring length? Calculate, perform virtual simulation, verify logic and timing, and output virtual wiring length +61. If the result of this virtual simulation is the value expected by the developer, then logical connection information... and virtual wiring length + 51 f semiconductor layout equipment +
31, and layout is performed so that the actual wiring length (6) does not exceed the virtual wiring length 161 as a limit value.

Next, the actual wire length 161 is input to the actual wire length simulation device (41) for final verification.

In the above embodiment, the semiconductor layout device 13) is the virtual machining head name 6)? I showed the case where I input it, but
The delay time calculated by virtual simulation may be input and converted into a virtual wiring length in the semiconductor layout device (3).

〔Effect of the invention〕

As described above, according to the present invention, since the virtual wiring length r is set as the limit value when performing layout, the data of virtual simulation can be effectively used during layout, and it is possible to solve problems in actual wiring length simulation after layout. This has the effect of reducing the occurrence of t#.

[Brief explanation of the drawing]

FIG. 1 is a development flow diagram of an L8 construction, etc., showing an embodiment of the present invention, and FIG. 2 is a development flow diagram of a conventional LB construction, etc. In the figure, 111 is logical connection information, 121 is a virtual wire length simulation device, (31 is a semiconductor layout device, +41 is an actual wire length simulation device, +61 is a virtual wire length, and (6) is an actual wire length. In addition, in the figures, the same reference numerals indicate the same or...outside the relevant parts.

Claims (1)

[Claims] A semiconductor characterized in that a virtual wiring length used in a virtual wiring length simulation performed before layout is input, and this virtual wiring length is used as a limit value, and layout is performed so that the actual wiring length after layout does not exceed this limit value. Layout device.