JPH01109452A - System for controlling erasion of translation lookaside buffer information - Google Patents

Abstract

PURPOSE:To efficiently erase translation lookaside buffer information over all processors by erasing a self translation lookaside buffer with the processor issued the instruction of the translation lookaside buffer erasion and immediately starting the next processing when the reception of the translation lookaside buffer erasion instruction is confirmed. CONSTITUTION:When the translation lookaside buffer erasion instruction is issued to other instructing processors 2 and 3 by a system processor 4, an instructing flag to show this operation is turned on by a flag processing procedure 4 and when erasing processing is finished by the instructing processors 2 and 3, which receive the instruction, the instructing flag is turned off. A completion confirming procedure 42 detects the preceding processing of the translation lookaside buffer erasion is completed by investigating the instructing flag. A processor 1, which issues the instruction of the translation lookaside buffer erasion, executes the erasion of the self translation lookaside buffer and when the reception of the translation lookaside buffer erasion instruction is confirmed, the next processing is immediately started without receiving the erasion processing completing information from the other processors 2 and 3. Thus, system efficiency can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a storage management control method in a multiprocessor configuration that shares memory, and aims to improve the efficiency of erasing conversion index buffer information across all processors. A conversion index buffer information deletion control method in a multiprocessor system equipped with a conversion index buffer that converts virtual pages and real pages, and a system processor that controls the system, in which two instruction processors erase the conversion index buffer. When an instruction is issued, when a conversion index buffer deletion instruction is issued to another instruction processor in the process performed by the system processor, an instruction flag indicating this is turned on, and the instruction processor that received the instruction finishes the deletion processing. A system processor that has received a conversion index buffer deletion instruction includes a flag processing procedure for turning off the instruction flag, and a completion confirmation procedure for detecting completion of the previous conversion index buffer deletion process by checking the instruction flag. ,
If the completion of the previous conversion index buffer deletion process is confirmed by the completion confirmation procedure, the processor that issued the conversion index buffer deletion instruction will notify the reception of the command, and the processor that has issued the conversion index buffer deletion command will erase its own conversion index buffer, and delete the conversion index buffer. If acceptance of the buffer erase command is confirmed, the next process is immediately started without receiving a notice of completion of the erase process from other processors.

[Industrial application field]

The present invention relates to a storage management control method in a multi-processor configuration that shares memory.

In processors that use virtual memory, Translator is a hardware that performs dynamic address translation from virtual pages to real pages at high speed.
ation Lookaside Buffer (generally referred to as TLB, hereinafter referred to as TLB)
It is common to have the following.

As shown in Figure 3, each processor (IPU-0, IP
TLB (TLB-0, TL
In a multiprocessor system with B-1, TL:B-2), the uniqueness of virtual pages and real pages is determined in the TLB of each processor, which is retrieved from the segment table in main memory that indicates the correspondence between virtual pages and real pages. In order to guarantee this, it is necessary to simultaneously erase the corresponding items of virtual pages and real pages that no longer correspond across all processors.

The present invention relates to an efficient processing method for such erasure.

[Conventional technology]

In a multiprocessor configuration equipped with a TLB, it is necessary to simultaneously erase correspondence items between virtual pages and real pages that no longer correspond to each other across all processors, and this process is performed as shown in the example shown in FIG.

In Figure 4, IPU-0, 1PU-1, 1PU-2
is an instruction processor (Instruction Processing U) that constitutes a multiprocessor system.
nit), and the SPU is the system processor (System Processing U) that controls the system.
nit).

■Each IPU performs address translation using its own TLB, but when you want to invalidate a page (for example, to replace a page due to a page fault) (for example, IPU
PU-1), erase command P P T L B (Part
ial Purge TLB) and other I to Spu.
Requests a PPTLB processing instruction to the PU.

■spu once instructs IPU-0 and IPU-2 to stop (STOP), then TLB purge (f!
Instruct A effect).

■Each IPU performs a designated page search.

■Each IPU resumes processing (RIJN).

(Problems to be Solved by the Invention) In the actual erasure processing (PPTLB processing), in order to guarantee the simultaneity of erasure, as shown in FIG. It is necessary to wait for the completion of deletion of the corresponding items of each processor.

Therefore, there is a problem that it takes a long time to wait for communication processing and completion of erasure.

The present invention aims to provide a conversion index buffer erasure control method that eliminates such conventional problems.

[Means for solving problems]

FIG. 1 shows an instruction processor (IPU) that constitutes the erasing system of the conversion index buffer of the present invention.

4 is a system processor (SPU) that controls the system
It is.

Reference numerals 11, 21, and 31 denote translation lookaside buffers (TLBs), which are provided in each instruction processor and perform dynamic translation between virtual pages and real pages.

41 is a flag processing procedure, in which when the system processor 4 issues a conversion index buffer deletion instruction to other instruction processors 2 and 3, an instruction flag indicating this is turned on, and the instruction processors 2 and 3 that have received the instruction erase the conversion index buffer. When the processing is completed, the instruction flag is turned off.

42 is a completion confirmation procedure, in which it is detected that the previous conversion index buffer erasing process has been completed by checking the instruction flag.

[For production]

Each IPUI, 2.3 performs address translation using its own TLB and executes the job, but one IPU
(For example, in 1), a page fault occurs and the T L I3 erase command (PPTLB) is issued to replace the page.
is issued, issues a PPTLB instruction to 5PU4.

(See Figure 1 (b) φ).

In 5PLJ4, the previous ppTL is
When the completion of B is confirmed, a PPTLB acceptance notification is issued, a stop instruction is issued to other IPUs (2, 3), and other rpu (
2, 3) stops, PPTLB is instructed, and the flag processing procedure 41 turns on the instruction flag.

When the completion of PPTLB is reported from the other IPUs (2, 3), the instruction flag is turned off and the other IPUs (2, 3) are instructed to restart the job.

After the IPUI that issued Pr'TLB erases its own TLB and confirms the reception of PPTLI3 from 5PU4, it can immediately execute the next command without waiting for the completion of PPTLI3 in other IPUs. Start.

To delete TLB information, there are two ways to delete the TLB information: ■ Release the area on the virtual memory that is no longer in use, and ■ Paging (the supervisor who manages virtual memory replaces pages between the real page area and the virtual page area as necessary). There are cases where a real page is replaced with another virtual page in page control such as processing that performs a virtual page. In the case of ■, the page is not being accessed by any other processor. In the case of (2), there are (a) a case involving input/output and a) a case not involving input/output.

Now, issue PPTLB and other processors will issue PPTL.
Let Ta be the time until B is executed.

On the other hand, in the case (2) above in the processor that issued the PPTLB, let Tb be the time from when the PPTLB is issued until the job waiting for the completion of page control is restarted.

At this time, the following relationship holds true: Ta <<'l'b (no input/output) x Tb (with input/output). In a typical example, Ta is about 50 steps x (average instruction execution time), and Tb is about 300 steps x (average instruction execution time) when there is no input/output.

Therefore, the processing of PPTLB is
Simply requesting PTLB eliminates the need to wait for completion.

As a result, it is possible to reduce the number of times of communication between processors, reduce the time required to wait for processing by other processors, and improve system efficiency.

〔Example〕

FIG. 2 is a flowchart showing the processing of one embodiment of the present invention.

The processing according to this embodiment will be explained below according to each step of the flowchart.

■When one IPU wants to invalidate a page, the PP
Issue a TLB command.

■Request the SPU to issue PPTLB instructions to other IPUs.

■The SPU receives the PPTLB instruction.

■The SPU checks whether the previously accepted PPTLB has been completed or not and whether the instruction flag is off.

It is checked by detection, and if it is off, it jumps to step (2), and if it is on, it goes to step 0.

(2) Wait for the previous PPTLB to be completed (the instruction flag is off), and when it is completed, proceed to step (2).

(2) The IPU issuing PPTLB executes its own PPTLB.

■Wait for the completion of PPTLB, and when it is completed, proceed to step ■.

(2) When the SPU completes the waiting, it sends a PPTLB instruction acceptance notification to the IPU that issued the PPTLB, and proceeds to step [phase].

■The IPU that issued the PPTLB is the PPT from the SPU.
After confirming the LB acceptance notification, processing of the next command is started.

@SPU sends a stop command to other IPUs.

The IPU stops at the end of the macro instruction currently being executed and notifies the SPU of the stop.

ospu receives a report of an IPU outage and
Instruct PPTLB to

◎Turn on the instruction flag corresponding to the IPU that instructed PPTLB.

[Phase] Wait for the PPTLB completion report from the tpu that instructed PPTLB.

The IPU instructed to @PPTLB erases the specified page of its own TLB. (PPTLB) @PPTLB
The IPU that has finished reporting the completion to the SPU.

The ospu turns off the instruction flag corresponding to the IPU that reported PPTLB termination.

@SPU issues a start instruction to other IPUs and makes them wait for the next process. Upon receiving the start instruction, the IPU starts the job whose execution is currently suspended.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the number of communications between processors and shorten the exclusive acquisition time for shared resources, and it is particularly effective in systems with few memory resources and frequent paging. The effect of contributing to improving system efficiency is extremely large.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a flowchart showing the operation of an embodiment of the present invention, Fig. 3 is a diagram explaining invalidation of TLB information in a multiprocessor configuration, and Fig. 5 is a conventional 12 is a flowchart showing PPTLB processing of FIG. In the drawing, 1.2.3 is an instruction processor (IPU), 4 is a system processor (SPU), 11, 21.31 is a translation lookaside buffer (TLB), 41 is a flag processing procedure, 42 is a completion confirmation procedure, are shown respectively. Principle block diagram of the present invention ffi IPU that performs PPTLB once 5 days M
Flowchart illustrating the processing according to an embodiment of the present invention - Diagram illustrating the operation of TLB in a multiprocessor configuration Figure 3 T!B in a multiprocessor configuration ,B No information] Figure 4 to explain blasphemy

Claims (1)

[Claims] Instruction processors (1), (2), (3) that share memory and
) Conversion index buffer information in a multiprocessor system equipped with conversion index buffers (11), (21), and (31) that convert virtual pages and real pages for each page, and a system processor (4) that controls the system. In this erasure control method, when one instruction processor (1) issues a conversion index buffer deletion instruction, the system processor (4) issues a conversion index buffer deletion instruction to other instruction processors (2) and (3). A flag processing procedure (41) in which an instruction flag indicating this is turned on when a buffer erase instruction is issued, and the instruction flag is turned off when the instruction processors (2) and (3) that received the instruction complete the erase processing. and a completion confirmation procedure (42) for detecting that the previous conversion index buffer deletion process is completed by checking the instruction flag, and the system processor (4) that has received the conversion index buffer deletion instruction performs the completion confirmation procedure (42). When the completion of the previous conversion index buffer erasing process is confirmed in step (42), the processor (1) which has issued the conversion index buffer erase instruction notifies the reception of the instruction and executes the erasure of its own conversion index buffer. , if the reception of the conversion index buffer deletion command is confirmed, other processors (2), (3)
A conversion index buffer information deletion control method characterized in that the next processing is started immediately without receiving a deletion processing completion notification from the conversion index buffer information.