JPH01108745A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01108745A JPH01108745A JP62267162A JP26716287A JPH01108745A JP H01108745 A JPH01108745 A JP H01108745A JP 62267162 A JP62267162 A JP 62267162A JP 26716287 A JP26716287 A JP 26716287A JP H01108745 A JPH01108745 A JP H01108745A
- Authority
- JP
- Japan
- Prior art keywords
- external
- terminals
- signal line
- terminal
- grounding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 14
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は半導体装置、特にマイクロ波帯〜準ミリ波帯
ＭＭ Ｉ Ｇ （＝ Ｈｏｎｏｌｉｔ旧ＣＨｉｃｒｏｗ
ａｖｅ ＩｎＬｅＱｒａｔＯｄ Ｃ１ｒｃｕｉｔ）の構
造に関するものである。[Detailed Description of the Invention] (Industrial Application Field) This invention relates to semiconductor devices, particularly microwave band to quasi-millimeter wave band MMI G (=Honolit former CHicrow
ave InLeQratOdC1rcuit).
第４図は従来の半導体装置であるＭＭＩＧの実装状態を
示す斜視図である。同図において、１はパッケージ基板
であり、このパッケージ基板１の四部１ａのほぼ中央部
にＭＭＩＣ基板２が搭載されてパッケージ基板１の凹部
１ａの両側方Ｉｌｌの表面とＭＭＩＣ塁板２の表面とが
同じ高さにｔｏｉＩえられている。このＭＭ Ｉ Ｃ基
板２上の左側領域のほぼ中央部に入力端子３が設けられ
ており、この入力端′ｆ３からＭＭ Ｉ ＣＭＭ２Ｏ中
央部に設けられた回路部（図示省略）に入力信号線路４
が伸びており、この入力信号線路４により入力端子３と
回路部とが電気的に接続されている。ざらに、回路部か
らＭＭ Ｉ Ｃ基板２上の右側領域のほぼ中央部に設け
られた出力端子５に出力信号線路６が伸びており、この
出力信号線路６により出力端子５と回路部とが電気的に
接続されている。また、ＭＭＩＣ基板２上の四隅には接
地端子７ａ〜７ｄが設けられており、接地端子７ａ、７
ｂが接地線路８ａで、また、接地端子７ｃ、７ｄが接地
線路８ｂでそれぞれ電気的に接続されている。この接地
線路８ａ、 ８ｂが入力信号線路４および出力信号線路
６をはさみ、いわゆる−」プレーナラインを形成してい
る。一方、パッケージ基板１の四部１ａの左側方位置に
は入力端子３に対応して外部入力端子９が設けられてお
り、さらに、この外部入力端子９から入力信））線路４
の延長線上に外部入力信号線路１０が設けられている。FIG. 4 is a perspective view showing the mounting state of an MMIG, which is a conventional semiconductor device. In the figure, 1 is a package board, and an MMIC board 2 is mounted approximately in the center of four parts 1a of the package board 1, and the surface of both sides Ill of the recessed part 1a of the package board 1 and the surface of the MMIC base plate 2 are mounted. are placed at the same height. An input terminal 3 is provided approximately at the center of the left side area on the MMI C board 2, and an input signal line 4 is connected from this input terminal 'f3 to a circuit section (not shown) provided at the center of the MMI CMM2O.
extends, and the input terminal 3 and the circuit section are electrically connected by this input signal line 4. Roughly speaking, an output signal line 6 extends from the circuit section to an output terminal 5 provided approximately at the center of the right side area on the MM I C board 2, and this output signal line 6 connects the output terminal 5 and the circuit section. electrically connected. Further, ground terminals 7a to 7d are provided at the four corners of the MMIC board 2.
b is a ground line 8a, and ground terminals 7c and 7d are electrically connected to each other via a ground line 8b. These ground lines 8a and 8b sandwich the input signal line 4 and output signal line 6, forming a so-called -'' planar line. On the other hand, an external input terminal 9 is provided on the left side of the four parts 1a of the package board 1 in correspondence with the input terminal 3, and an input signal is input from the external input terminal 9))
An external input signal line 10 is provided on an extension of the line.
また、パッケージ基板１の凹部１ａの右側方位置には出
力端？５に対応して外部出力端子１１が設けられており
、さらに、この外部出力端Ｐ１１から出力信号線路６の
延長線上に外部出力信号線路１２が設けられている。そ
して、外部入力端子９と入力端子３とが金ワイヤ１３に
より電気的に接続され、また、外部出力端？’ｌｌと出
力ＩＰ５とが金ワイヤ１４により電気的に接続されてい
る。なお、パッケージ基板１の凹部１ａは全面メツ許さ
れ接地されているチップキャリア１５であり、このチッ
プキャリア１５と接地端子７ａ〜７ｄとがそれぞれ金ワ
イヤ１６ａ〜１６ｄにより電気的に接続されて接地線路
８ａ、８ｂを接地している。Also, there is an output end located on the right side of the recess 1a of the package substrate 1. An external output terminal 11 is provided corresponding to the external output terminal P11, and an external output signal line 12 is provided on an extension of the output signal line 6 from this external output terminal P11. The external input terminal 9 and the input terminal 3 are electrically connected by the gold wire 13, and the external output terminal? 'll and the output IP5 are electrically connected by a gold wire 14. Incidentally, the recess 1a of the package substrate 1 is a chip carrier 15 that is completely closed and grounded, and the chip carrier 15 and the ground terminals 7a to 7d are electrically connected by gold wires 16a to 16d, respectively, to form a ground line. 8a and 8b are grounded.
次に、上記のように構成された。半導体装置の動作につ
いて説明する。外部人力信″；３線路１０に与えられた
Ｒ Ｆ （” Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ）信号
は外部入力ＱｔＪ ｊ’ ９ 、金ワイＡア１３ 、入
力端子３および入力信号線路４を介して回路部に与えら
れる。一方、回路部よりの出力信号は出力信号線路６．
出力端子５．金ワイヤ１４．外部出力端子１１および外
部出力信号線路１２を介して素子外部に取り出される。It was then configured as described above. The operation of the semiconductor device will be explained. The RF (Radio Frequency) signal applied to the 3-line 10 is applied to the circuit section via the external input QtJ'9, the gold wire 13, the input terminal 3, and the input signal line 4. . On the other hand, the output signal from the circuit section is transmitted through the output signal line 6.
Output terminal 5. Gold wire14. The signal is taken out to the outside of the device via an external output terminal 11 and an external output signal line 12.
（発明が解決しようとする問題点〕
従来の半導体装置は以上のように構成されているので、
入力ｆａ了３と外部入力端″Ｆ９との闇を金ワイヤ１３
で、出ツノ端子５と外部出力端子１１との間を金ワイヤ
１４で、また、チップキャリア１５と接地端子７ａ〜７
ｄとの間をそれぞれ金ワイヤ１６ａ〜１６ｄで電気的に
接続するためにワイヤボンディング工程が必要となり、
アゼンプリを複雑なものにしていた。(Problems to be solved by the invention) Since the conventional semiconductor device is configured as described above,
Gold wire 13 connects the input terminal 3 and the external input terminal "F9"
A gold wire 14 is connected between the output terminal 5 and the external output terminal 11, and a gold wire 14 is connected between the chip carrier 15 and the ground terminals 7a to 7.
A wire bonding process is required to electrically connect the gold wires 16a to 16d with the gold wires 16a to 16d, respectively.
It made Azenpuri complicated.
また、一般的に信号の周波数が高い場合には金ワイヤ１
３，１４．１６ａ 〜１６ｄのインダクタンスも無視で
きなくなり、極力この値を小さくしなければならない。Generally, when the signal frequency is high, gold wire 1
3, 14. The inductance of 16a to 16d can no longer be ignored, and this value must be made as small as possible.
そのため、上記のごと（、パッケージ基板１の凹部１ａ
の両側方位置の表面とＭＭ Ｉ Ｃ１板２の表面とが同
じ高さになるように、すなわち入力端子３と外部入力端
子９とがまた出力端子５と外部出力端子１１とがそれぞ
れ同じ高さになるようにして金ワイヤ１．３．１４の長
さを極力短くしていた。したがって、上記の理由からパ
ッケージの形状に一定の制限が加えられ、パッケージ設
露１の自由度が低下するという問題があった。Therefore, as described above (the recess 1a of the package substrate 1
The surfaces on both sides of the MM I C1 board 2 are at the same height, that is, the input terminal 3 and the external input terminal 9 are at the same height, and the output terminal 5 and the external output terminal 11 are at the same height, respectively. The length of gold wire 1.3.14 was made as short as possible so that Therefore, for the above-mentioned reasons, there is a problem in that certain restrictions are placed on the shape of the package, and the degree of freedom in installing the package is reduced.
この発明は上記のような問題点を解消するためになされ
たもので、７センブリが同車で、寄生インダクタンスが
低く、しかもパッケージ設計の自由度が高い半導体装置
を提供することを目的とする。This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which seven assemblies can be assembled in the same vehicle, have low parasitic inductance, and have a high degree of freedom in package design.
この発明に係る半導体装ｔは、パッケージ基板上に設け
られた複数の外部端子と、前記パッケージ基板上に搭載
された半導体基板と、前記半導体填板上に前記′ｍ数の
外部端子と位置的に対応させて設番ノられた複数の端子
とを備え、位置的に対応する前記複数の端子と前記複数
の外部端子とが前記半導体基板を目通して設けられた複
数のバイアホールを利用してそれぞれ電気的に接続され
ている。The semiconductor device t according to the present invention includes a plurality of external terminals provided on a package substrate, a semiconductor substrate mounted on the package substrate, and the number of external terminals located on the semiconductor mounting plate. a plurality of terminals numbered in correspondence with the semiconductor substrate, and the plurality of terminals and the plurality of external terminals corresponding in position utilize a plurality of via holes provided through the semiconductor substrate. They are electrically connected to each other.
（作用）
この発明における半導体装置は、位置的に対応する複数
の端子と複数の外部端子とが、半導体基板を貫通してＱ
＜プられた複数のバイアホールを利用してそれぞれ電気
的に接続されているので、前記複数の端子と前記複数の
外部端子との間のそれぞれの寄生インダクタンスが低減
されるとともに、前記複数の端子と前記複数の外部端子
とを同一高さに揃えなければならないというパッケージ
設計上のｔ、ＩＪ約がなくなりパッケージ設計の自由度
が高くなる。また、上記のような構造においては、ワイ
ヤボンディングは不要であり、ワイヤボンディング工程
を省略でき、アセンブリがｍ単になる。(Function) In the semiconductor device according to the present invention, a plurality of positionally corresponding terminals and a plurality of external terminals penetrate through the semiconductor substrate and
<Since the plurality of via holes are used to electrically connect each other, the parasitic inductance between the plurality of terminals and the plurality of external terminals is reduced, and the The degree of freedom in package design is increased because the t and IJ constraints in package design, such as having to arrange the external terminals and the plurality of external terminals at the same height, are eliminated. Further, in the above structure, wire bonding is not necessary, the wire bonding process can be omitted, and the assembly becomes simple.
第１図はこの発明の一実施例である半導体装置の斜視図
、第２図は第１図の要部斜視図である。FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a perspective view of a main part of FIG.
両図において、１は平坦なパッケージ葛根である。In both figures, 1 is a flat package root.
このパッケージ基板１上の右側領域には、ＭＭＩＣ基板
２の出力端子５に対応する位Ｃに外部出力端子１１が設
けられるとともに、この外部出力端子１１から右側方向
に向けて外部出力線路１２が設けられる。また、ＭＭ
Ｉ Ｇ基板２の接地端？７ｂ、７ｄに対応して外部接地
端子１７ｂ、１７ｄが設けられており、さらに、これら
外部接地端子１７ｂ、１７ｄのそれぞれから外部出力線
路１２に対して平行に外部接地線路１８ｂ、１８ｄが設
けられている。一方、詳細な図示は省略されているが、
パッケージ基板１上の左側領域らその右側領域と左右対
称に構成されている。すなわち、ＭＭＩＣＪＩ板２の入
力端子３に対応するパッケージ基板１上に外部入力端子
（図示省略）が設けられるとと６に、この外部入カニａ
ｆから左側方に向けて外部入力線路１０が形成される。On the right side area of the package board 1, an external output terminal 11 is provided at a position C corresponding to the output terminal 5 of the MMIC board 2, and an external output line 12 is provided from this external output terminal 11 toward the right side. It will be done. Also, MM
Grounding end of IG board 2? External grounding terminals 17b and 17d are provided corresponding to external grounding terminals 7b and 7d, and external grounding lines 18b and 18d are provided parallel to the external output line 12 from these external grounding terminals 17b and 17d, respectively. There is. On the other hand, although detailed illustrations are omitted,
The left side area on the package substrate 1 is configured symmetrically with the right side area thereof. That is, if an external input terminal (not shown) is provided on the package substrate 1 corresponding to the input terminal 3 of the MMICJI board 2, this external input terminal a
An external input line 10 is formed toward the left side from f.
また、ＭＭＩＣＥｔ板２の接地端子７ａ、７ｃに対応し
て外部接地端子（図示省略）が設けられており、さらに
、これら外部接地端子のそれぞれから外部入力線路１０
に対して平行に外部接地線路１８８．１８Ｇが形成され
ている。Further, external grounding terminals (not shown) are provided corresponding to the grounding terminals 7a and 7c of the MMICEt board 2, and each of these external grounding terminals is connected to an external input line 10.
An external grounding line 188.18G is formed parallel to the external grounding line 188.18G.
ＭＭＩＣ基板２の右側領域には、出力信号線路６に連続
してバイアホール１９が設けられるとともに、接地線路
Ｂａ、Ｂｂに連続してバイアホール２０ｂ、２０ｄ／ｆ
ｉ設けられる。同様に、ＭＭＩＣ基板２の左側領域にも
、入力信号線路４に連続してバイアホール２１が設けら
れるとともに、接地線路８ａ、８ｂに連続してバイアホ
ール２０ａ。In the right side area of the MMIC board 2, a via hole 19 is provided continuous to the output signal line 6, and via holes 20b and 20d/f are provided continuous to the ground lines Ba and Bb.
i will be provided. Similarly, in the left side region of the MMIC board 2, a via hole 21 is provided continuous to the input signal line 4, and a via hole 20a is provided continuous to the ground lines 8a, 8b.
２０ｃが設けられる。そして、これら各バイアホール１
９．２０ａ 〜２０ｄ、２１には配線用の金属がそれぞ
れ充填され、それぞれの配線用金属の上面で出力端子５
．接地端子７ａ〜７ｄおよび入力端子３が形成される。20c is provided. And each of these via holes 1
9. 20a to 20d and 21 are each filled with wiring metal, and the output terminal 5 is connected to the upper surface of each wiring metal.
．． Ground terminals 7a to 7d and input terminal 3 are formed.
また、第３図に示すように、ＭＭＩ Ｃｌ器板の裏面側
には、バイアホール１９．２１を避けてバイアホール２
０ａ〜２Ｏｄ内の配線用金属とのみ電気的に接続される
接地電極２２が形成され、−方、パッケージ基板１上に
は、上記接地電極２２に対応して四隅の外部接地端子１
７ｂ、１７ｄ（左側の外部接地端子は図示省略）とのみ
電気的に接続される接地電極２３が形成される。そして
、各バイアホール１９，２０ａ 〜２０ｄ、２１を外部
出力端子１１．外部接地端子１７ｂ、１７ｄ（左側の外
部接地ｉＦは図示省略）および外部入力端子（図示省略
）にそれぞれ位置的に対応させた状態で、両接地電極２
２．２３が相互に重ね合わせてダイボンドにより接続さ
れる。こうして、外部出力信号線路１２．外部接地線路
１８ａ〜１８ｄおよび外部入力信号線路１０が、バイア
ホール１９．２０ａ 〜２０ｄ、２１を介して、出力端
子５．接地端子７ａ〜７ｄ、および入力端子３をそれぞ
れ電気的に接続される。In addition, as shown in Fig. 3, a via hole 2 is provided on the back side of the MMI Cl plate, avoiding via holes 19 and 21.
A ground electrode 22 is formed which is electrically connected only to the wiring metal within 0a to 2Od.
A ground electrode 23 is formed which is electrically connected only to 7b and 17d (the left external ground terminal is not shown). Then, each via hole 19, 20a to 20d, 21 is connected to an external output terminal 11. Both ground electrodes 2 are placed in positional correspondence with the external ground terminals 17b and 17d (external ground iF on the left side is not shown) and the external input terminal (not shown).
2.23 are stacked on top of each other and connected by die bonding. In this way, the external output signal line 12. External ground lines 18a to 18d and external input signal line 10 are connected to output terminals 5. The ground terminals 7a to 7d and the input terminal 3 are electrically connected to each other.
次に、上記のように構成された半尋体！Ａ四の動作につ
いて説明する。外部出力線路）線路１０に与えられたＲ
Ｆ信号は外部入力端子（図示省略）よりバイアホール２
１を通して入力端′：ｆ３に伝わり、さらに入力信号線
路４を介して回路部に与えられる。一方、回路部よりの
出力信号は出力信号線路６から出力端子５に伝わり、バ
イアホール１９を通り外部出力端子１１．外部出力信号
線路１２を経て素子外部に取り出される。また、接地線
路８ａには、外部接地線路１８ａ、外部接地端子（図示
省略）、バイアホール２０ａおよび接地端子７ａを介し
て電子が供給されるとと乙に、外部接地線路１８ｂ、外
部接地端子１７ｂ、バイアホール２０ｂ、外部接地端子
７ｂを介して電子が供給される。一方、接地線路８ｂに
は、外部接地線路１８Ｇ、外部接地端子（図示省略）、
バイアホール２０Ｃ１接地端子７Ｃを介して電子が供給
されるととらに、外部接地線路１８ｄ、外部接地端子１
７ｄ、バイアホール２０ｄ、接地端子７ｄを介して電子
が供給される。Next, the hanjin body constructed as above! The operation of A4 will be explained. R given to line 10 (external output line)
The F signal is connected to via hole 2 from the external input terminal (not shown).
1 to the input terminal ′:f3, and is further applied to the circuit section via the input signal line 4. On the other hand, the output signal from the circuit section is transmitted from the output signal line 6 to the output terminal 5, and passes through the via hole 19 to the external output terminal 11. The signal is taken out to the outside of the device via an external output signal line 12. Furthermore, electrons are supplied to the grounding line 8a via an external grounding line 18a, an external grounding terminal (not shown), a via hole 20a, and a grounding terminal 7a. , via hole 20b, and external ground terminal 7b. On the other hand, the ground line 8b includes an external ground line 18G, an external ground terminal (not shown),
While electrons are supplied through the via hole 20C1 and the ground terminal 7C, the external ground line 18d and the external ground terminal 1
7d, via hole 20d, and ground terminal 7d.
以上のように、バイアボール１９．２０ａ〜２０ｄ、２
１によりＭＭ Ｉ Ｃ基板２上の各端？５゜７ａ〜７ｄ
、３とパッケージ基板１上の各端子１１．１７ｂ、１７
ｄ（一部図示省略）とを電気的に接続しているので、金
ワイヤによるワイヤボンディング工程を省略できてアセ
ンブリが簡単となるとともに、金ワイヤに比べ寄生イン
ダクタンスも低減でき、さらに、パッケージ基板１の形
状に対する制約もなくなってパッケージ設計の自由度が
高くなる。As mentioned above, via balls 19.20a to 20d, 2
1 on each end of the MM I C board 2? 5°7a~7d
, 3 and each terminal 11.17b, 17 on the package board 1
d (partially not shown), the wire bonding process using gold wires can be omitted, simplifying assembly, and parasitic inductance can be reduced compared to gold wires. There are no restrictions on the shape of the package, increasing the degree of freedom in package design.
なお、上記実施例では入力、出力および接地部分にバイ
アホールを設【ノる場合について説明したが、これらの
部分以外の回ｆｆ１ｆｆｌ極部分、たとえばバイアス部
分についても上記と同様に、ＭＭＩＣ塁板２合板２１通
してバイアホールを設けるようにしてもよい。In the above embodiment, the case where via holes are provided in the input, output, and ground portions has been described, but the MMIC base plate 2 A via hole may be provided through the plywood 21.
以上のように、この発明の半導体装置によれば、位置的
に対応する゛ト導体基板上の複数の端子とパッケージ基
板上の複数の外部端子とを、半々体塁板を量適して設け
られた複数のバイアホールによりそれぞれ電気的に接続
しているの゛で、ワイヤボンディングｒ程が省略でき、
アセンブリが簡単になるとともに、前記複数の端゛Ｔと
前記複数の外部端子との間のそれぞれの寄生インダクタ
ンスが低減され、しかもパッケージｗｉ８１上の制約が
なくなリパッケージ設計の自由度が高くなるという効果
がある。As described above, according to the semiconductor device of the present invention, a plurality of positionally corresponding terminals on the conductive substrate and a plurality of external terminals on the package substrate can be provided in an appropriate amount on a half-body base plate. Since they are electrically connected through multiple via holes, wire bonding can be omitted.
In addition to simplifying assembly, each parasitic inductance between the plurality of terminals T and the plurality of external terminals is reduced, and there are no restrictions on the package wi81, increasing the degree of freedom in repackaging design. effective.
【図面の簡単な説明】
第１図はこの発明の一実施例である半導体装置の斜視図
、第２図は第１図のｖ１部斜視図、第３図はダイボンド
方法を説明するための図、第４図は従来の半導体装置の
斜視図である。
図において、１はパッケージ基板、２はＭＭＩＣｍ板、
３は入力端子、５は出力端７’、７ａ〜７ｄは接地端子
、９は外部入力端子、１１は外部出力端子、１７ｂ、１
７ｄは外部接地端？−，１９゜２０ａ〜２０６．２１は
バイアボールである。
なお、各図中同一符号は同一・または相当部分を示す。
代理人 大 岩 増 雄
第１図
１９２０ａ〜２０ｄ２１：にイアホール第４図[Brief Description of the Drawings] Fig. 1 is a perspective view of a semiconductor device which is an embodiment of the present invention, Fig. 2 is a perspective view of the v1 section of Fig. 1, and Fig. 3 is a diagram for explaining the die bonding method. , FIG. 4 is a perspective view of a conventional semiconductor device. In the figure, 1 is a package board, 2 is an MMICm board,
3 is an input terminal, 5 is an output terminal 7', 7a to 7d are ground terminals, 9 is an external input terminal, 11 is an external output terminal, 17b, 1
Is 7d the external ground terminal? -, 19°20a to 206.21 are via balls. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 1920a-20d21: Earhole Figure 4
Claims (1)
、前記パッケージ基板上に搭載された半導体基板と、前
記半導体基板上に前記複数の外部端子と位置的に対応さ
せて設けられた複数の端子とを備えた半導体装置におい
て、 位置的に対応する前記複数の端子と前記複数の外部端子
とが前記半導体基板を貫通して設けられた複数のバイア
ホールを利用してそれぞれ電気的に接続されていること
を特徴とする半導体装置。(1) A plurality of external terminals provided on a package substrate, a semiconductor substrate mounted on the package substrate, and a plurality of external terminals provided on the semiconductor substrate in positional correspondence with the plurality of external terminals. In the semiconductor device, the plurality of positionally corresponding terminals and the plurality of external terminals are electrically connected to each other using a plurality of via holes provided through the semiconductor substrate. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62267162A JPH01108745A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62267162A JPH01108745A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01108745A true JPH01108745A (en) | 1989-04-26 |
Family
ID=17440956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62267162A Pending JPH01108745A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01108745A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
-
1987
- 1987-10-21 JP JP62267162A patent/JPH01108745A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
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