JPH01108725A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the breakdown strength between wirings from deteriorating as well as the second wiring from being disconnected at gap parts by a method wherein the gaps in an interlayer film formed by etch back process are filled up with spin-on-glass. CONSTITUTION:An SiO2 film 9 is formed on a silicon substrate 8, the first wirings 10 are formed on the SiO2 film 9, an interlayer insulating film 11 is formed between and on the wirings 10, the interlayer insulating film 11 is flatly coated with resist 12 in thickness of around 1.2-1.5mum, finally the resist 12 and the interlayer insulating film 11 are etched back. Next, the interlayer insulating film 11 is flatly coated with spin-on-glass 14 filling up the gaps 13 made by the etch back process and later the spin-on-glass 14 is turned into another SiO2 film by heat-treatment and then etched away until the interlayer insulating film 11 is exposed. Finally, the insulating film 11 is flattened leaving the spin-on- glass 14 only in the gap parts 13 to form the second wiring 15.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit device that can embed and planarize an interlayer insulating film without forming slits between conductive wires. be.

BACKGROUND OF THE INVENTION As semiconductor devices become smaller and more highly integrated, it becomes difficult to embed a glabellar insulating film between wiring lines and achieve flattening. For example, when a plasma oxide film is deposited as an insulating film between the eyebrows, when the distance between wires becomes short, cavities are created between the wires because there is a limit to the step coverage of the plasma oxide film.

This cavity lowers the withstand voltage between wiring lines and may cause leakage, which poses a reliability problem. Further, if a cavity exists, unevenness will occur on the glabella insulating film when the interlayer insulating film is later planarized by the etch-back method (4), causing disconnection of the second layer wiring.

Conventionally, in order to solve such problems, there is a technique of embedding an insulating film with good step coverage between wirings and then planarizing the insulating film by an etch-back method. Using this technique, it is possible to embed an insulating film without creating cavities between interconnects. Therefore, the manufacturing method is shown in FIGS. 2(M) to 2(C).

First, a 5i02 film is formed on a silicon substrate, then wiring is formed, and an interlayer insulating film is formed between and on the wiring (FIG. 2(A)).

Next, a resist is applied evenly onto the interlayer insulating film.

(Figure 2)).

Next, the resist 5 and interlayer insulating film 4 are etched at the same time,
Planarization is performed (Fig. 2 (C1)).

The problem that the invention seeks to solve Problems with the above manufacturing method will be described below with reference to FIG.

When the interlayer insulating film 4 is planarized using the etch pack method in the above manufacturing method, there are parts of the interlayer insulating film 4 that are easily etched, so if some overetching occurs, the result will be as shown in FIG. 2(C). A gap 6 may occur between the two. If a second layer of wiring is formed on top of this, no wiring will be formed in the gap, resulting in a disconnection state.

Means for Solving the Problems The technical means of the present invention for solving the above problems is the following method. First, a 5 inch
2 films are formed, and a first wiring is formed on the insulating film. Thereafter, an interlayer insulating film having good step coverage is buried between and on the first wiring, and a resist is evenly applied onto the interlayer insulating film.

Next, the resist and the interlayer insulating film are etched to a predetermined thickness using an etch pack method. Next, in order to fill the gap in the interlayer insulating film caused by the etch pack, spin-on glass is coated thinly and flatly on the interlayer insulating film so that no unevenness occurs in the gap, and then heat treatment is performed and the spin-on glass is・Make the on-glass SiO□. Next, the spin-on glass is removed by etching until the interlayer insulating film is exposed, and the insulating film is planarized, leaving the spin-on glass only in the gap. Next, a second wiring is formed on the interlayer insulating film and the spin-on glass.

action The effect of this technical means is as follows.

Since the gap between the next interlayer insulating film caused by the etch pack is filled with spin-on glass, the interlayer insulating film can be flattened. Therefore, the second layer wiring will not be disconnected at the gap.

Further, since no cavities are formed between the wirings, the dielectric strength voltage between the wirings does not become low.

Embodiment An embodiment of the present invention will be described with reference to FIGS.

First, a SiO2 film 9 is formed on a silicon substrate 8, and a SiO2 film 9 is formed on a silicon substrate 8.
A first wiring 10 is formed on the O2 film e. after that.

An interlayer insulating film 11 is formed between the first wirings 10 and on the wirings. At this time, the interlayer insulating film 11 is formed using a photo-CVN method or the like which provides good step coverage (FIG. 1(A)).

Next, a resist layer with a thickness of 1.2 to 1.6 μm is applied on the interlayer insulating film 11.
Apply it evenly (Fig. 1 @)).

Next, the resist 12 and the interlayer insulating film 1 are formed using an etch pack method.
1 is etched under conditions such that the etch rate of both is 1:1. At this time, the thickness of the interlayer insulating film 11 on the first wiring 10 is set to be approximately 600 to 800 nm. In addition, at this time, since there is a poor film quality part with a high etching rate in the interlayer insulating film 11, the glabellar insulating film 1
A gap 13 is generated on the surface of the wafer 1 (FIG. 1(C)).

Next, the spin-on glass 14 is applied flatly on the interlayer insulating film 11, and the gap 13 is filled with the spin-on glass 14. At this time, the spin-on on the interlayer insulating film 11
The thickness of the glass 14 is preferably 150 nm or less in order to prevent cracks from being generated later during heat treatment. Thereafter, heat treatment is performed to turn the spin-on glass 14 into an Sio2 film (as shown in FIG. 1).

Next, the spin-on glass 14 is removed by etching until the interlayer insulating film 11 is exposed.
is left only in the gap 13, and the insulating film is planarized (first
Zuko)).

Next, a second wiring 15 is formed on the interlayer insulating film 11 and the spin-on glass 14 (FIG. 1 (F'l)).

As mentioned above, the gap 13 is filled with spin-on glass 1
4 and flatten it, the second layer wiring 1
6 will not be disconnected at the gap 13. Further, since no cavities are formed between the wirings, the dielectric strength voltage between the wirings does not become low.

In the above embodiment, as a method for forming the interlayer insulating film 11, it is preferable to use a photo-CVD method that uses SiH2 and N20 as reaction gases and has good step coverage. At this time, if an insulating film with poor step coverage is formed, the gap 21 will become larger as shown in Figure 3, causing cracks 22 in the embedded spin-on glass and creating cavities between the wiring. , the flatness deteriorates. Also, spin
There is also a risk that the on-glass may come off from the cracked area. However, if a photo-CVD method with good step coverage is used, large gaps will not be created between wiring lines, and flatness will not deteriorate.

Effects of the Invention As described above, according to the present invention, spin-on glass is buried in the gap on the surface of the interlayer insulating film caused by the etch-back method to flatten the surface, so that the second layer wiring can be formed in the gap. There will be no disconnection.

Further, since no cavities are formed between the wirings, the dielectric strength voltage between the wirings does not become low.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. 8...Silicon substrate, 9...SiO2
Film, 1o...First wiring, 11...Interlayer insulating film, 12...Resist, 13...
・Gap, 14-...Spin-on glass, 16
...Second wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person
Silicon Feng 11 --- 4-kaku special l trap f2 --- Left No. 1111 14 --- λ pico no force 1 inserted Figure 2 7-: Ji 113m body

Claims (1)

[Claims] a first step of forming a first wiring on the semiconductor substrate;
a second step of forming an insulating film on the semiconductor substrate and the first wiring, and forming a flat resist film on the insulating film; a third step of etching the resist film and the insulating film; , a fourth step of forming spin-on glass on the insulating film and performing heat treatment; and etching the spin-on glass to remove the insulating film and the spin-on glass.
A method for manufacturing a semiconductor integrated circuit device, comprising a fifth step of forming a second wiring on on-glass.