JPH01107654A - Fet rectification - Google Patents

Fet rectification

Info

Publication number
JPH01107654A
JPH01107654A JP26181487A JP26181487A JPH01107654A JP H01107654 A JPH01107654 A JP H01107654A JP 26181487 A JP26181487 A JP 26181487A JP 26181487 A JP26181487 A JP 26181487A JP H01107654 A JPH01107654 A JP H01107654A
Authority
JP
Japan
Prior art keywords
transformer
output
circuit
switch
switch element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26181487A
Other languages
Japanese (ja)
Inventor
Toshiyuki Zaitsu
俊行 財津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26181487A priority Critical patent/JPH01107654A/en
Publication of JPH01107654A publication Critical patent/JPH01107654A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance efficiency, by driving a rectifying FET via a pulse transformer with the output of a controlling circuit. CONSTITUTION:A FET rectifying system is composed of a DC power source 1, a transformer 2, a switch element 3 switched in a specified period and a specified conduction width variable switches 4-5 series-connected to the secondary side of the transformer 2 and suppressing partial output fed to the load side in the conduction period of the primary side switch 3, and a controlling circuit 6 for driving the gate of the switch element 3. The controlling circuit 6 is composed to drive the variable switches 4-5 via a pulse transformer 7, and the clock of the circuit 6 is synchronized with clock signal 8. Then, by the controlling circuit 6, output voltage and previously set reference voltage are compared with each other, and by regulating the clock signal, the output voltage Vo is regulated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスイッチングレギュレータの整流方式に係シ、
特にFET整流方式に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a rectification method of a switching regulator.
In particular, it relates to the FET rectification system.

〔従来の技術〕[Conventional technology]

従来、スイッチングレギュレータの整流方式はダイオー
ド整流方式である。
Conventionally, the rectification method of a switching regulator is a diode rectification method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のダイオード整流方式では、出力電流が小
さい場合もダイオードの順方向降下電圧に依存するロス
が生じるという問題点があった。
The conventional diode rectification method described above has a problem in that even when the output current is small, a loss occurs depending on the forward voltage drop of the diode.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のFET整流方式は、所定周期でかつ所定導通幅
で開閉されるスイッチ素子を介して変成器の一次側に矩
形波を誘起する電力供給回路と、上記変成器の二次側に
直列に接続され一次側スイッチ素子の導通期間に負荷側
に供給される出力の一部を阻止する可変スイッチと、こ
の可変スイッチをパルストランスを介して駆動する制御
回路と、上記可変スイッチの出力を整流・平滑する整流
平滑回路を含むものである。
The FET rectification method of the present invention includes a power supply circuit that induces a rectangular wave on the primary side of the transformer via a switching element that is opened and closed at a predetermined period and with a predetermined conduction width, and a power supply circuit that is connected in series to the secondary side of the transformer. A variable switch that blocks part of the output supplied to the load side during the conduction period of the connected primary side switching element, a control circuit that drives this variable switch via a pulse transformer, and a control circuit that rectifies and rectifies the output of the variable switch. It includes a rectifying and smoothing circuit for smoothing.

〔作用〕[Effect]

本発明においては、整流用のFITを、制御回路の出力
をパルストランスを介して駆動する。
In the present invention, the rectifying FIT is driven by the output of the control circuit via a pulse transformer.

〔実施例〕〔Example〕

以下、図面に基づき本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

第1図は本発明の一実施例を示す構成図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

図において、1は直流電源、2は変成器、3は所定周期
でかつ所定導通幅で開閉されるスイッチ素子で、これら
は所定周期でかつ所定導通幅で開閉するスイッチ素子3
を介して変成器2の一次側に矩形波を誘起する電力供給
回路を構成している。
In the figure, 1 is a DC power supply, 2 is a transformer, and 3 is a switch element that opens and closes at a predetermined period and with a predetermined conduction width;
This constitutes a power supply circuit that induces a rectangular wave on the primary side of the transformer 2 via the transformer 2.

4.5はスイッチ素子で、このスイッチ素子4゜5は変
成器2の二次側に直列に接続され一次側スイッチ素子3
の導通期間に負荷側に供給される出力の一部を阻止する
可変スイッチを構成している。
4.5 is a switch element, and this switch element 4.5 is connected in series to the secondary side of the transformer 2 and is connected to the primary side switch element 3.
A variable switch is configured to block part of the output supplied to the load side during the conduction period of the switch.

6は出力電圧と予め設定した基準電圧とを比較しクロッ
ク信号8を発生してスイッチ素子3のゲートを駆動する
制御回路で、この制御回路6は上記可変スイッチをパル
ストランスTを介して駆動するように構成されている。
A control circuit 6 compares the output voltage with a preset reference voltage and generates a clock signal 8 to drive the gate of the switch element 3. This control circuit 6 drives the variable switch via the pulse transformer T. It is configured as follows.

そして、この制御回路6のクロックはクロック信号8と
同期している。
The clock of this control circuit 6 is synchronized with the clock signal 8.

9はフライホイールダイオード、10はチョークコイル
、11はコンデンサで、とれらは上記可変スイッチの出
力を整流・平滑する整流平滑回路を構成している。12
m 、 12bは出力が得られる出力端子である。
9 is a flywheel diode, 10 is a choke coil, and 11 is a capacitor, which constitute a rectifying and smoothing circuit that rectifies and smoothes the output of the variable switch. 12
m, 12b is an output terminal from which an output is obtained.

第2図は第1図の動作説明に供する各部の波形図で、(
a)は変成器2の二次側の両端電圧VSの波形を示した
もので、あ!り、(b)はパルストランス1の二次側電
圧、すなわち、スイッチ素子4.5のゲート電圧vse
の波形、(C)は整流後の電圧vLの波形を示したもの
である。なお、vOは出力電圧を示し、Gは接地電位□
、ヒ)はスイッチ素子4,50オン期間、(ロ)はスイ
ッチ素子4.5のオフ期間を示す。
Figure 2 is a waveform diagram of each part used to explain the operation of Figure 1.
A) shows the waveform of the voltage VS across the secondary side of transformer 2. Ah! (b) is the secondary side voltage of the pulse transformer 1, that is, the gate voltage vse of the switching element 4.5.
(C) shows the waveform of the voltage vL after rectification. Note that vO indicates the output voltage, and G is the ground potential □
, h) shows the on period of the switch elements 4 and 50, and (b) shows the off period of the switch element 4.5.

つぎに第1図に示す実施例の動作を第2図を参照して説
明する。
Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

まず、所定周期でかつ所定導通幅でスイッチ素子3を開
閉して変成器2の二次側に第2図(a)に示すような矩
形波を誘起させ、スイッチ素子3の等適時間に制御回路
6からのクロック信号でパルストランス7を介しスイッ
チ素子4,5を導通させる(第2図(b)参照)。つぎ
に、制御回路6が出力電圧と予め設定した基準電圧を比
較してクロック信号を調整することによシ出力電圧vo
t−調整する(第2図(c)参照)。
First, the switching element 3 is opened and closed at a predetermined period and with a predetermined conduction width to induce a rectangular wave as shown in FIG. The switching elements 4 and 5 are made conductive by the clock signal from the circuit 6 via the pulse transformer 7 (see FIG. 2(b)). Next, the control circuit 6 compares the output voltage with a preset reference voltage and adjusts the clock signal.
t-adjust (see Figure 2(c)).

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、整流用のFETを、制
御回路の出力をパルストランスを介して駆動することに
よシ、簡単にFET整流回路を構成でき、従来のダイオ
ード整流方式に比べ高効率な整流回路を美肌することが
でき石効来がある。
As explained above, the present invention allows a FET rectifier circuit to be easily configured by driving a rectifying FET with the output of a control circuit via a pulse transformer, and has a high performance compared to the conventional diode rectification method. The efficient rectifier circuit can beautify the skin and has stone effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第4図は本発明の一実施例を示す構成図、第2図は第1
図の動作説明に供する各部の波形図である。 1・・・・直流電源、2拳・・・変成器、3〜5・・・
・スイッチ素子、6・・・・制御回路、7・・・・パル
ストランス、9・・−・フライホイールダイオード、1
0・・・・チョークコイル、11・@―・コンデンサ。
FIG. 4 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 4 is a waveform diagram of each part for explaining the operation of the figure. 1...DC power supply, 2 fists...transformer, 3-5...
・Switch element, 6...Control circuit, 7...Pulse transformer, 9...Flywheel diode, 1
0...Choke coil, 11.@--Capacitor.

Claims (1)

【特許請求の範囲】[Claims] 所定周期でかつ所定導通幅で開閉されるスイッチ素子を
介して変成器の一次側に矩形波を誘起する電力供給回路
と、前記変成器の二次側に直列に接続され一次側スイッ
チ素子の導通期間に負荷側に供給される出力の一部を阻
止する可変スイッチと、この可変スイッチをパルストラ
ンスを介して駆動する制御回路と、前記可変スイッチの
出力を整流・平滑する整流平滑回路を含むことを特徴と
するFET整流方式。
A power supply circuit that induces a rectangular wave on the primary side of the transformer through a switch element that is opened and closed at a predetermined period and with a predetermined conduction width, and a power supply circuit that is connected in series to the secondary side of the transformer and conducts the primary side switch element. A variable switch that blocks part of the output supplied to the load during a period, a control circuit that drives this variable switch via a pulse transformer, and a rectifying and smoothing circuit that rectifies and smoothes the output of the variable switch. FET rectification system featuring
JP26181487A 1987-10-19 1987-10-19 Fet rectification Pending JPH01107654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26181487A JPH01107654A (en) 1987-10-19 1987-10-19 Fet rectification

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26181487A JPH01107654A (en) 1987-10-19 1987-10-19 Fet rectification

Publications (1)

Publication Number Publication Date
JPH01107654A true JPH01107654A (en) 1989-04-25

Family

ID=17367088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26181487A Pending JPH01107654A (en) 1987-10-19 1987-10-19 Fet rectification

Country Status (1)

Country Link
JP (1) JPH01107654A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008230516A (en) * 2007-03-22 2008-10-02 Toyota Central R&D Labs Inc Shock absorbing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008230516A (en) * 2007-03-22 2008-10-02 Toyota Central R&D Labs Inc Shock absorbing device

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