JPH01107569A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01107569A JPH01107569A JP26383887A JP26383887A JPH01107569A JP H01107569 A JPH01107569 A JP H01107569A JP 26383887 A JP26383887 A JP 26383887A JP 26383887 A JP26383887 A JP 26383887A JP H01107569 A JPH01107569 A JP H01107569A
- Authority
- JP
- Japan
- Prior art keywords
- transition metal
- silicide layer
- metal silicide
- semiconductor device
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 229910021350 transition metal silicide Inorganic materials 0.000 claims abstract description 21
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 17
- 150000003624 transition metals Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000203 mixture Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 6
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 claims 1
- 229910005883 NiSi Inorganic materials 0.000 claims 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 22
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- 229910001325 element alloy Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 14
- 239000010408 film Substances 0.000 description 12
- 238000001556 precipitation Methods 0.000 description 8
- 238000001228 spectrum Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 238000000026 X-ray photoelectron spectrum Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002175 menstrual effect Effects 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、および、超ＬＳＩの製造に好適な
Ａｌ配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming Al interconnects suitable for manufacturing semiconductor devices and VLSIs.
従来、ＬＳＩ用配線にはＡΩ−Ｓｉ合金が泪いられてき
た。しかし、基板からのＳｉ吸い上げ防止の目的で加ら
れている配線中のＳｉが逆に後から加えられるアニール
の結果、基板上に析出することが問題となっていた。特
に、素子の微細化に伴い、配線と素子との接合面積が少
なくなると、少量のＳｉ析出でも容易に接合部全面をお
おってしまいコンタクト抵抗を増大させ問題となってい
た。このＳｉ析出の防止のために、月経マイクロデバイ
ス、１９８６年１２月号ＰＰ８５〜ＰＰＩ ００ ニ記
載のように、配線の下にＴ’ｉＮ、シリサイド。Conventionally, AΩ-Si alloys have been used for LSI wiring. However, there has been a problem in that Si in the wiring, which is added to prevent Si from being sucked up from the substrate, is deposited on the substrate as a result of annealing that is added later. Particularly, as devices become finer and the bonding area between wiring and devices decreases, even a small amount of Si precipitates easily covers the entire surface of the bonding area, causing a problem of increased contact resistance. In order to prevent this Si precipitation, T'iN and silicide are added under the wiring as described in Menstrual Micro Device, December 1986 issue PP85-PPI00.
ＴｉＷ等のバリヤ層を、スパッタ法等の薄膜形成プロセ
スを用いて形成する方法が考案されてきた。A method of forming a barrier layer such as TiW using a thin film forming process such as a sputtering method has been devised.
このバリヤ層の存在によりＡＩ２合金とＳｉ基板が接触
しないようにし、Ｓｉ析出を防止している。The presence of this barrier layer prevents the AI2 alloy from coming into contact with the Si substrate, thereby preventing Si precipitation.
このバリヤ層の構造は、Ａｆ１合金配線と同時にパター
ニングを行うために配線の下には、つねにバリヤ層が存
在するものと、素子との接合部にのみバリヤ層を持つも
のの二種類が考えられている。Two types of barrier layer structures are considered: one in which the barrier layer is always present under the wiring in order to perform patterning at the same time as the Af1 alloy wiring, and one in which the barrier layer is present only at the junction with the element. There is.
また、本発明と技術的に近い発明に、特開昭５７−１６
２４２４号公報に記載の半導体装置の製造方法が開示さ
れている。ただし、上記発明は接合部にポリシリコンを
形成する技術である点、熱処理が二段階である点で本発
明と異なる。In addition, an invention technically similar to the present invention is disclosed in Japanese Patent Application Laid-Open No. 57-16
A method for manufacturing a semiconductor device is disclosed in Japanese Patent No. 2424. However, the above-mentioned invention differs from the present invention in that it is a technique for forming polysilicon in the joint portion and that heat treatment is performed in two stages.
上記従来技術によると、配線はＡｆｉ合金／バリヤ層の
二層構造、あるいは、接合部のみＡｌ合金／バリヤ層の
二層構造になる。このうち前者では、Ａｌ合金とバリヤ
層を連続してエツチングすることになる。この場合、微
細加工に適した、ドライエツチング法を用いる場合には
、Ａｌ合金とバリヤ層とでエツチングガスを変える必要
があり、装置面での工夫と工程増がさけられない。また
、両者のエツチングレートが異なりバリヤ層がアンダー
カットされる場合が生じる。この場合には、バリヤ層の
アンダーカット部の汚染をおとすことが困難でこの部分
から配線の腐食を発生させやｔいという問題があった。According to the above-mentioned conventional technology, the wiring has a two-layer structure of AFi alloy/barrier layer, or a two-layer structure of Al alloy/barrier layer only at the joint portion. In the former case, the Al alloy and the barrier layer are etched successively. In this case, if a dry etching method suitable for microfabrication is used, it is necessary to change the etching gas for the Al alloy and the barrier layer, which necessitates devising equipment and increasing the number of steps. Further, the etching rates of the two may be different and the barrier layer may be undercut. In this case, there is a problem in that it is difficult to remove contamination from the undercut portion of the barrier layer, and corrosion of the wiring is likely to occur from this portion.
また、後者の接合部のみＡｌ合金／バリヤ層の構造とし
た場合には、バリヤ層とＡｌ合金の両者に対し、それぞ
れ、ホトエツチングプロセスが必要となり、工程数が大
福に増加するという問題があった。Furthermore, if only the latter joint has an Al alloy/barrier layer structure, a photo-etching process is required for both the barrier layer and the Al alloy, resulting in a significant increase in the number of steps. Ta.
一方、接合部のみのバリヤ層形成を自己整合的に行う方
法も知られている。すなわち、遷移金属を半導体素子全
面に蒸着あるいはスパッタにより膜形成し、その後で熱
処理し、遷移金属と接合部のシリコンを反応させ、シリ
サイド層を形成し、バリヤ層とし、未反応の遷移金属を
エツチングし除去する方法である６しかし、この方法は
、化学反応を用いるため、バリヤ層の膜厚制御が困難で
、容易に１０００人程度０厚さと°なる。しかし、一般
にシリサイドの比抵抗は金属に比べて大きいので、高集
積化により配線が微細化し、配線抵抗が問題となり、こ
の膜厚は、さらに、薄くすることが望まれる。シ方、半
導体素子にとっても、シリサイド層形成のために素子中
のシリコンが供給されるが、それは素子の微細化に伴っ
て浅くなっているシリコン拡散層のシリコンを消費する
ことであり、素子の信頼性が低下するため問題があった
。On the other hand, a method is also known in which the barrier layer is formed only at the joint portion in a self-aligned manner. That is, a transition metal film is formed by vapor deposition or sputtering over the entire surface of a semiconductor element, and then heat treatment is performed to react the transition metal with silicon at the junction to form a silicide layer, which serves as a barrier layer, and the unreacted transition metal is etched. However, since this method uses a chemical reaction, it is difficult to control the thickness of the barrier layer, and the thickness can easily drop to about 1,000. However, in general, the specific resistance of silicide is larger than that of metal, and as interconnections become finer due to higher integration, interconnect resistance becomes a problem, and it is desirable to further reduce the film thickness. On the other hand, for semiconductor devices, silicon in the device is supplied to form a silicide layer, but this consumes silicon in the silicon diffusion layer, which is becoming shallower as the device becomes smaller. There was a problem because reliability decreased.
本発明の目的は、半導体素子とＡｌ合金配線の接合部に
選択的に１００Å以下の厚さで均一に遷移金属シリサイ
ドバリヤ層を形成する技術を提供し、それにより、高集
積化に好適で高信頼性の接合構造を持った半導体装置を
提供することにある。 ′〔問題点を解決するた
めの手段〕
上記目的は、Ａｌ合金配線としてｐｄ、ＭｇｔＰｔ、Ｎ
ｉのうちの一遷移金属とシリコンを遷移金属シリサイド
の組成比よりシリコン過剰となるような組成で含むＡｌ
合金を用い、半導体素子上にＡｆｉ合金配線を形成後、
歯子界面に遷移金属を集中させる工程、集中した遷移金
属をシリサイド化する工程を経て、遷移金属シリサイド
層を半導体素子とＡｌ合金配線の間に形成し、その後、
オーミックコンタクト形成のための熱処理を行うことに
より達成される。An object of the present invention is to provide a technique for selectively and uniformly forming a transition metal silicide barrier layer with a thickness of 100 Å or less at the junction between a semiconductor element and an Al alloy wiring, thereby making it suitable for high integration and high performance. An object of the present invention is to provide a semiconductor device having a reliable junction structure. [Means for solving the problem] The above purpose is to use pd, MgtPt, N
Al containing one of the transition metals of i and silicon in a composition such that silicon is in excess of the composition ratio of the transition metal silicide
After forming Afi alloy wiring on the semiconductor element using the alloy,
A transition metal silicide layer is formed between the semiconductor element and the Al alloy wiring through a process of concentrating the transition metal at the tooth interface and a process of siliciding the concentrated transition metal, and then,
This is achieved by performing heat treatment to form ohmic contact.
Ａｌ合金配線／Ｓｉ基基板台部上へのＳｉの析出はＳｉ
基板上にあるイオン打込みの際１発生した損傷部や、接
合部形成の際のドライエツチングによる損傷、周囲の絶
縁膜との間に生じる応力による欠陥を核として基板上に
Ａ０合金中に含まれていたＳｉがエピタキシャル成長し
て発生する。The precipitation of Si on the Al alloy wiring/Si base substrate pedestal is
The damage contained in the A0 alloy on the substrate is caused by damage caused during ion implantation on the substrate, damage caused by dry etching during the formation of bonding parts, and defects caused by stress generated between the surrounding insulating film. This is generated by epitaxial growth of Si that had previously been deposited.
このＳｉのエピタキシャル成長は４００℃前後から顕著
となる。それに対し、たとえば、 ＰｄｚＳｉ形成反応
は１３０℃ですでに進行する。そこで、Ｓｉ析出は生じ
ないがＰｄｚＳｉ 等のシリサイドは形成する温度での
アニールをＡｆｉ合金膜の形成後に行えば、Ｓｉ基板表
面に選択的にＰｄｚＳｉ層を形成することができる。Ｐ
ｄｚＳｉ 層が形成される際にＳｉ析出の発生点となる
Ｓｉ基板表面の損傷や欠陥はおおい隠されてしまい、ま
た、ＰｄｚＳｉ とＳｉでは結晶構造が異なることか
らＳｉのエピタキシャル成長も抑えることができる。This epitaxial growth of Si becomes noticeable at around 400°C. In contrast, for example, the PdzSi formation reaction proceeds already at 130°C. Therefore, by performing annealing at a temperature that does not cause Si precipitation but forms silicide such as PdzSi after forming the Afi alloy film, a PdzSi layer can be selectively formed on the surface of the Si substrate. P
When the dzSi 2 layer is formed, damage and defects on the Si substrate surface, which are the points where Si precipitation occurs, are largely hidden, and since PdzSi 2 and Si have different crystal structures, epitaxial growth of Si can also be suppressed.
このように−度ＰｄｚＳｉ のような遷移金属シリサ
イド層が形成されるとＳｉ析出は発生しにくくなるため
、その後でバリヤ層がない場合にはＳｉ析出が問題とな
っていたオーミックコンタクト形成のためのアニール工
程を経てもＳｉ析出は生じない。In this way, when a transition metal silicide layer such as PdzSi is formed, Si precipitation is less likely to occur, so it is difficult to form an ohmic contact, where Si precipitation would have been a problem if there was no barrier layer. Even after the annealing process, Si precipitation does not occur.
また、この方法ではＡｌ合金配線中の遷移金属およびシ
リコンの量を変えることにより、容易に遷移金属シリサ
イドバリヤの厚さを変えることができ、また、シリサイ
ド形成反応はＡｌ合金とＳｉの界面で十分低い温度で進
行させるため均一に進行する。そのため、１００Å以下
のしかも切れ目のない遷移金属シリサイドバリヤ層を形
成することができる。In addition, with this method, the thickness of the transition metal silicide barrier can be easily changed by changing the amounts of transition metal and silicon in the Al alloy wiring, and the silicide formation reaction is sufficient at the interface between the Al alloy and Si. It progresses uniformly because it progresses at a low temperature. Therefore, a continuous transition metal silicide barrier layer having a thickness of 100 Å or less can be formed.
以下、本発明の一実施例を第１図により説明する。第１
図は１本発明の結果形成される半導体装置の構造であり
、Ａｌ合金配線１と、シリコン拡散層４の間に厚さ１０
０Å以下のＰｄｚＳｉ 層５が形成されている。第２
図は本発明の実施手段を示した図である。はじめに半導
体素子上にＡｌ−０，３ｗｔ％Ｐｄ−１ｖｔ％Ｓｉの組
成の膜をスパッタ法で形成し、ホトエツチング工程を経
て配線パターンを形成する６次に１５０℃のアニールを
行う、この工程によりＡ１合金中のＰｄは半導体素子と
の界面に集中する。この様子をＳＩＭＳスペクトルでｗ
Ａ測したのが第３・画である。ＩＦ移金金属してＰｄを
用いた場合には形成されるシリサイドはＰｄｚＳｉ
だが、第４図、に示すシリコン界面のＸＰＳスペクトル
ではＰ ｄ ３ｄ５．／２ピークはほぼＰｄ金属の位置
にある。すなわち、最初のアニールではＰｄｚＳｉ
は形成されず接合界面に集中しているのはＰｄ金属に少
量のＳｉを含む状態にとどまっている。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows the structure of a semiconductor device formed as a result of the present invention, with a thickness of 10 mm between an Al alloy wiring 1 and a silicon diffusion layer 4.
A PdzSi layer 5 with a thickness of 0 Å or less is formed. Second
The figure is a diagram showing means for implementing the present invention. First, a film with a composition of Al-0, 3wt%Pd-1vt%Si is formed on the semiconductor element by sputtering, and a wiring pattern is formed through a photoetching process.6 Next, annealing is performed at 150°C. Pd in the alloy is concentrated at the interface with the semiconductor element. This situation can be seen in the SIMS spectrum lol
The third picture was measured A. When Pd is used as the IF transfer metal, the silicide formed is PdzSi.
However, in the XPS spectrum of the silicon interface shown in FIG. 4, P d 3d5. The /2 peak is located approximately at the position of Pd metal. That is, in the first annealing, PdzSi
is not formed and concentrated at the bonding interface remains in a state where the Pd metal contains a small amount of Si.
さらに、最初、のアニールに引き続き温度を３５０℃に
上昇させ一時間アニールすると第２図工段目に示すよう
に、シリコン界面のＰｄはＰｄｚＳｉ に変わる。こ
の時のシリコン界証のＰｄ３ｄＸＰＳスペクトルを第５
図に示す、ＰｄはすべてＰｄｚＳｉ となっている、
さらに引続き温度を上昇させ４５０℃で３Ｑ分間アニー
ルし、第２図の四段目に示すように、スパッタダメージ
を解消しオーミックコンタクトを形成する。これにより
接合界面へ析出するＳｉの量は、配線にＡｌ−１％Ｉｔ
％Ｓｉを用い、４５０℃、玉子分間のアニールによりオ
ーミックコンタクトを形成する場合の１１５以下となっ
た。Further, following the initial annealing, the temperature is raised to 350° C. and annealing is performed for one hour, and as shown in the second step of the drawing, Pd at the silicon interface changes to PdzSi 2 . The Pd3dXPS spectrum of the silicon world certificate at this time is the fifth
In the figure, all Pd is PdzSi,
Further, the temperature is increased and annealing is performed at 450° C. for 3Q minutes to eliminate sputter damage and form an ohmic contact, as shown in the fourth row of FIG. As a result, the amount of Si deposited on the bonding interface is reduced by Al-1%It
%Si and was 115 or less when an ohmic contact was formed by annealing at 450° C. for minutes.
本実施例において、アニールを三段階とせず、第二段階
の３５０℃−時間の７ニールを省略すると、シリコン界
面に一度集中したＰｄがその後の４５０℃三十分玉子７
ニールの際に再度Ａｌ合金膜中に分散してしまい、切れ
目のないＰｄｚＳｉ層を形成することができない。その
ため、アニールは三段階とする必要がある。ただし、ア
ニールの各段階の間に室温まで一度冷却してもＰｄｚＳ
ｉの形成には影響がなく良質のバリヤ層を形成すること
ができる。In this example, if the annealing is not done in three stages and the second stage of 7 hours at 350°C is omitted, the Pd once concentrated on the silicon interface will be removed by the subsequent 30 minutes at 450°C.
During annealing, the PdzSi layer is dispersed again into the Al alloy film, making it impossible to form a seamless PdzSi layer. Therefore, it is necessary to carry out annealing in three stages. However, even once cooled to room temperature between each step of annealing, PdzS
The formation of i is not affected and a high quality barrier layer can be formed.
また、Ａｌ合金膜中に含まれるＰｄとＳｉの比率を原子
比で２：１以下とすると、最初の７二一ルの段階から部
分的にＰｄｚＳｉ 層を界面に形成してしまい、Ｐｄ
１Ｓｉ 層の厚さを均一に制御できない、そのため、Ｐ
ｄとＳｉの含有率は原子比で２：１以上にＳｉを含まな
ければならない。Furthermore, if the ratio of Pd and Si contained in the Al alloy film is 2:1 or less in terms of atomic ratio, a PdzSi layer will be partially formed at the interface from the initial 721 stage, and the Pd
The thickness of the 1Si layer cannot be controlled uniformly, so P
The content of d and Si must be at least 2:1 in atomic ratio.
このようにして形成されたＰｄｚＳｉ 層は、本実施例
では膜厚５０人である。また、第二段階のアニール後Ａ
ｌをエツチングしたシリコン界面の５ｉ２ｐのｘＰＳス
ペクトル（第６図）から明らかなように、界面のシリコ
ンは、すべて、ＰｄｚＳｉになっており、ＰｄｚＳｉ
層が切れ目なくあり、未反応のシリコン界面はない。The PdzSi layer thus formed has a thickness of 50 mm in this example. In addition, after the second stage annealing, A
As is clear from the 5i2p xPS spectrum (Figure 6) of the silicon interface etched with
The layers are continuous and there are no unreacted silicon interfaces.
本発明によれば、半導体素子とＡｌ合金配線の間に遷移
、金属シリサイド層を膜厚の制御性よく形成可能であり
、１００Å以下の膜を均一に形成できるため、半導体装
置の高集積化ができる。According to the present invention, it is possible to form a transition metal silicide layer between a semiconductor element and an Al alloy wiring with good controllability of film thickness, and a film with a thickness of 100 Å or less can be formed uniformly, so that high integration of semiconductor devices is possible. can.
第１図は本発明の一実施例の断面図、第２図は本発明の
実施手順を示す図゛、第３図は素子界面へのＰｄ集中工
程後のＳＩＭＳ分析結果を示す図、第４図は同工程後の
素子界面のＰｄ３ｄＸＰＳスペクトル図、第５図はＰｄ
ｚＳｉ 形成工程後の素子界面のＰｄ３ｄＸＰＳスペク
トル図、第６図は同工程後の素子界面の５ｉ２ｐＸＰＳ
スペクトル図である。
１・・・Ａｌ合金配線、２・・・パッシベーション膜、
３・・・熱酸化５ｉＯｚ膜、４・・・拡散層、５・・・
ＰｄｚＳｉ層、６・・・シリコン基板、７・・・Ａｆｉ
合金膜形成時のスパッタダメ・−ジ、８・・・Ｐｄ層。
＼ご−／
第 １ ロ
冨Ｊ図
スバ・ツタ時間（任意日盛）
第４ｍ
３４５３ヰＯ５５３５０
＊ｇ合１″ｆ−ルキ゛−（ｅＶ）
弔５０
Ｊ４−５３４θ ３３５Ｊθ
Ｓ色合エネル午”−（ｅＶ）
弔６図
１と合エネルキ°’ （ｅＶ）Figure 1 is a cross-sectional view of one embodiment of the present invention, Figure 2 is a diagram showing the implementation procedure of the present invention, Figure 3 is a diagram showing SIMS analysis results after the step of concentrating Pd on the element interface, and Figure 4 The figure is a Pd3dXPS spectrum diagram of the device interface after the same process, and Figure 5 is a Pd3dXPS spectrum diagram of the device interface after the same process.
Pd3dXPS spectrum diagram of the element interface after the zSi formation process, Figure 6 shows the 5i2pXPS spectrum of the element interface after the same process.
It is a spectrum diagram. 1... Al alloy wiring, 2... Passivation film,
3... Thermal oxidation 5iOz film, 4... Diffusion layer, 5...
PdzSi layer, 6... silicon substrate, 7... Afi
Sputter damage during alloy film formation, 8...Pd layer. ＼Go-/ No. 1 Rotomi J Map Suba-Ivy Time (Arbitrary Date) 4th m 3453ヰO55350 *g total 1″f-kilk-(eV) 弔50 J4-534θ 335Jθ S-hue energy ”-(eV ) 6 Figure 1 and combined energy °' (eV)
Claims (1)
ド層を膜形成し、前記遷移金属シリサイド層上にＡｌ合
金配線を形成した半導体素子において、前記遷移金属シ
リサイド層の膜厚が１００Å以下であり、かつ、前記遷
移金属シリサイド層に切れ目がなく前記半導体基板とＡ
ｌ合金配線が直接接することのないように構成したこと
を特徴とする半導体装置。 ２、前記遷移金属シリサイド層としてＰｄ＿２Ｓｉ、Ｍ
ｇ＿２Ｓｉ、ＰｔＳｉ、ＮｉＳｉのいずれかを用い、又
、前Ａｌ合金配線中の前記遷移金属シリサイド層を形成
するのと同種の遷移金属およびシリコンを含有し、その
含有比率が前記遷移金属シリサイド層の組成よりシリコ
ン過剰であることを特徴とする特許請求の範囲第１項記
載の半導体装置。 ３、半導体基板の接合部上に選択的に遷移金属シリサイ
ド層を形成し、前記遷移金属シリサイド層の上にＡｌ合
金配線を形成した半導体素子の製造方法において、前記
Ａｌ合金配線に、前記遷移金属シリサイド層を形成する
のと同種の遷移金属およびシリコンをその含有比率が前
記遷移金属シリサイド層の組成よりシリコン過剰となる
ように含有したものを用い、前記半導体素子上に前記Ａ
ｌ合金配線を形成後、配線中の遷移金属の前記半導体素
子の界面上に集中させる工程、界面に集中した前記遷移
金属をシリサイド化させる工程を経て界面に前記遷移金
属シリサイド層を形成し、その後、オーミックコンタク
トを形成するための熱処理を行うことを特徴とする半導
体装置の製造方法。 ４、前記遷移金属を前記半導体素子の界面に集中させる
工程が１００℃乃至２５０℃の熱処理であり、前記遷移
金属をシリサイド化させる工程が２５０℃乃至４００℃
の熱処理であることを特徴とする特許請求の範囲第３項
記載の半導体装置の製造方法。[Scope of Claims] 1. A semiconductor element in which a transition metal silicide layer is selectively formed on a joint portion of a semiconductor substrate, and an Al alloy wiring is formed on the transition metal silicide layer. The film thickness is 100 Å or less, and there is no break in the transition metal silicide layer and the semiconductor substrate and A
1. A semiconductor device characterized in that it is configured such that l-alloy wiring does not come into direct contact with one another. 2. Pd_2Si, M as the transition metal silicide layer
g_2Si, PtSi, or NiSi is used, and the same type of transition metal and silicon as those forming the transition metal silicide layer in the previous Al alloy wiring are contained, and the content ratio is the same as the composition of the transition metal silicide layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a higher silicon content. 3. A method for manufacturing a semiconductor device in which a transition metal silicide layer is selectively formed on a joint portion of a semiconductor substrate, and an Al alloy wiring is formed on the transition metal silicide layer, wherein the transition metal silicide layer is formed on the Al alloy wiring. Using a transition metal of the same type as that forming the silicide layer and silicon in such a manner that the content ratio thereof is in excess of silicon relative to the composition of the transition metal silicide layer, the A
After forming the alloy wiring, the transition metal silicide layer is formed at the interface through a step of concentrating the transition metal in the wiring on the interface of the semiconductor element, and a step of siliciding the transition metal concentrated at the interface, and then A method of manufacturing a semiconductor device, comprising performing heat treatment to form an ohmic contact. 4. The step of concentrating the transition metal on the interface of the semiconductor element is heat treatment at 100°C to 250°C, and the step of siliciding the transition metal is 250°C to 400°C.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the heat treatment is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26383887A JPH01107569A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26383887A JPH01107569A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107569A true JPH01107569A (en) | 1989-04-25 |
Family
ID=17394927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26383887A Pending JPH01107569A (en) | 1987-10-21 | 1987-10-21 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107569A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03131021A (en) * | 1989-10-16 | 1991-06-04 | Matsushita Electron Corp | Manufacture of semiconductor device |
-
1987
- 1987-10-21 JP JP26383887A patent/JPH01107569A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03131021A (en) * | 1989-10-16 | 1991-06-04 | Matsushita Electron Corp | Manufacture of semiconductor device |
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