JPH01106942U - - Google Patents
Info
- Publication number
- JPH01106942U JPH01106942U JP20026387U JP20026387U JPH01106942U JP H01106942 U JPH01106942 U JP H01106942U JP 20026387 U JP20026387 U JP 20026387U JP 20026387 U JP20026387 U JP 20026387U JP H01106942 U JPH01106942 U JP H01106942U
- Authority
- JP
- Japan
- Prior art keywords
- debugging
- source
- instruction command
- source program
- decoding means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案のデバツグ装置の構成を示すブ
ロツク図、第２図は同装置のラベル情報テーブル
の詳細図、第３図は同装置の行番号アドレス対応
表の詳細図、第４図は同装置のデータ領域情報ア
ドレスの詳細図、第５図はソースプログラムの一
例を示す図である。
１；デバツグ装置、２；ソース解読部、３；イ
ンタープリター制御部、４；デバツグ指示コマン
ド処理部、５；シミユレーシヨン部、６；ソース
プログラム、７；ラベル情報テーブル、８；行番
号アドレス対応表、９；中間コードフアイル、１
０；データ領域情報テーブル、１１；処理行番号
レジスタ、１２；ＣＰＵフラグ情報テーブル、１
３；レジスタ情報テーブル、１４；表示装置。
FIG. 1 is a block diagram showing the configuration of the debugging device of the present invention, FIG. 2 is a detailed diagram of the label information table of the same device, FIG. 3 is a detailed diagram of the line number address correspondence table of the same device, and FIG. 4 is a detailed diagram of the device's line number address correspondence table. FIG. 5 is a detailed diagram of data area information addresses of the same device, and is a diagram showing an example of a source program. 1: Debugging device, 2: Source decoding unit, 3: Interpreter control unit, 4: Debugging instruction command processing unit, 5: Simulation unit, 6: Source program, 7: Label information table, 8: Line number address correspondence table, 9; Intermediate code file, 1
0; Data area information table, 11; Processing line number register, 12; CPU flag information table, 1
3; register information table; 14; display device.
Claims (1)
を解読するソース解読手段と、このソース解読手
段で解読されたソースプログラムがアセンブリ命
令である場合に該アセンブリ命令のマイクロプロ
セツサ上での動作をシミユレートするシミユレー
シヨン手段と、前記ソース解読手段で解読された
ソースプログラムが注釈文である場合に該注釈文
にデバツグ指示コマンドが記述されているときに
そのデバツグ指示コマンドに従つたデバツグ処理
を実行するデバツグ指示コマンド処理手段とを具
備したことを特徴とするデバツグ装置。 Source decoding means for decoding a source program written in assembly language, and simulation means for simulating the operation of assembly instructions on a microprocessor when the source program decoded by the source decoding means is assembly instructions. , a debugging instruction command processing means for executing a debugging process according to the debugging instruction command when the source program decoded by the source decoding means is a comment text and a debugging instruction command is written in the comment text; A debugging device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20026387U JPH01106942U (en) | 1987-12-31 | 1987-12-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20026387U JPH01106942U (en) | 1987-12-31 | 1987-12-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01106942U true JPH01106942U (en) | 1989-07-19 |
Family
ID=31490680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20026387U Pending JPH01106942U (en) | 1987-12-31 | 1987-12-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01106942U (en) |
-
1987
- 1987-12-31 JP JP20026387U patent/JPH01106942U/ja active Pending
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