JPH0110654Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a data transfer signal generation circuit that ensures data transfer from volatile memory to nonvolatile memory when power is cut off.

Recently, microcomputers have been widely used in electronic equipment, industrial machinery, and the like. A microcomputer basically consists of an input interface that converts commands and data input from the outside into a form suitable for internal processing, and a predetermined program that converts the commands and data input via the input interface. A central processing unit (so-called CPU) that performs calculations according to It consists of an interface that converts the data into a form suitable for processing.

By the way, data is sent and received between a microcomputer's CPU and memory via a data bus, but volatile memory such as RAM is usually used, so when the power is cut off, the data is not stored. All data in the memory will be lost, so if there is data that you do not want to lose, we use a method that forcibly transfers the data in the memory to the non-volatile area of the CPU at the same time as the power is turned off.
Figure 1 shows a conventional data transfer circuit used for data transfer when the power is cut off, and 1 is
CPU, 2 is volatile memory composed of RAM, 3
is a data transfer signal, ie, a save signal generation circuit. When the power off signal is input to the save signal generation circuit 3, the save signal generation circuit 3 is activated after a predetermined time delay.
A save signal S is sent from memory 2 to memory 2.
transfers its contents to the non-volatile area of CPU1.
However, in conventional data transfer circuits, CPU1
Since the save signal generating circuit 3 and the save signal generation circuit 3 operate independently, in other words, the save signal S is output regardless of the operation of the CPU, so that the memory contents may not be transferred to the nonvolatile memory of the CPU. In other words, when the save signal S occurs while CPU 1 is accessing memory 2, or conversely, when the contents of memory 2 are
There is a problem in that when the CPU 1 accesses the memory 2 while data is being transferred to the nonvolatile memory of the CPU 1, the data transfer cannot be executed. For example, CPU
Considering the case where the save signal is output while the CPU is accessing volatile memory, the CPU does not access a large amount of data at once, but instead accesses 8-bit data.
A CPU usually accesses each byte (8 bits) multiple times. For that purpose the CPU
If a save signal is output while accessing volatile memory, it is not guaranteed whether the data transferred from volatile memory to nonvolatile memory is the data before access or the data after access, and it is usually a mixture of the two. There is a problem with this.

In consideration of the above points, this idea was designed to ensure that data in volatile memory can be transferred to non-volatile memory when the power is cut off, and a memory access signal indicating whether the volatile memory is being accessed or not. and a power on/off signal indicating the power on/off state, perform a negative AND operation between the transfer trigger signal that triggers data transfer and the memory access signal, and invert the logical product to use it as a transfer trigger signal. A data transfer signal, that is, a save signal is generated based on a trigger signal.

In this way, a save signal will not be output while volatile memory is being accessed, or volatile memory will not be accessed while data is being transferred to non-volatile memory, and data will not be transferred from volatile memory to non-volatile memory. can be transferred reliably. In addition, by delaying the inversion of the NAND mentioned above, even if the power is turned on again during data transfer to non-volatile memory, the volatile memory will not be accessed, and the data will be transferred from volatile memory to non-volatile memory. Transfer can be done reliably.

This invention will be explained below based on the drawings.

FIG. 2 shows an embodiment of the data transfer signal generation circuit according to this invention, in which the CPU 1 and the volatile memory 2 are connected by a data bus.
CPU1 has one input terminal A and one output terminal B
and has. Input terminal A is a reset terminal,
When an "L" signal is input to this terminal A, the CPU 1 is reset. Further, the output terminal B is at the "H" level when the CPU 1 is accessing the memory 2, and is at the "L" level when the CPU 1 is not accessing the memory 2. The memory 2 transfers the memory contents to the nonvolatile area of the CPU 1, that is, the memory, in response to the save signal S from the save signal generation circuit 3.

The input side of the save signal generation circuit 3 includes an AND gate 41 and a transistor 4 whose base is connected to the output terminal of the AND gate 41, whose emitter is grounded, and whose collector is connected to the power supply +B via a resistor R.
2, buffer 43, and one input terminal is CPU
1 input terminal A and the other input terminal is CPU1
and the output terminal is AND gate 4
NAND gate 4 connected to one input terminal of 1
A save signal generation control circuit 4 (encircled by a broken line) consisting of 4 is connected to the save signal generation control circuit 4, and when the save signal generation control circuit 4 outputs a "L" level, it becomes a transfer trigger signal and generates a save signal. A data transfer signal, that is, a save signal is output from the circuit 3. The output signal of the save signal generation control circuit 4 is sent to the input terminal A of the save signal generation circuit 3 and the CPU 1,
It is applied to one input terminal of the NAND gate 44. Note that the power on/off signal is "L" when the power is on, and "H" when the power is off.

Next, the operation of the above circuit will be explained.

Normal operating condition i.e. power on
When the CPU 1 is not accessing the memory 2, the output terminal B of the CPU 1 is at "L" level, so the output level of the NAND gate 44 is "H", and the power on/off signal to the AND gate 41 is "L". Therefore, the output level to the AND gate 41 becomes "L", the transistor 42 becomes non-conductive, and the output of the buffer 43 becomes "H" level.
As a result, the save signal S is not output from the save signal generation circuit 3 and the CPU 1 is not reset.

If the power is cut off now, the power on/off signal becomes "H" level. At this moment, the output level of the NAND gate 44 is "H", so the AND condition of the AND gate 41 is satisfied, and the transistor 42
conducts. As a result, the buffer 43 outputs the save signal S from the save signal generating circuit 3 as a transfer trigger signal of the "L" level, and is also input as a reset signal to the input terminal A of the CPU 1, so that the CPU 1 is reset. Volatile memory 2 saves data based on save signal S.
Transfer to non-volatile memory of CPU1. Assuming that the CPU 1 is accessing the memory 2 when the power is cut off, the level of the output terminal B of the CPU 1 is "H" at this time, so the output level of the NAND gate 44 becomes "L", and the AND gate The output level of 41 remains "L". Therefore, the transistor 42 remains non-conductive, the output level of the buffer 43 remains at "H", the save signal S is not output, and the CPU 1 is not reset. That is, while the CPU 1 is accessing the memory, the save signal S is not output even if the power is cut off, and the CPU 1 is also not reset. For the first time, the transistor 42 becomes conductive and the save signal generation circuit 3 and CPU
An "L" level signal is applied to input terminal A of CPU 1, a save signal S is generated, and CPU 1 is reset.

In this way, if CPU 1 is accessing memory when the power is turned off, then after that access is completed, if it is not accessing, CPU 1 is reset at the same time as the power is turned off, a save signal S is generated, and the data in memory 2 is transferred to the non-volatile memory of CPU 1. be transferred.
Thereafter, when the power supply voltage is supplied, the transistor 42 becomes non-conductive regardless of the state of the CPU 1. As a result, the capacitor C begins to be charged by the current flowing through the resistor R, and the potential of the capacitor C begins to rise with the CR time constant. Since the potential of the capacitor C is below a predetermined level for a certain period of time after power is supplied, the output of the buffer 43 becomes "L" level, and the CPU 1 is reset. However, at this time, the save signal generation circuit 3 does not output the save signal (the save signal generation circuit 3 generates the save signal S when its input changes from the "H" level to the "L" level). The data within is not transferred to the non-volatile memory of CPU1. After that, when the charging potential of capacitor C rises and exceeds a predetermined level, buffer 4
The output of the CPU 3 becomes "H" level, the reset state of the CPU 1 is released, and the memory 2 is accessed. In this way, the CR delay circuit temporarily resets the CPU 1 when the power supply voltage is supplied, and also ensures that data transfer in the memory 2 is not yet completed when the power supply is restored by turning the power on again in the event of a momentary power supply interruption. Since it is possible that the data transfer has not been completed, the CPU 1 is kept in a reset state until the data transfer is completed, and the CPU 1 is prevented from accessing the memory 2 during that time.

In this way, in the above embodiment, even if the power is cut off, neither the save signal S nor the CPU reset signal is output while the CPU is accessing the volatile memory. After the access is completed, a save signal and a CPU reset signal are output, and the data in the volatile memory is transferred to the non-volatile memory based on the save signal S.
Since the CPU is prevented from accessing volatile memory, data in volatile memory can be reliably transferred to non-volatile memory when the power is turned off. Further, in the embodiment, the output of the AND gate 41 has a delay characteristic, but this is not essential to achieving the purpose of the invention.

As explained above, in this invention, when data in volatile memory is transferred to non-volatile memory at the time of power-off, a memory access signal indicating whether the volatile memory is being accessed or not, and a power on/off signal indicating the on/off state of the power supply are used. Input the signal, take the NAND of the transfer trigger signal that triggers data transfer and the memory access signal, take the AND of the NAND and the power on/off signal, invert the AND, and transfer. A trigger signal is used, and a data transfer signal, that is, a save signal is generated based on this transfer trigger signal, so that data transfer can be performed reliably when the power is cut off, and the fatal drawback of data loss due to mistake can be avoided. I can do it.

[Brief explanation of drawings]

FIG. 1 shows a conventional data transfer circuit, and FIG. 2 shows an embodiment of a data transfer signal generating circuit according to this invention. 1... CPU, 2... Volatile memory, 3... Save signal generation circuit, 4... Save signal generation control circuit, 41... AND gate, 42... Transistor, 43... Buffer, 44... NAND gate.

Claims (1)

[Claims for Utility Model Registration] (1) In a data transfer signal generation circuit that generates a data transfer signal for transferring data in a volatile memory to a non-volatile memory when power is cut off, the circuit determines whether or not the volatile memory is being accessed. a first logic circuit that performs a NAND of a memory access signal and a transfer trigger signal; and a second logic circuit that performs an AND of a power on/off signal representing a power on/off state and the first logic circuit. and an inversion circuit that inverts the output of the second logic circuit, the output of the inversion circuit is used as a transfer trigger signal, and a data transfer signal is generated based on the transfer trigger signal. Data transfer signal generation circuit. (2) The data transfer signal generating circuit according to claim 1, wherein the inverting circuit has delay characteristics.