JPH01103973U - - Google Patents
Info
- Publication number
- JPH01103973U JPH01103973U JP19910287U JP19910287U JPH01103973U JP H01103973 U JPH01103973 U JP H01103973U JP 19910287 U JP19910287 U JP 19910287U JP 19910287 U JP19910287 U JP 19910287U JP H01103973 U JPH01103973 U JP H01103973U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- dynamic focus
- switching circuit
- amplitude
- deflection width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は、この考案の一実施例によるダイナミ
ツクフオーカス回路のブロツク図、第２図はこの
考案の振幅切換回路の一実施例を示す回路図、第
３図は従来のダイナミツクフオーカス回路のブロ
ツク図、第４図ａ〜ｃは偏向幅切換時のダイナミ
ツクフオーカス波形説明のための画枠図、偏向電
流波形図、パラボラ波形図である。
図において、１は偏向回路、２は偏向コイル、
３はパラボラ波発生回路、４は振幅調整回路、５
は増幅回路、６はダイナミツクフオーカス回路、
７は加算回路、８は偏向幅切換回路、１４は振幅
切換回路、１５は第１のエミツタフオロア接続ト
ランジスタ、１６は第１のエミツタ抵抗、１７は
第１の振幅調整抵抗、１８は第２のエミツタフオ
ロア接続トランジスタ、１９は振幅切換スイツチ
、２０はバイアス抵抗、２１はスイツチング用ト
ランジスタ、２２は第２の振幅調整抵抗、２３は
第３の振幅調整抵抗、２４は第２のエミツタ抵抗
を示す。尚、図中、同一符号は同一、又は相当部
分を示す。
Fig. 1 is a block diagram of a dynamic focus circuit according to an embodiment of this invention, Fig. 2 is a circuit diagram showing an embodiment of an amplitude switching circuit of this invention, and Fig. 3 is a diagram of a conventional dynamic focus circuit. The block diagram of the circuit, FIGS. 4a to 4c, is a picture frame diagram, a deflection current waveform diagram, and a parabolic waveform diagram for explaining the dynamic focus waveform at the time of switching the deflection width. In the figure, 1 is a deflection circuit, 2 is a deflection coil,
3 is a parabolic wave generation circuit, 4 is an amplitude adjustment circuit, 5
is an amplifier circuit, 6 is a dynamic focus circuit,
7 is an adder circuit, 8 is a deflection width switching circuit, 14 is an amplitude switching circuit, 15 is a first emitter follower connection transistor, 16 is a first emitter resistor, 17 is a first amplitude adjustment resistor, and 18 is a second emitter follower. 19 is a connection transistor, 20 is a bias resistor, 21 is a switching transistor, 22 is a second amplitude adjustment resistor, 23 is a third amplitude adjustment resistor, and 24 is a second emitter resistor. In the drawings, the same reference numerals indicate the same or equivalent parts.
補正 昭６３．３．３１
図面の簡単な説明を次のように補正する。
明細書中第７頁第１５行から第１７行に「第４
図ａ〜ｃ…波形図である。」とあるのを次のとお
り訂正する。「第４図は偏向幅切換時のダイナミ
ツクフオーカス波形を説明するための図である。
」Amendment: March 31, 1981 The brief description of the drawing is amended as follows. In the specification, from page 7, line 15 to line 17, “4th
Figures a to c are waveform diagrams. ” is corrected as follows. ``Figure 4 is a diagram for explaining the dynamic focus waveform when switching the deflection width.
”
Claims (1)
又はビデオプロジエクシヨン装置のダイナミツク
フオーカス回路において、上記偏向幅切換回路に
連動してダイナミツクフオーカス補正信号の振幅
を切換える振幅切換回路を備えたことを特徴とす
るダイナミツクフオーカス回路。 A television receiver having a deflection width switching circuit,
Alternatively, a dynamic focus circuit for a video projection device, comprising an amplitude switching circuit that switches the amplitude of a dynamic focus correction signal in conjunction with the deflection width switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19910287U JPH01103973U (en) | 1987-12-25 | 1987-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19910287U JPH01103973U (en) | 1987-12-25 | 1987-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01103973U true JPH01103973U (en) | 1989-07-13 |
Family
ID=31489571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19910287U Pending JPH01103973U (en) | 1987-12-25 | 1987-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01103973U (en) |
-
1987
- 1987-12-25 JP JP19910287U patent/JPH01103973U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01103973U (en) | ||
| JPS58565U (en) | Image quality adjustment circuit | |
| JPH0216661U (en) | ||
| JPH03130668U (en) | ||
| JP2814561B2 (en) | Dynamic focus circuit | |
| JPS63198285U (en) | ||
| JPS6342613Y2 (en) | ||
| JPH02137181U (en) | ||
| JPS5838684Y2 (en) | Vertical blanking circuit | |
| JPH0485967U (en) | ||
| JPS5910843Y2 (en) | vertical deflection circuit | |
| JPS61146065U (en) | ||
| JPH0445295Y2 (en) | ||
| JPS58158572U (en) | television receiver | |
| JPH0485964U (en) | ||
| JPH0182554U (en) | ||
| JPS59140580U (en) | Left and right pincushion distortion correction circuit | |
| JPS61146066U (en) | ||
| JPS5811369U (en) | Automatic black level correction circuit for television receivers | |
| JPS6331669U (en) | ||
| JPS5871265U (en) | Linearity correction circuit | |
| JPS58158561U (en) | CRT display device pincushion distortion correction circuit | |
| JPH0232274U (en) | ||
| JPS604084U (en) | White balance adjustment circuit for color television receivers | |
| JPS58123673U (en) | Screen distortion correction circuit for television receivers |